| Opening Keynote 2 |
| The Cyber-Physical Metaverse ‐ Where Digital Twins and Humans Come Together | |  |
| Dirk Elias, Dirk Ziegenbein, Philipp Mundhenk, Arne Hamann, Anthony Rowe |
| Focus session: Embracing uncertainty and exploring non-determinism for efficient implementations of Machine Learning models |
| Binary ReRAM-based BNN first-layer implementation | | |
| Mona Ezzadeen, Atreya Majumdar, Sigrid Thomas, Jean-Philippe Noel, Bastien Giraud, Marc Bocquet, Francois Andrieu, Damien Querlioz and Jean-Michel Portal |
| Scalable Spintronics-based Bayesian Neural Network for Uncertainty Estimation | | |
| Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume PRENAT, Lorena Anghel and Mehdi Tahoori |
| Countering Uncertainties in In-Memory-Computing Platforms with Statistical Training, Accuracy Compensation and Recursive Test | | |
| Amro Eldebiky, Grace Li Zhang and Bing Li |
| ASD technical session: Designing Fault tolerant and resilient autonomous systems |
| MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles | | |
| Yu-Shun Hsiao, Zishen Wan, Tianyu Jia, Radhika Ghosal, Abdulrahman Mahmoud, Arijit Raychowdhury, David Brooks, Gu-Yeon Wei and Vijay Janapa Reddi |
| Phalanx: Failure-Resilient Truck Platooning System | | |
| Changjin Koo, jaegeun park, Ahn TaeWook, Hongsuk Kim, Jong-Chan Kim and Yongsoon Eun |
| Efficient Software-Implemented HW Fault Tolerance for TinyML Inference in Safety-critical Applications | | |
| Uzair Sharif, Daniel Mueller-Gritschneder, Rafael Stahl and Ulf Schlichtmann |
| Formal Analysis of Timing Diversity for Autonomous Systems | | |
| Anika Christmann, Robin Hapka and Rolf Ernst |
| Multi-partner projects |
| NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips | | |
| Xabier Iturbe, Nassim Abderrahmane, Jaume Abella, Sergi Alcaide, Eric Beyne, Henri-Pierre Charles, Christelle Charpin-Nicolle, Lars Chittka, Angélica Dávila, Arne Erdmann, Carles Estrada, Ander Fernández, Anna Fontanelli, José Flich, Gianluca Furano, Alejandro Hernán Gloriani, Erik Isusquiza, Radu Grosu, Carles Hernández, Daniele Ielmini, David Jackson, Maha Kooli, Nicola Lepri, Bernabé Linares-Barranco, Jean-Loup Lachese, Eric Laurent, Menno Lindwer, Frank Linsenmaier, Mikel Luján, Karel Masařík, Nele Mentens, Orlando Moreira, Chinmay Nawghane, Luca Peres, Jean-Philippe Noel, Arash Pourtaherian, Christoph Posch, Peter Priller, Zdenek Prikryl, Felix Resch, Oliver Rhodes, Todor Stefanov, Moritz Storring, Michele Taliercio, Rafael Tornero, Marcel van de Burgwal, Geert van der Plas, Elisa Vianello, and Pavel Zaykov |
| Optimizing Industrial Applications for Heterogeneous HPC Systems: The OPTIMA Project | | |
| Dimitris Theodoropoulos, Oliver Michel, PAVLOS MALAKONAKIS, Konstantinos Georgopoulos, Giovanni Isotton, Dionisios Pnevmatikatos, Ioannis Papaefstathiou, Gino Perna, Panagiotis Miliadis, Mariza Zanotti, Chloe Alverti, Aggelos Ioannou, Max Engelen, Valeria Bartsch, Mathias Balzer and Iakovos Mavroidis |
| Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors | | |
| Jens Trommer, Niladri Bhattacharjee, Thomas Mikolajick, Sebastian Huhn, Marcel Merten, Mohammed E. Djeridane, Muhammad Hassan, Rolf Drechsler, Shubham Rai, Nima Kavand, Armin Darjani, Akash Kumar, Violetta Sessi, Maximilian Drescher, Sabine Kolodinski and Maciej Wiatr |
| SAFEXPLAIN: Safe and Explainable Critical Embedded Systems Based on AI | | |
| Jaume Abella, Jon Perez, Cristofer Englund, Bahram Zonooz, Gabriele Giordana, Carlo Donzella, Francisco J Cazorla, Enrico Mezzetti, Isabel Serra, Axel Brando, Irune Agirre, Fernando Eizaguirre, Thanh Hai Bui, Elahe Arani, Fahad Sarfraz, Ajay Balasubramaniam, Ahmed Badar, Ilaria Bloise, Lorenzo Feruglio, Ilaria Cinelli, Davide Brighenti and Davide Cunial |
| The FORA European Training Network on Fog Computing for Robotics and Industrial Automation | | |
| Mohammadreza Barzegaran and Paul Pop |
| PetaOps/W edge-AI μProcessors: Myth or reality? | | |
| Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Friedemann Zenke, Frank Gurkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, Sam Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu and Henk Corporaal |
| VE-FIDES: Designing Trustworthy Supply Chains Using Innovative Fingerprinting Implementations | | |
| Bernhard Lippmann, Joel Hatsch, Stefan Seidl, Detlef Houdeau, Niranjana Papagudi Subrahmanyam, Daniel Schneider, Malek Safieh, Anne Passarelli, Aliza Maftun, Michaela Brunner, Tim Music, Michael Pehl, Tauseef Siddiqui, Ralf Brederlow, Ulf Schlichtmann, Bjoern Driemeyer, Maurits Ortmanns, Robert Hesselbarth and Matthias Hiller |
| Late Breaking Results: novel computing paradigms |
| Digital Emulation of Oscillator Ising Machines | | |
| Shreesha Sreedhara, Jaijeet Roychowdhury, Joachim Wabnig and Pavan Koteshwar Srinath |
| Energy-Efficient Bayesian Inference Using Near-Memory Computation with Memristors | | |
| Clément Turck, Kamel-Eddine Harabi, Tifenn Hirtzlin, Elisa Vianello, Raphaël Laurent, Jacques Droulez, Pierre Bessière, Jean-Michel Portal, Marc Bocquet and Damien Querlioz |
| Towards a Robust Multiply-Accumulate Cell in Photonics using Phase-Change Materials | | |
| Raphael Cardoso, Clément Zrounba, Mohab Abdalla, Paul Jimenez, Mauricio Gomes, Benoît Charbonnier, Fabio Pavanello, Ian O'Connor and S�bastien Le Beux |
| Lightspeed Binary Neural Networks using Optical Phase-Change Materials | | |
| Taha Shahroodi, Raphael Cardoso, Mahdi Zahedi, Stephan Wong, Alberto Bosio, Ian O'Connor and Said Hamdioui |
| Real-Time Fully Unsupervised Domain Adaptation for Lane Detection in Autonomous Driving | | |
| Kshitij Bhardwaj, Zishen Wan, Arijit Raychowdhury and Ryan Goldhahn |
| A Linear-Time, Optimization-Free, and Edge Device-Compatible Hypervector Encoding | | |
| Sercan Aygun, M. Hassan Najafi and Mohsen Imani |
| Memory-centric computing |
| Minimizing Communication Conflicts in Network-On-Chip Based Processing-In-Memory Architecture | | |
| Hanbo Sun, Tongxin Xie, Zhenhua Zhu, Guohao Dai, Huazhong Yang and Yu Wang |
| Hierarchical Non-Structured Pruning for Computing-In-Memory Accelerators with Reduced ADC Resolution Requirement | | |
| Wenlu Xue, Jinyu Bai, Sifan Sun and Wang Kang |
| PIC-RAM: Process-Invariant Capacitive Multiplier Based Analog In Memory Computing in 6T SRAM | | |
| Kailash Prasad, Aditya Biswas, Arpita Sanjay Kabra and Joycee Mekie |
| Logic synthesis and verification |
| Computing Effective Resistances on Large Graphs Based on Approximate Inverse of Cholesky Factor | | |
| Zhiqiang Liu and Wenjian Yu |
| Fanout-Bounded Logic Synthesis for Emerging Technologies - A Top-Down Approach | | |
| Dewmini Sudara Marakkalage and Giovanni De Micheli |
| Synthesis with Explicit Dependencies | | |
| Priyanka Golia, Subhajit Roy and Kuldeep S Meel |
| ASD special session: Information Processing Factory, Take Two on Self-Aware Systems of MPSoCs |
| Information Processing Factory 2.0 ‐ Self-awareness for Autonomous Collaborative Systems | | |
| Nora Sperling, Alex Bendrick, Rolf Ernst, Bryan Donyanavard, Markus Maurer, Oliver Lenke, Anmol Prakash Surhonne, Andreas Herkersdorf, Walaa Amer, Caio Batista de Melo, Ping-Xiang Chen, Quang Anh Hoang, Rachid Karami, Biswadip Maity, Paul Nikolian, Mariam Rakka, Dongjoo Seo, Saehanseul Yi, Minjun Seo, Nikil Dutt and Fadi Kurdahi |
| Security of emerging technologies and machine learning |
| Privacy-Preserving Neural Representation for Brain-Inspired Learning | | |
| Javier Roberto Rubalcava-Cortes, Alejandro , Hernandez Cano, Alejandra Citlalli Pacheco Tovarm, Farhad Imani, Rosario Cammarota and Mohsen Imani |
| Exploiting Short Application Lifetimes for Low Cost Hardware Encryption in Flexible Electronics | | |
| Nathaniel L. Bleier, Muhammad Husnain Mubarik, Suman Balaji, Francisco Rodriguez, Antony Sou, Scott White and Rakesh Kumar |
| Attacking ReRAM-based Architectures using Repeated Writes | | |
| Biresh Kumar Joardar and Krishnendu Chakrabarty |
| Security Evaluation of a Hybrid CMOS/MRAM Ascon Hardware Implementation | | |
| Nathan Roussel, Olivier Potin, Jean-Max Dutertre and Jean-Baptiste Rigaud |
| MANTIS: Machine Learning-Based Approximate ModeliNg of RedacTed Integrated CircuitS | | |
| Chaitali Sathe, Yiorgos Makris and Benjamin Carrion Schaefer |
| Long Range Detection of Emanation from HDMI Cables Using CNN and Transfer Learning | | |
| Md Faizul Bari, Meghna Roy Chowdhury and Shreyas Sen |
| Adversarial Attack on Hyperdimensional Computing-based NLP Applications | | |
| Sizhe Zhang, Zhao Wang and Xun Jiao |
| A Practical Remote Power Attack on Machine Learning Accelerators in Cloud FPGAs | | |
| Shanquan Tian, Shayan Moini, Daniel Holcomb, Russell Tessier and Jakub Szefer |
| Scalable Scan-Chain-Based Extraction of Neural Network Models | | |
| Shui Jiang, Seetal Potluri and Tsung-Yi Ho |
| Comprehensive Analysis of Hyperdimensional Computing against Gradient Based Attacks | | |
| Hamza Errahmouni Barkam, SungHeon Eavn Jeong, Calvin Yeung, Zhuowen Zou, Xun Jiao and Mohsen Imani |
| Logical and physical analysis and design |
| Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin Accessibility | | |
| Jooyeon Jeong, Sehyeon Chung, Kyeongrok Jo and Taewhan Kim |
| Center-of-delay: a new metric to drive timing margin against spatial variation in complex SOCs | | |
| Christian Lutkemeyer and Anton Belov |
| A Novel Delay Calibration Method Considering Interaction between Cells and Wires | | |
| Leilei Jin, Jia Jie Xu, Wenjie Fu, Hao Yan, Xiao Shi, Ming Ling and Longxing Shi |
| Rethinking NPN Classification from Face and Point Characteristics of Boolean Functions | | |
| Jiaxi Zhang, Shenggen Zheng, Liwei Ni, Huawei Li and Guojie Luo |
| Exact Synthesis Based on Semi-Tensor Product Circuit Solver | | |
| Hongyang Pan and Zhufei Chu |
| An Effective and Efficient Heuristic for Rational-Weight Threshold Logic Gate Identification | | |
| Ting Yu Yeh, Yueh Cho and Yung Chih Chen |
| Fast STA Graph Partitioning Framework for Multi-GPU Acceleration | | |
| Guannan Guo, Tsung-Wei Huang and Martin Wong |
| TOFU: A Two-Step Floorplan Refinement Framework for Whitespace Reduction | | |
| Shixiong Kai, Chak-Wa Pui, Fangzhou Wang, Jiang Shougao, Bin Wang, Yu Huang and Jianye Hao |
| Routability Prediction using Deep Hierarchical Classification and Regression | | |
| Daeyeon Kim, Jakang Lee and Seokhyeong Kang |
| Efficient Design Rule Checking with GPU Acceleration | | |
| Wei Zhong, Zhenhua Feng, Zhuolun He, Weimin Wang, Yuzhe Ma and Bei Yu |
| Mitigating Layout Dependent Effect-induced Timing Risk in Multi-Row-Height Detailed Placement | | |
| Li-Chen Wang and Shao-Yun Fang |
| Two-stage PCB Routing Using Polygon-based Dynamic Partitioning and MCTS | | |
| Youbiao He, Hebi Li, Ge Luo and Forrest Sheng Bao |
| DeepTH: Chip Placement with Deep Reinforcement Learning Using a Three-Head Policy Network | | |
| Dengwei Zhao, Shuai Yuan, Yanan Sun, Shikui Tu and Lei Xu |
| Reconfigurable architectures, machine learning and circuit design |
| Towards Efficient Neural Network Model Parallelism on Multi-FPGA Platforms | | |
| David Rodriguez Agut, Rafael Tornero and Jose Flich |
| High-accuracy Low-power Reconfigurable Architectures for Decomposition-based Approximate Lookup Table | | |
| Xingyue Qian, Chang Meng, Xiaolong Shen, Junfeng Zhao, Leibin Ni and Weikang Qian |
| FPGA Acceleration of GCN in Light of the Symmetry of Graph Adjacency Matrix | | |
| Gopikrishnan Raveendran Nair, Han-sok Suh, Mahantesh Halappanavar, Frank Liu, Jae-sun Seo and Yu Cao |
| PR-ESP: An Open-Source Platform for Design and Programming of Partially Reconfigurable SoCs | | |
| Biruk Seyoum, Davide Giri, Kuan-Lin Chiu, Bryce Natter and Luca Carloni |
| ISOP: Machine Learning Assisted Inverse Stack-Up Optimization for Advanced Package Design | | |
| Hyunsu Chae, Bhyrav Mutnury, Keren Zhu, Doug Wallace, Doug Winterberg, Daniel de Araujo, Jay Reddy, Adam Klivans and David Z. Pan |
| Fast and Accurate Wire Timing Estimation Based on Graph Learning | | |
| Yuyang Ye, Tinghuan Chen, Yifei Gao, Hao Yan, Bei Yu and Longxing Shi |
| DTOC: integrating Deep-learning driven Timing Optimization into state-of-the-art Commercial EDA tool | | |
| Kyungjoon Chang, Heechun Park, Jaehoon Ahn, Kyu-Myung Choi and Taewhan Kim |
| RL-Legalizer: Reinforcement Learning-based Cell Priority Optimization in Mixed-Height Standard Cell Legalization | | |
| Sung-Yun Lee, Seonghyeon Park, Daeyeon Kim, Minjae Kim, Tuyen P. Le and Seokhyeong Kang |
| Neural Network on the Edge: Efficient and Low Cost FPGA Implementation of Digital Predistortion in MIMO Systems | | |
| Yiyue Jiang, Andrius Vaicaitis, John Dooley and Miriam Leeser |
| Quantised Neural Network Accelerators for Low-Power IDS in Automotive Networks | | |
| Shashwat Khandelwal, Anneliese Walsh and Shreejith Shanker |
| Focus session: The Past, Present and Future of Chiplets |
| The Next Era for Chiplet Innovation | | |
| Gabriel Loh and Raja Swaminathan |
| Achieving Datacenter-scale Performance through Chiplet-based Manycore Architectures | | |
| Harsh Sharma, Sumit Mandal, Jana Doppa, Umit Ogras and Partha Pratim Pande |
| Machine Learning Accelerators in 2.5D Chiplet Platforms with Silicon Photonics | | |
| Febin Sunny, Ebadollah Taheri, Mahdi Nikdast and Sudeep Pasricha |
| ASD technical session: Autonomy for systems perception, control and optimization |
| Autonomous Hyperloop Control Architecture Design using MAPE-K | | |
| Julian Demicoli, Laurin Prenzel and Sebastian Steinhorst |
| Reinforcement-Learning-Based Job-Shop Scheduling for Intelligent Intersection Management | | |
| Shao-Ching Huang, Kai-En Lin, Cheng-Yen Kuo, Li-Heng Lin, Muhammed Omer Sayin and Chung-Wei Lin |
| Bio-inspired Autonomous Exploration Policies with CNN-based Object Detection on Nano-drones | | |
| Lorenzo Lamberti, Luca Bompani, Victor Javier Kartsch Morinigo, Manuele Rusci, Daniele Palossi and Luca Benini |
| Butterfly Effect Attack: Tiny and Seemingly Unrelated Perturbations for Object Detection | | |
| Nguyen Anh Vu Doan, Arda Yueksel and Chih-Hong Cheng |
| ASD Panel session: Autonomous Systems Design as a Driver of Innovation? |
| Autonomous System Design Session ‐ Benefits, Challenges and Risks in Various Application Domains | | |
| Rasmus Adler |
| Testing |
| Device-Aware Test for Back-Hopping Defects in STT-MRAMs | | |
| Sicong Yuan, Mottaqiallah Taouil, Moritz Fieback, Hanzhi Xun, Erik Jan Marinissen, Gouri Kar, Siddharth Rao, Sebastien Couet and Said Hamdioui |
| CorrectNet: Robustness Enhancement of Analog In-Memory Computing for Neural Networks by Error Suppression and Compensation | | |
| Amro Eldebiky, Grace Li Zhang, Georg Bocherer, Bing Li and Ulf Schlichtmann |
| Assessing Convolutional Neural Networks Reliability through Statistical Fault Injections | | |
| Annachiara Ruospo, Gabrile Gavarini, Corrado De Sio, Juan David Guerrero Balaguera, Luca Sterpone, Matteo Sonza Reorda, Ernesto Sanchez, Riccardo Mariani, Joseph Aribido and Jyotika Athavale |
| Machine Learning techniques for embedded systems |
| PRADA: Point Cloud Recognition Acceleration via Dynamic Approximation | | |
| Zhuoran Song, Heng Lu, Gang Li, Li Jiang, Naifeng Jing and Xiaoyao Liang |
| Federated Learning with Heterogeneous Models for On-device Malware Detection in IoT Networks | | |
| sanket shukla, Setareh Rafatirad, Houman Homayoun and Sai Manoj Pudukotai Dinakarrao |
| Genetic Algorithm-based Framework for Layer-Fused Scheduling of Multiple DNNs on Multi-core Systems | | |
| Sebastian Karl, Arne Symons, Nael Fasfous and Marian Verhelst |
| Benchmarking and verification |
| Benchmarking Large Language Models for Automated Verilog RTL Code Generation | | |
| Shailja Thakur, Baleegh Ahmad, Zhenxing Fan, Hammond Pearce, Benjamin Tan, Ramesh Karri, Brendan Dolan-Gavitt and Siddharth Garg |
| Processor Verification using Symbolic Execution: A RISC-V Case-Study | | |
| Niklas Bruns, Vladimir Herdt and Rolf Drechsler |
| Perspector: Benchmarking Benchmark Suites | | |
| Sandeep Kumar, Abhisek Panda and Smruti R. Sarangi |
| From synthesis to application |
| Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-Core Processor | | |
| Marco Bertuletti, Yichao Zhang, Alessandro Vanelli-Coralli and Luca Benini |
| Narrowing The Synthesis Gap: Academic FPGA Synthesis Is Catching Up With The Industry | | |
| Benjamin Lukas Cajus Barzen, Arya Reais-Parsi, Eddie Hung, Minwoo Kang, Alan Mishchenko, Jonathan W. Greene and John Wawrzynek |
| SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility | | |
| Haoyi Zhang, Xiaohan Gao, Haoyang Luo, Jiahao Song, Xiyuan Tang, Junhua Liu, Yibo Lin, Runsheng Wang and Ru Huang |
| Multi-partner projects |
| Securing a RISC-V architecture: A dynamic approach | | |
| Sebastien Pillement, Maria Mendez Real, Juliette Pottier, Thomas Nieddu, Bertrand Le Gall, Sébastien Faucou, Jean-Luc Béchennec, Mikaël Briday, Sylvain Girbal, Jimmy Le Rhun, Olivier Gilles, Daniel Gracia Pérez, Andre Sintzoff and Jean-Roch Coulon |
| The ZuSE-KI-Mobil AI Accelerator SoC: Overview and a Functional Safety Perspective | | |
| Fabian Kempf, Julian Hoefer, Tanja Harbaum, Juergen Becker, Nael Fasfous, Alexander Frickenstein, Hans-Jörg Vögel, Simon Friedrich, Robert Wittig, Emil Matus, Gerhard Fettweis, Matthias Lueders, Holger Blume, Karl-Heinz Eickel, Darius Grantz, Jens Benndorf, Martin Zeller and Dietmar Engelke |
| ZuSE-KI-AVF: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving | | |
| Gia Bao Thieu, Sven Gesper, Guillermo Payá Vayá, Christoph Riggers, Oliver Renke, Till Fiedler, Jakob Marten, Tobias Stuckenberg, Holger Blume, Christian Weis, Lukas Steiner, Chirag Sudarshan, Norbert Wehn, Lennart Reimann, Rainer Leupers, Michael Beyer, Daniel Kohler, Alisa Jauch, Jan Micha Bormann, Setareh Jaberansari, Tim Berthold, Meinolf Blawat, Markus Kock, Gregor Schewior, Jens Benndorf, Frederik Kautz, Hans-Martin Bluethgen and Christian Sauer |
| EuFRATE: European FPGA Radiation-hardened Architecture for Telecommunications | | |
| Ludovica Bozzoli, Antonino Catanese, Emilio Fazzoletto, Eugenio Scarpa, Diana Goehringer, Sergio A. Pertuz, Lester Kalms, Cornelia Wulf, Najdet Charaf, Luca Sterpone, Sarah Azimi, Daniele Rizzieri, Salvatore Gabriele La Greca, David Merodio Codinachs and Stephen King |
| The SERRANO platform: Stepping towards seamless application development & deployment in the heterogeneous edge-cloud continuum | | |
| Aggelos Ferikoglou, Argyris Kokkinis, Dimitrios Danopoulos, Ioannis Oroutzoglou, Anastasios Nanos, Stathis Karanastasis, Marton Sipos, Javad Fadaie Ghotbi, Juan Jose Vegas Olmos, Dimosthenis Masouros and Kostas Siozios |
| Evaluation of heterogeneous AIoT Accelerators within VEDLIoT | | |
| Rene Griessl, Florian Porrmann, Nils Kucza, Kevin Mika, Jens Hagemeyer, Martin Kaiser, Mario Porrmann, Marco Tassemeier, Marcel Flottmann, Fareed Mohammad Qararyah, Muhammad Waqar Azhar, Pedro Trancoso, Daniel Odman, Karol Gugala and Grzegorz Latosinksi |
| SPHERE-DNA: Privacy-Preserving Federated Learning for eHealth | | |
| Jari Nurmi, Yinda Xu, Jani Boutellier and Bo Tan |
| ASD focus session 1: Autonomy-driven Emerging Directions in Software-defined Vehicles |
| Autonomy-driven Emerging Directions in Software-defined Vehicles | | |
| Unmesh Bordoloi, Samarjit Chakraborty, Prachi Joshi, Markus Jochim, Arvind Raghuraman and S Ramesh |
| Hardware accelerators and memory subsystems |
| UVMMU: Hardware-Offloaded Page Migration for Heterogeneous Computing | | |
| Jihun Park, Donghun Jeong and Jungrae Kim |
| ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining | | |
| Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos and Dionisios Pnevmatikatos |
| FastRW: A Dataflow-Efficient and Memory-Aware Accelerator for Graph Random Walk on FPGAs | | |
| Yingxue Gao, teng wang, Lei Gong, Chao Wang, Xi Li and Xuehai Zhou |
| Twin ECC: A Data Duplication Based ECC for Strong DRAM Error Resilience | | |
| Hyeong Kon Bae, Myung Jae Chung, Young-Ho Gong and Sung Woo Chung |
| Aiding to Multimedia Accelerators: A Hardware Design for Efficient Rounding of Binary Floating Point Numbers | | |
| MAHENDRA RATHOR, Vishesh Mishra and Urbi Chatterjee |
| CRSPU: Exploit Commonality of Regular Sparsity to Support Various Convolutions on Systolic Arrays | | |
| Jianchao Yang, Mei Wen, Junzhong Shen, Yasong Cao, Minjin Tang, Renyu Yang, Xin Ju and Chunyuan Zhang |
| CLAP: Locality Aware and Parallel Triangle Counting with Content Addressable Memory | | |
| Tianyu Fu, Chiyue Wei, Zhenhua Zhu, Shang Yang, Zhongming Yu, Guohao Dai, Huazhong Yang and Yu Wang |
| Atomic but Lazy Updating with Memory-mapped Files for Persistent Memory | | |
| Qisheng Jiang, Lei Jia and Chundong Wang |
| Out-of-Step Pipeline for Gather/Scatter Instructions | | |
| Yi Ge, Katsuhiro Yoda, Makiko Ito, Toshiyuki Ichiba, Takahide Yoshikawa, Ryota Shioya and Masahiro Goshima |
| MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster | | |
| Samuel Riedel, Gua Hao Khov, Sergio Mazzola, Matheus Cavalcante, Renzo Andri and Luca Benini |
| Novel Efficient Synonym Handling Mechanism for Virtual-real Cache Hierarchy | | |
| Varun Venkitaraman, Ashok Sathyan, Shrihari P. Deshmukh and Virendra Singh |
| TURBULENCE: Complexity-effective Out-of-order Execution on GPU with Distance-based ISA | | |
| Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai and Ryota Shioya |
| Resource-aware computing |
| Efficient Hyperdimensional Learning with Trainable, Quantizable, and Holistic Data Representation | | |
| Jiseung Kim, Hyunsei Lee, Mohsen Imani and Yeseong Kim |
| Smart Knowledge Transfer-based Runtime Power Management | | |
| Lin Chen, Xiao Li, Fan Jiang, Chengeng Li and Jiang Xu |
| REDRAW: Fast and Efficient Hardware Accelerator with REDuced Reads And Writes for 3D UNet | | |
| Tom Glint, Manu Awasthi and Joycee Mekie |
| Temperature-Aware Sizing of Multi-Chip Module Accelerators for Multi-DNN Workloads | | |
| Prachi Shukla, Derrick Aguren, Tom Burd, Ayse Coskun and John Kalamatianos |
| Jumping Shift: A Logarithmic Quantization Method For Low-Power CNN Acceleration | | |
| Longxing Jiang, David Aledo and Rene van Leuken |
| Thermal Management for S-NUCA Many-Cores via Synchronous Thread Rotations | | |
| Yixian Shen, Sobhan Niknam, Anuj Pathania and Andy D. Pimentel |
| Proteus: HLS-based NoC Generator and Simulator | | |
| Abhimanyu Rajeshkumar Bambhaniya, Yangyu Chen, FNU Anshuman, Rohan Banerjee and Tushar Krishna |
| MOELA: A Multi-Objective Evolutionary/Learning Design Space Exploration Framework for 3D Heterogeneous Manycore Platforms | | |
| Sirui Qi, Yingheng Li, Sudeep Pasricha and Ryan Gary Kim |
| Developing an Ultra-low Power RISC-V Processor for Anomaly Detection | | |
| Jina Park, Eunjin Choi, Kyungwon Lee, Jae-Jin Lee, Kyuseung Han and Woojoo Lee |
| Extended Abstract: Monitoring-based Thermal Management for Mixed-Criticality Systems | | |
| Marcel Mettler, Martin Rapp, Heba Khdr, Daniel Mueller-Gritschneder, Joerg Henkel and Ulf Schlichtmann |
| A Lightweight Congestion Control Technique for NoCs with Deflection Routing | | |
| Shruti Yadav Narayana, Sumit K. Mandal, Raid Ayoub, Micheal Kishinevsky and Umit Ogras |
| Test methods and dependability |
| Improving Reliability of Spiking Neural Networks through Fault Aware Threshold Voltage Optimization | | |
| Ayesha Siddique and Khaza Anuarul Hoque |
| Automated and Agile Design of Layout Hotspot Detector via Neural Architecture Search | | |
| Zihao Chen, Fan Yang, Li Shang and Xuan Zeng |
| Upheaving Self-Heating Effects from Transistor to Circuit Level using Conventional EDA Tool Flows | | |
| Florian Klemme, Sami Salamin and Hussam Amrouch |
| Built-in Self-Test and Built-in Self-Repair Strategies Without Golden Signature for Computing in Memory | | |
| Yu-Chih Tsai, Wen-chien Ting, Chia-Chun Wang, chia-cheng chang and Ren-Shuo Liu |
| Security-Aware Approximate Spiking Neural Network | | |
| Syed Tihaam Ahmad, Ayesha Siddique and Khaza Anuarul Hoque |
| BAFFI: a bit-accurate fault injector for improved dependability assessment of FPGA prototypes | | |
| Ilya Tuzov, David de Andres, Juan-Carlos Ruiz and Carles Hernandez |
| A Novel Fault-Tolerant Architecture for Tiled Matrix Multiplication | | |
| Sandeep Bal, Chandra Sekhar Mummidi, Victor da Cruz Ferreira, Sudarshan Srinivasan and Sandip Kundu |
| Reduce: A Framework for Reducing the Overheads of Fault-Aware Retraining | | |
| Muhammad Abdullah Hanif and Muhammad Shafique |
| Bitstream-Level Interconnect Fault Characterization for SRAM-based FPGAs | | |
| Christian Fibich, Martin Horauer and Roman Obermaisser |
| Compact test pattern generation for multiple faults in deep neural networks | | |
| Dina A. Moussa, Michael Hefenbrock and Mehdi Tahoori |
| READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction | | |
| Zuodong Zhang, Meng Li, Yibo Lin, Runsheng Wang and Ru Huang |
| Robust Resistive Open Defect Identification Using Machine Learning with Efficient Feature Selection | | |
| Zahra Paria Najafi-Haghi, Florian Klemme, Hanieh Jafarzadeh, Hussam Amrouch and Hans-Joachim Wunderlich |
| Modelling, verification and timing analysis of cyber-physical systems |
| ImpactTracer: Root Cause Localization in Microservices Based on Fault Propagation Modeling | | |
| Ru Xie, Jing Yang, Jingying Li and Liming Wang |
| PumpChannel: An Efficient and Secure Communication Channel for Trusted Execution Environment on ARM-FPGA Embedded SoC | | |
| Jingquan Ge, Yuekang Li, Yang Liu, Yaowen Zheng, Yi Liu and Lida Zhao |
| On the Degree of Parallelism in Real-Time Scheduling of DAG Tasks | | |
| Qingqiang He, Nan Guan, Mingsong Lv and Zonghua Gu |
| Timing Predictability for SOME/IP-based Service-Oriented Automotive In-Vehicle Networks | | |
| Enrico Fraccaroli, Prachi Joshi, Shengjie Xu, Khaja Shazzad, Markus Jochim and Samarjit Chakraborty |
| Analysis and Optimization of Worst-Case Time Disparity in Cause-Effect Chains | | |
| Xu Jiang, xiantong Luo, Nan Guan, Zheng Dong, Shaoshan Liu and Wang Yi |
| Data Freshness Optimization on Networked Intermittent Systems | | |
| Hao-Jan Huang, Wen Sheng Lim, Chia-Heng Tu, Chun-Feng Wu and Yuan-Hao Chang |
| A Safety-Guaranteed Framework for Neural-Network-Based Planners in Connected Vehicles under Communication Disturbance | | |
| Kevin Kai-Chun Chang, Xiangguo Liu, Chung-Wei Lin, Chao Huang and Qi Zhu |
| Co-Design of Topology, Scheduling, and Path Planning in Automated Warehouses | | |
| Christopher Leet, Chanwook Oh, Michele Lora, Sven Koenig and Pierluigi Nuzzo |
| Polyglot Modal Models through Lingua Franca | | |
| Alexander Schulz-Rosengarten, Reinhard von Hanxleden, Marten Lohstroh, Soroush Bateni and Edward A. Lee |
| DEL: Dynamic Symbolic Execution-based Lifter for Enhanced Low-Level Intermediate Representation | | |
| Hany Abdelmaksoud, Zain A. H. Hammadeh, Goerschwin Fey and Daniel Luedtke |
| WCET Analysis of Shared Caches in Multi-Core Architectures using Event-Arrival Curves | | |
| Thilo L. Fischer and Heiko Falk |
| Resource Optimization with 5G Configured Grant Scheduling for Real-Time Applications | | |
| Yungang Pan, Rouhollah Mahfouzi, Soheil Samii, Petru Eles and Zebo Peng |
| Motivating Agent-Based Learning for Bounding Time in Mixed-Criticality Systems | | |
| Behnaz Ranjbar, Ali Hosseinghorban and Akash Kumar |
| Applications of emerging technologies and computing paradigms |
| HDGIM: Hyperdimensional Genome Sequence Matching on Unreliable Highly Scaled FeFET | | |
| Hamza Errahmouni Barkam, Sanggeon Yun, Paul R. Genssler, Zhuowen Zou, Che-Kai Liu, Hussam Amrouch and Mohsen Imani |
| Quantum Measurement Discrimination using Cumulative Distribution Functions | | |
| Zachery Utt, Daniel Volya and Prabhat Mishra |
| Extending the Design Space of Dynamic Quantum Circuits for Toffoli based Network | | |
| Abhoy Kole, Arighna Deb, Kamalika Datta and Rolf Drechsler |
| AI-Based Detection of Droplets and Bubbles in Digital Microfluidic Biochips | | |
| Jianan Xu, Wenjie Fan, Georgi Plamenov Tanev, Jan Madsen and Luca Pezzarossa |
| Split Additive Manufacturing for Printed Neuromorphic Circuits | | |
| Haibin Zhao, Michael Hefenbrock, Michael Beigl and Mehdi Tahoori |
| PIMPR: PIM-based Personalized Recommendation with Heterogeneous Memory Hierarchy | | |
| Tao Yang, Hui Ma, Yilong Zhao, Fangxin Liu, Zhezhi He, Xiaoli Sun and Li Jiang |
| FSL-HD: Accelerating Few-Shot Learning on ReRAM using Hyperdimensional Computing | | |
| Weihong Xu, Jaeyoung Kang and Tajana Rosing |
| HD-I-IoT: Hyperdimensional Computing for Resilient Industrial Internet of Things Analytics | | |
| Onat Gungor, Tajana Rosing and Baris Aksanli |
| STAR: An Efficient Softmax Engine for Attention Model with RRAM Crossbar | | |
| Yifeng Zhai, Bing Li and Bonan Yan |
| Value-based Reinforcement Learning using Efficient Hyperdimensional Computing | | |
| Yang Ni, Danny Abraham, Mariam Ali Issa, Yeseong Kim, Pietro Mercati and Mohsen Imani |
| DropDim: Incorporating Efficient Uncertainty Estimation into Hyperdimensional Computing | | |
| Yang Ni, Hanning Chen, Prathyush P. Poduval, Pietro Mercati and Mohsen Imani |
| ASD focus session 2: SelPhys: Self-awareness in Cyber-physical Systems |
| Self-awareness in Cyber-physical Systems | | |
| Lukas Esterle and Axel Jantsch |
| Supply chain attacks |
| Hardware Trojans in eNVM Neuromorphic Devices | | |
| Lingxi Wu, Rahul Sreekumar, Rasool Sharifi, Kevin Skadron, Stan Mircea and Ashish Venkat |
| EvoLUTe: Evaluation of Look-Up-Table-based Fine-Grained IP Redaction | | |
| Rui Guo, Mohammad S. Rahman, Hadi Mardani Kamali, Fahim Rahman, Farimah Farahmandi and Mark Tehranipoor |
| RTLock: IP Protection using Scan-Aware Logic Locking at RTL | | |
| Md Rafid Muttaki, Shuvagata Saha, Hadi Mardani Kamali, Fahim Rahman, Mark Tehranipoor and Farimah Farahmandi |
| Improving Heterogenous hardware utilization |
| Ditty: Directory-based Cache Coherence for Multicore Safety-critical Systems | | |
| Zhuanhao Wu, Marat Bekmyrza, Nachiket Kapre and Hiren Patel |
| Light Flash Write for Efficient Firmware Update on Energy-harvesting IoT Devices | | |
| Songran Liu, Mingsong Lv, Wei Zhang, Xu Jiang, Chuancai Gu, Tao Yang, Wang Yi and Nan Guan |
| HADAS: Hardware-Aware Dynamic Neural Architecture Search for Edge Performance Scaling | | |
| Halima Bouzidi, Mohanad Odema, Hamza Ouarnoughi, Mohammad Al Faruque and Smail Niar |
| Industrial Experiences Brief Papers |
| Multiphysics Design and Simulation Methodology for Dense WDM Silicon Photonics | | |
| Jinsung Youn, Luca Ramini, Zeqin Lu, Ahsan Alam, James Pond, Marco Fiorentino and Raymond Beausoleil |
| Two-Stream Neural Network for Post-Layout Waveform Prediction | | |
| Sanghwi Kim, Hyejin Shin and Hyunkyu Kim |
| Quantization-Aware Neural Architecture Search with Hyperparameter Optimization for Industrial Predictive Maintenance Applications | | |
| Nick van de Waterlaat, Sebastian Vogel, Hiram Rayo Torres Rodriguez, Willem Sanberg and Gerardo Daalderop |
| Focus Session: Smart Additive Manufacturing: Fabrication and Design (Automation) |
| Highly-Bespoke Robust Printed Neuromorphic Circuits | | |
| Haibin Zhao, Brojogopal Sapui, Michael Hefenbrock, Zhidong Yang, Michael Beigl , Mehdi B. Tahoori |
| Hardware accelerators serving efficient machine learning software architectures |
| Pipe-BD: Pipelined Parallel Blockwise Distillation | | |
| Hongsun Jang, Jaewon Jung, Jaeyong Song, Joonsang Yu, Youngsok Kim and Jinho Lee |
| Layer-Puzzle: Allocating and Scheduling Multi-task on Multi-core NPUs by Using Layer Heterogeneity | | |
| Chengsi Gao, Ying Wang, Cheng Liu, Mengdi Wang, Weiwei Chen, yinhe han and Lei Zhang |
| Dynamic Task Remapping for Reliable CNN Training on ReRAM Crossbars | | |
| Chung-Hsuan Tung, Biresh Kumar Joardar, Partha Pratim Pande, Jana Doppa, Hai (Helen) Li and Krishnendu Chakrabarty |
| Mobile Accelerator Exploiting Sparsity of Multi-Heads, Lines and Blocks in Transformers in Computer Vision | | |
| Eunji Kwon, Haena Song, Jihye Park and Seokhyeong Kang |
| RAWAtten: Reconfigurable Accelerator for Window Attention in Hierarchical Vision Transformers | | |
| Wantong Li, Yandong Luo and Shimeng Yu |
| M5: Multi-modal Multi-task Model Mapping on Multi-FPGA with Accelerator Configuration Search | | |
| Akshay Karkal Kamath, Stefan Abi-Karam, Ashwin Bhat and Cong Hao |
| SteppingNet: A Stepping Neural Network with Incremental Accuracy Enhancement | | |
| Wenhao Sun, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Huaxi Gu, Bing Li and Ulf Schlichtmann |
| AIRCHITECT: Automating Hardware Architecture and Mapping Optimization | | |
| Ananda Samajdar, Jan Moritz Joseph and Tushar Krishna |
| Accelerating Inference of 3D-CNN on ARM Many-core CPU via Hierarchical Model Partition | | |
| Jiazhi Jiang, ZiJian Huang, Dan Huang, Jiangsu Du and Yutong Lu |
| CEST: Computation-Efficient N:M Sparse Training for Deep Neural Networks | | |
| Chao Fang, Wei Sun, Aojun Zhou and Zhongfeng Wang |
| BOMP-NAS: Bayesian Optimization Mixed Precision NAS | | |
| David van Son, Floran de Putter, Sebastian Vogel and Henk Corporaal |
| A machine-learning-guided framework for fault-tolerant DNNs | | |
| Marcello Traiola, Angeliki Kritikakou and Olivier Sentieys |
| Secure circuits and architectures |
| Establishing Dynamic Secure Sessions for ECQV Implicit Certificates in Embedded Systems | | |
| Fikret Basic, Christian Steger and Robert Kofler |
| Cache Side-channel Attacks and Defenses of the Sliding Window Algorithm in TEEs | | |
| Zili KOU, Sharad Sinha, Wenjian HE and Wei ZHANG |
| The First Concept and Real-world Deployment of a GPU-based Thermal Covert Channel: Attack and Countermeasures | | |
| Jeferson Gonzalez-Gomez, Kevin Cordero-Zuniga, Lars Bauer and Joerg Henkel |
| SIGFuzz: A Framework for Discovering Microarchitectural Timing Side Channels | | |
| Chathura Rajapaksha, Leila Delshadtehrani, Manuel Egele and Ajay Joshi |
| Run-time integrity monitoring of untrustworthy analog front-ends | | |
| Heba Salem and Nigel P. Topham |
| SPOILER-ALERT: Detecting Spoiler Attacks Using a Cuckoo Filter | | |
| Jinhua Cui, Yiyun Yin, Congcong Chen and Jiliang Zhang |
| HUnTer: Hardware Underneath Trigger for Exploiting SoC-level Vulnerabilities | | |
| Sree Ranjani Rajendran, Shams Tarek, Benjamin Myers Hicks, Hadi Mardani Kamali, Farimah Farahmandi and Mark Tehranipoor |
| Maximizing the Potential of Custom RISC-V Vector Extensions for Speeding up SHA-3 Hash Functions | | |
| Huimin Li, Nele Mentens and Stjepan Picek |
| Privacy-by-Sensing with Time-domain Differentially-Private Compressed Sensing | | |
| Jianbo Liu, Boyang Cheng, Pengyu Zeng, Steven Davis, Muya Chang and Ningyuan Cao |
| Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array | | |
| Jianan Mu, HuaJie Tan, Jiawen Wu, Haotian Lu, Chip-Hong Chang, Shuai Chen, Shengwen Liang, Jing Ye, Huawei Li and Xiaowei Li |
| CoFHEE: A Co-processor for Fully Homomorphic Encryption Execution | | |
| Mohammed Nabeel Thari Moopan, Deepraj Soni, Mohammed Ashraf, Mizan Abraha Gebremichael, Homer Gamil, Eduardo Chielle, Ramesh Karri, Mihai Sanduleanu and Michail Maniatakos |
| A Rapid Reset 8-Transistor Physically Unclonable Function Utilising Power Gating | | |
| Yujin Zheng, Alex Bystrov and Alex Yakovlev |
| Focus session: Cross Layer Design for the Predictive Assessment of Technology-Enabled Architectures |
| Cross Layer Design for the Predictive Assessment of Technology-Enabled Architectures | | |
| Michael Niemier, X. Sharon Hu, Liu Liu, Mohammad Mehdi Sharifi, Ian O'Connor, David Atienza, Giovanni Ansaloni, Can Li, Asif Khan and Daniel C. Ralph |
| Focus session: New perspectives for neuromorphic cameras: algorithms, architectures and circuits for event-based CMOS sensors |
| The CNN vs. SNN Event-camera Dichotomy and Perspectives For Event-Graph Neural Networks | | |
| Thomas DALGATY, Thomas Mesquida, Damien JOUBERT, Amos SIRONI, Pascal Vivet and Christoph POSCH |
| Brain-Inspired Spatiotemporal Processing Algorithms for Efficient Event-Based Perception | | |
| Biswadeep Chakraborty, Uday Kamal, Xueyuan She, Saurabh Dash and Saibal Mukhopadhyay |
| Low-Throughput Event-Based Image Sensors and Processing | | |
| Laurent Fesquet, Rosalie TRAN, Xavier LESAGE, Mohamed Akrarai and Gilles Sicard |
| Efficient processing for NNs |
| Automated Energy-Efficient DNN Compression under Fine-Grain Accuracy Constraints | | |
| Ourania Spantidi and Iraklis Anagnostopoulos |
| A Speed- and Energy-Driven Holistic Training Framework for Sparse CNN Accelerators | | |
| Yuanchen Qu, Yu Ma and Pingqiang Zhou |
| Hardware Efficient Weight-Binarized Spiking Neural Networks | | |
| Chengcheng Tang and Jie Han |
| Hardware accelerators |
| Accelerating Gustavson-based SpMM on Embedded FPGAs with Element-wise Parallelism and Access Pattern-aware Caches | | |
| Shiqing Li and Weichen Liu |
| GraphIte: Accelerating Iterative Graph Algorithms on ReRAM Architectures via Approximate Computing | | |
| Dwaipayan Choudhury, Ananth Kalyanaraman and Partha Pratim Pande |
| PEDAL: A Power Efficient GCN Accelerator with Multiple DAtafLows | | |
| Yuhan Chen, Alireza Khadem, Xin He, Nishil Talati, Tanvir Ahmed Khan and Trevor Mudge |
| Hardware Security |
| SoCFuzzer: SoC Vulnerability Detection using Cost Function enabled Fuzz Testing | | |
| Muhammad Monir Hossain, Arash Vafaei, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi and Mark Tehranipoor |
| Non-Profiled Side-Channel Assisted Fault Attack: A Case Study on DOMREP | | |
| Sayandeep Saha, Prasanna Ravi, Dirmanto Jap and Shivam Bhasin |
| Efficient Software Masking of AES through Instruction Set Extensions | | |
| Songqiao Cui and Josep Balasch |
| Application specific circuits and systems |
| A Decentralized Frontier Queue for Improving Scalability of Breadth-First-Search on GPUs | | |
| Chou-Ying Hsieh, Po-Hsiu Cheng, Chia-Ming Chang and Sy-Yen Kuo |
| Timely Fusion of Surround Radar/Lidar for Object Detection in Autonomous Driving Systems | | |
| Wenjing XIE, Tao Hu, Neiwen Ling, Guoliang Xing, Shaoshan Liu and Nan Guan |
| A Lightweight and Adaptive Cache Allocation Scheme for Content Delivery Networks | | |
| Ke Liu, Hua Wang, Ke Zhou and Cong Li |
| TBERT: Dynamic BERT Inference with Top-k Based Predictors | | |
| Zejian Liu, kun zhao and Jian Cheng |
| Token Adaptive Vision Transformer with Efficient Deployment for Fine-Grained Image Recognition | | |
| Chonghan Lee, Rita Brugarolas Brufau, Ke Ding and Vijaykrishnan Narayanan |
| End-to-End Optimization of High-Density e-Skin Design: From Spiking Taxel Readout to Texture Classification | | |
| Jiaqi Wang, Mark Daniel Alea, Jonah Van Assche and Georges Gielen |
| Towards deep learning-based occupancy detection via WiFi sensing in unconstrained environments | | |
| Cristian Turetta, Geri Skenderi, Luigi Capogrosso, Florenc Demrozi, Philipp H. Kindt, Alejandro Masrur, Franco Fummi, Marco Cristani and Graziano Pravadelli |
| Content- and Lighting-Aware Adaptive Brightness Scaling for Improved Mobile User Experience | | |
| Samuel Isuwa, David Amos, Amit Kumar Singh, Bashir Al-Hashimi and Geoff Merrett |
| Towards Smart Cattle Farms: Automated Inspection of Cattle Health with Real-Life Data | | |
| Yigit Tuncel, Toygun Basaklar, Mackenzie Smithyman, Vinicius Nunes de Gouvea, Joao Dorea, Younghyun Kim and Umit Ogras |
| Time Series-based Driving Event Recognition for Two Wheelers | | |
| Sai Usha Goparaju, Lakshmanan L, Abhinav Navnit, Rahul Biju, Lovish Bajaj, Deepak Gangadharan and Dr. Aftab Hussain |
| Future memories |
| OverlaPIM: Overlap Optimization for Processing In-Memory Neural Network Acceleration | | |
| Minxuan Zhou, Xuan Wang and Tajana Rosing |
| TAM: A Computing in Memory based on Tandem Array within STT-MRAM for Energy-Efficient Analog MAC Operation | | |
| Jinkai Wang, Zhengkun Gu, Hongyu Wang, Zuolei Hao, Bojun Zhang, Weisheng Zhao and Yue Zhang |
| Out-of-channel data placement for balancing wear-out and IO workloads in RAID-enabled SSDs | | |
| Yang Fan, Xiao Chen qi, Li Jun, Sha Zhi bing, Cai Zhi gang and Liao Jian wei |
| AGDM：An Adaptive Granularity Data Migration Strategy for Hybrid Memory Systems | | |
| Zhouxuan Peng, Dan Feng, Jianxi Chen, Jing Hu and Chuang Huang |
| P-PIM: A Parallel Processing-in-DRAM Framework Enabling RowHammer Protection | | |
| Ranyang Zhou, Sepehr Tabrizchi, Mehrdad Morsali, Arman Roohi and Shaahin Angizi |
| PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration | | |
| Wangxin He, Jian Meng, Sujan Kumar Gonugondla, Shimeng Yu, Naresh R. Shanbhag and Jae-sun Seo |
| End-to-End DNN Inference on a Massively Parallel In-Memory Computing Architecture | | |
| Nazareno Bruschi, Giuseppe Tagliavini, Angelo Garofalo, Francesco Conti, Irem Boybat, Luca Benini and Davide Rossi |
| UHS: An Ultra-fast Hybrid Storage Consolidating NVM and SSD in Parallel | | |
| Qingsong Zhu, Qiang Cao and Jie Yao |
| Optimizing Data Migration for Garbage Collection in ZNS SSDs | | |
| Zhenhua Tan, Linbo Long, Renping Liu, Congming Gao, Yi Jiang and Yan Liu |
| ENASA: Towards Edge Neural Architecture Search based on CIM acceleration | | |
| Shixin Zhao, Songyun Qu, Ying Wang and yinhe han |
| Design and Test of Mixed-Signal Circuits and Memories |
| Post-Silicon Optimization of a Highly Programmable 64-MHz PLL Achieving 2.7-5.7µW | | |
| Marco Gonzalez and David Bol |
| Analog Coverage-driven Selection of Simulation Corners for AMS Integrated Circuits | | |
| Sayandeep Sanyal, Aritra Hazra, Pallab Dasgupta, Scott Morrison, Sudhakar S, Lakshmanan Balasubramanian and Moshiur Rahman |
| Fast Performance Evaluation Methodology for High-speed Memory Interfaces | | |
| Taehoon Kim, Yoona Lee and Woo-Seok Choi |
| Equivalence Checking of System-Level and SPICE-Level Models of Static Nonlinear Circuits | | |
| Kemal Çağlar Coşkun, Muhammad Hassan and Rolf Drechsler |
| Electromigration-aware design technology co-optimization for SRAM in advanced technology nodes | | |
| Mahta Mayahinia, Hsiao-Hsuan Liu, Subrat Mishra, Zsolt Tokei, Francky Catthoor and Mehdi Tahoori |
| Smart Hammering: A practical method of pinhole detection in MRAM memories | | |
| Sina Bakhtavari Mamaghani, Christopher Muench, Jongsin Yun, Martin Keim and Mehdi Baradaran Tahoori |
| MA-Opt: Reinforcement Learning-based Analog Circuit Optimization using Multi-Actors | | |
| Youngchang Choi, Minjeong Choi, Kyongsu Lee and Seokhyeong Kang |
| AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells | | |
| Sumanth Kamineni, Arvind Sharma, Ramesh Harjani, Sachin S. Sapatnekar and Benton H. Calhoun |
| Debugging Low Power Analog Neural Networks for Edge Computing | | |
| Sascha Schmalhofer, Marwin Moeller, Nikoletta Katsaouni, Marcel H. Schulz and Lars Hedrich |
| High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology | | |
| Aibin Yan, Zhen Zhou, Liang Ding, Jie Cui, Zhengfeng Huang, Xiaoqing Wen and Patrick Girard |
| Minimum Unit Capacitance Calculation for Binary-Weighted Capacitor Arrays | | |
| Nibedita Karmokar, Ramesh Harjani and Sachin S. Sapatnekar |
| System modelling, simulation, and validation |
| Spatio-Temporal Modeling for Flash Memory Channels Using Conditional Generative Nets | | |
| Simeng Zheng, Chih-Hui Ho, Wenyu Peng and Paul H. Siegel |
| Efficient Approximation of Performance Spaces for Analog Circuits via Multi-Objective Optimization | | |
| Benedikt Ohse, David Schreiber, Juergen Kampe and Christopher Schneider |
| Multidimensional Features Helping Predict Failures in Production SSD-Based Consumer Storage Systems | | |
| Xinyan Zhang, Zhipeng Tan, Dan Feng, Qiang He, Ju Wan, Hao Jiang, Ji Zhang, Lihua Yang and Wenjie Qi |
| par-gem5: Parallelizing gem5's Atomic Mode | | |
| Niko Zurstraßen, Jose Cubero-Cascante, Jan Moritz Joseph, Rainer Leupers, Xie Xinghua and Li Yichao |
| Fast Behavioural RTL Simulation of 10B Transistor SoC Designs with Metro-MPI | | |
| Guillem López-Paradís, Brian Li, Adrià Armejach, Stefan Wallentowitz, Miquel Moreto and Jonathan Balkind |
| Dynamic Refinement of Hardware Assertion Checkers | | |
| Hasini Witharana, Sahan Sanjaya and Prabhat Mishra |
| STSearch: State Tracing-based Search Heuristics for RTL Validation | | |
| Ziyue Zheng and Yangdi Lyu |
| eF2lowSim: System-Level Simulator of eFlash-Based Compute-in-Memory Accelerators for Convolutional Neural Networks | | |
| Jooho Wang, Sunwoo Kim, Junsu Heo and Chester Sungchung Park |
| Structural Generation of Virtual Prototypes for Smart Sensor Development in SystemC-AMS from Simulink Models | | |
| Alexandra Kuester, Rainer Dorsch and Christian Haubelt |
| A Hardware-Software Cooperative Interval-Replaying for FPGA-based Architecture Evaluation | | |
| Hongwei Cui, Shuhao Liang, Yujie Cui, Weiqi Zhang, Honglan Zhan, Chun Yang, Xianhua Liu and Xu Cheng |
| FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing | | |
| Sajjad Parvin, Mehran Goli, Frank Sill Torres and Rolf Drechsler |
| Quo Vadis Signal? Automated Directionality Extraction for Post-Programming Verification of a Transistor-Level Programmable Fabric | | |
| Apurva Jain, Thomas Broadfoot, Yiorgos Makris and Carl Sechen |
| Multi-partner projects |
| The TeamPlay Project: Analysing and Optimising Time, Energy, and Security for Cyber-Physical Systems | | |
| Benjamin Rouxel, Christopher Brown, Emad Ebeid, Kerstin Eder, Heiko Falk, Clemens Grelck, Jesper Holst, Shashank Jadhav, Yoann Marquer, Marcos Martinez De Alejandro, Kris Nikov, Ali Sahafi, Ulrik Schultz, Adam Seewald, Vangelis Vassalos, Simon Wegener and Olivier Zendra |
| Hardware and Software Support for Mixed Precision Computing: a Roadmap for Embedded and HPC Systems | | |
| William Fornaciari, Giovanni Agosta, Davide Zoni, Andrea Galimberti, Gabriele Magnani, Lev Denisov and Daniele Cattaneo |
| Real Time Acoustic Perception for Automotive Applications | | |
| Jun Yin, Stefano Damiano, Marian Verhelst, Toon van Waterschoot and Andre Guntoro |
| HERMES: qualification of High pErformance pRogrammable Microprocessor and dEvelopment of Software ecosystem | | |
| Nadia Ibellaatti, Edouard LEPAPE, Alp Kilic, Kaya AKYEL, Kassem CHOUAYAKH, Fabrizio Ferrandi, Claudio Barone, Serena Curzel, Michele Fiorito, Giovanni Gozzi, Miguel MASMANO, Ana Risquez Navarro, Manuel Munoz, Vicente Nicolau Gallego, Patricia LOPEZ CUEVA, Jean-noel LETRILLARD and Franck WARTEL |
| A Step Toward Safe Unattended Train Operations: A Pioneer Vital Control Module | | |
| Giovanni Mezzina, Arturo Amendola, Mario Barbareschi, Salvatore De Simone, Grazia Mascellaro, Alberto Moriconi, Cataldo Luciano Saragaglia, Diana Serra and Daniela De Venuto |
| The Post-pandemic Effects on IoT for Safety: The SAFE PLACE Project | | |
| Federico Cunico, Luigi Capogrosso, Alberto Castellini, Francesco Setti, Patrik Pluchino, Filippo Zordan, Valeria Santus, Anna Spagnolli, Stefano Cordibella, Giambattista Gennari, Alberto Sozza, Stefano Troiano, Roberto Flor, Andrea Zanella, Alessandro Farinelli, Luciano Gamberini and Marco Cristani |
| Approximate computing |
| Maximizing Computing Accuracy on Resource-Constrained Architectures | | |
| Van-Phu Ha and Olivier Sentieys |
| MECALS: A Maximum Error Checking Technique for Approximate Logic Synthesis | | |
| Chang Meng, Jiajun Sun, Yuqi Mai and Weikang Qian |
| COMPACT: Co-processor for Multi-mode Precision-adjustable Non-linear Activation Functions | | |
| Wenhui Ou, Zhuoyu Wu, Zheng Wang, Chao Chen and Yongkui Yang |
| DeepCAM: A fully CAM-based inference accelerator with variable hash lengths for energy-efficient deep neural networks | | |
| Duy-Thanh Nguyen, Abhiroop Bhattacharjee, Abhishek Moitra and Priyadarshini Panda |
| Design of Large-Scale Stochastic Computing Adders and their Anomalous Behavior | | |
| Timothy Baker and John Hayes |
| Accurate yet Efficient Stochastic Computing Neural Acceleration with High Precision Residual Fusion | | |
| Yixuan Hu, Tengyu Zhang, Renjie Wei, Meng Li, Runsheng Wang, Yuan Wang and Ru Huang |
| PECAN: A Product-Quantized Content Addressable Memory Network | | |
| Jie Ran, Rui Lin, Jason Chun Lok Li, JiaJun Zhou and Ngai Wong |
| XRing: A Crosstalk-Aware Synthesis Method for Wavelength-Routed Optical Ring Routers | | |
| Zhidan Zheng, Mengchu Li, Tsun-Ming Tseng and Ulf Schlichtmann |
| Exploiting assertions mining and fault analysis to guide RTL-level approximation | | |
| Alberto Bosio, Samuele Germiniani, Graziano Pravadelli and Marcello Traiola |
| An Efficient Fault Injection Algorithm for Identifying Unimportant FFs in Approximate Computing Circuits | | |
| Jiaxuan LU, Yutaka MASUDA and Tohru ISHIHARA |
| Hardware-Aware Automated Neural Minimization for Printed Multilayer Perceptrons | | |
| Argyris Kokkinis, Georgios Zervakis, Kostas Siozios, Mehdi Tahoori and Joerg Henkel |
| Emerging design technologies for future computing |
| Scalable Coherent Optical Crossbar Architecture using PCM for AI Acceleration | | |
| Dan Sturm and Sajjad Moazeni |
| Mixed-Signal Memristor-based Iterative Montgomery Modular Multiplication | | |
| Mehdi Kamal and Massoud Pedram |
| ODLPIM: A Write-Optimized and Long-Lifetime ReRAM-Based Accelerator for Online Deep Learning | | |
| Heng Zhou, Bing Wu, Huan Cheng, Wei Zhao, Xueliang Wei, Jinpeng Liu, Dan Feng and Wei Tong |
| SAT-Based Quantum Circuit Adaptation | | |
| Sebastian Brandhofer, Jinwoong Kim, Siyuan Niu and Nicholas T. Bronn |
| Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits | | |
| Tathagata Srimani, Robert M. Radway, Jinwoo Kim, Kartik Prabhu, Dennis Rich, Carlo Gilardi, Priyanka Raina, Max Shulaker, Sung Kyu Lim and Subhasish Mitra |
| Memristor-Spikelearn: A Spiking Neural Network Simulator for Studying Synaptic Plasticity under Realistic Device and Circuit Behaviors | | |
| Yuming Liu, Angel Yanguas-Gil, Sandeep Madireddy and Yanjing Li |
| Exploiting Kernel Compression on BNNs | | |
| Franyell Silfa, Jose Maria Arnau and Antonio González |
| AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads | | |
| Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti and Luca Benini |
| SIMSnn: A Weight-Agnostic ReRAM-based Search-In-Memory Engine for Spiking Neural Network Acceleration | | |
| Fangxin Liu, Fangxin Liu, Fangxin Liu, Xiaokang Yang and Li Jiang |
| BOMIG: A Majority Logic Synthesis Framework for AQFP Logic | | |
| Rongliang Fu, Junying Huang, Mengmeng Wang, Yoshikawa Nobuyuki, Bei Yu, Tsung-Yi Ho and Olivia Chen |
| Optimized software architecture towards an improved utilization of hardware features |
| MARB: Bridge the Semantic Gap between Operating System and Application Memory Access Behavior | | |
| Haifeng Li, Ke Liu, Ting Liang, Zuojun Li, Tianyue Lu, Yisong Chang, Hui Yuan, Yinben Xia, Yungang Bao, Mingyu Chen and Yizhou Shan |
| SAT-MapIt: A SAT-based Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures | | |
| Cristian Tirelli, Lorenzo Ferretti and Laura Pozzi |
| Liveness-Aware Checkpointing of Arrays for Efficient Intermittent Computing | | |
| Youngbin Kim, Yoojin Lim and Chaedeok Lim |
| SERICO: Scheduling Real-Time I/O Requests in Computational Storage Drives | | |
| Yun HUANG, Nan Guan, Shuhan BAI, Tei-Wei Kuo and Jason Xue |
| Region-based Flash Caching with Joint Latency and Lifetime Optimization in Hybrid SMR Storage Systems | | |
| Zhengang Chen, Guohui Wang, Zhiping Shi, Yong Guan and Tianyu Wang |
| GEM-RL: Generalized Energy Management of Wearable Devices using Reinforcement Learning | | |
| Toygun Basaklar, Yigit Tuncel, Suat Gumussoy and Umit Ogras |
| ViX: Analysis-driven Compiler for Efficient Low-Precision Differentiable Inference | | |
| Ashitabh Misra, Jacob Laurel and Sasa Misailovic |
| Chameleon: Dual Memory Replay for Online Continual Learning on Edge Devices | | |
| Shivam Aggarwal, Kuluhan Binici and Tulika Mitra |
| FAGC: Free Space Fragmentation Aware GC Scheme based on Observations of Energy Consumption | | |
| Lihua Yang, Zhipeng Tan, Fang Wang, Yang Xiao, Wei Zhang and Biao He |
| TransLib: A Library to Explore Transprecision Floating-Point Arithmetic on Multi-Core IoT End-Nodes | | |
| Seyed Ahmad Mirsalari, Giuseppe Tagliavini, Davide Rossi and Luca Benini |
| CFU Playground: Want a faster ML processor? Do it yourself! | | |
| Shvetank Prakash, Timothy J. Callahan, Joseph Bushagour, Colby Banbury, Alan V. Green, Pete Warden, Tim Ansell and Vijay Janapa Reddi |
| Power-efficient and Smart Energy Systems |
| SparseMEM: Energy-efficient Design for In-memory Sparse-based Graph Processing | | |
| Mahdi Zahedi, Geert Custers, Taha Shahroodi, Georgi Gaydadjiev, Stephan Wong and Said Hamdioui |
| HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC | | |
| Luca Valente, Yvan Tortorella, Mattia Sinigaglia, Giuseppe Tagliavini, Alessandro Capotondi, Luca Benini and Davide Rossi |
| High-Speed and Energy-Efficient Single-Port Content Addressable Memory to Achieve Dual-Port Operation | | |
| Honglan Zhan, Chenxi Wang, Hongwei Cui, Xianhua Liu, Feng Liu and Xu Cheng |
| Energy-efficient Hardware Acceleration of Shallow Machine Learning Applications | | |
| Ziqing Zeng and Sachin S. Sapatnekar |
| Stateful Energy Management for Multi-Source Energy Harvesting Transient Computing Systems | | |
| Sergey Mileiko, Oktay Cetinkaya, Rishad Shafik and Domenico Balsamo |
| Fully On-board Low-Power Localization with Multizone Time-of-Flight Sensors on Nano-UAVs | | |
| Hanna Mueller, Nicky Zimmerman, Tommaso Polonelli, Jens Behley, Michele Magno, Cyrill Stachniss and Luca Benini |
| Energy-efficient Wearable-to-Mobile offload of ML inference for PPG-based Heart-Rate estimation | | |
| Alessio Burrello, Matteo Risso, Noemi Tomasello, Yukai Chen, Luca Benini, Enrico Macii, Massimo Poncino and Daniele Jahier Pagliari |
| A Coupled Battery State of Charge and VoltageModel for Optimal Control Applications | | |
| Masoomeh Karami, Sajad Shahsavari, Eero Immonen, Hashem Haghbayan and Juha Plosila |
| ADEE-LID: Automated Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers | | |
| Martin Hurta, Vojtech Mrazek, Michaela Drahosova and Lukas Sekanina |
| Physical attacks and countermeasures |
| Table Re-Computation Based Low Entropy Inner Product Masking Scheme | | |
| Jingdian Ming, Yongbin Zhou, Wei Cheng and Huizhong Li |
| SCFI: State Machine Control-Flow Hardening Against Fault Attacks | | |
| Pascal Nasahl, Martin Unterguggenberger, Rishub Nagpal, Robert Schilling, David Schrammel and Stefan Mangard |
| EASIMask - Towards Efficient, Automated, and Secure Implementation of Masking in Hardware | | |
| Fabian Buschkowski, Pascal Sasdrich and Tim Güneysu |
| ObfusLock: An Efficient Obfuscated Locking Framework for Circuit IP Protection | | |
| You Li, Guannan Zhao, Yunqi He and Hai Zhou |
| Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs | | |
| Ognjen Glamocanin, Hajira Bazaz, Mathias Payer and Mirjana Stojilovic |
| APUF production line faults: uniqueness and testing | | |
| Yeqi Wei, Wenjing Rao and Natasha Devroye |
| Fault Model Analysis of DRAM under Electromagnetic Fault Injection Attack | | |
| Qiang Liu, Longtao Guo and Honghui Tang |
| Expanding In-Cone Obfuscated Tree for Anti SAT Attack | | |
| RuiJie Wang, Li-Nung Hsu, Yung-Chih Chen and TingTing Hwang |
| SheLL: Shrinking eFPGA Fabrics for Logic Locking | | |
| Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi and Mark Tehranipoor |
| Highlighting Two EM Fault Models while Analyzing a Digital Sensor Limitations | | |
| Roukoz Nabhan, Jean-Max Dutertre, Jean-Baptiste Rigaud, Jean-Luc Danger and Laurent Sauvage |
| Securing Heterogeneous 2.5D ICs Against IP Theft through Dynamic Interposer Obfuscation | | |
| Jonti Talukdar, Arjun Chaudhuri, Jinwoo Kim, Sung-Kyu Lim and Krishnendu Chakrabarty |
| Warm-Boot Attack on Modern DRAMs | | |
| Yichen Jiang, Shuo Wang, Renato Jansen Figueiredo and Yier Jin |
| Low-Cost First-Order Secure Boolean Masking in Glitchy Hardware | | |
| Dilip Kumar S V, Josep Balasch, Benedikt Gierlichs and Ingrid Verbauwhede |
| TIPLock: Key-Compressed Logic Locking using Through-Input-Programmable Lookup-Tables | | |
| Kaveh Shamsi and Rajesh Datta |
| Efficient utilization of heterogeneous hardware architectures running machine learning-based applications |
| Block Group scheduling: A General Precision-scalable NPU Scheduling Technique with Capacity-aware Memory Allocation | | |
| Seokho Lee, Younghyun Lee, Hyejun Kim, taehoon kim and Yongjun Park |
| FPGA-Based Accelerator for Rank-Enhanced and Highly-Pruned Block-Circulant Neural Networks | | |
| Haena Song, Jongho Yoon, Dohun Kim, Eunji Kwon, Tae-Hyun Oh and Seokhyeong Kang |
| Lossless Sparse Temporal Coding for SNN-based Classification of Time-Continuous Signals | | |
| Johnson Loh and Tobias Gemmeke |
| NAF: Deeper Network/Accelerator Co-Exploration for Customizing CNNs on FPGA | | |
| Wenqi Lou, Jiaming Qian, Lei Gong, Xuan Wang, Chao Wang and Xuehai Zhou |
| ESRU: Extremely Low-Bit and Hardware-Efficient Stochastic Rounding Unit Design for 8-Bit DNN Training | | |
| Sung-En Chang, Geng Yuan, Alec Lu, Mengshu Sun, Yanyu Li, Xiaolong Ma, Zhengang Li, Yanyue Xie, Minghai Qin, Xue Lin, Zhenman Fang and Yanzhi Wang |
| Class-based Quantization for Neural Networks | | |
| Wenhao Sun, Grace Li Zhang, Huaxi Gu, Bing Li and Ulf Schlichtmann |
| RoaD-RuNNer: Collaborative DNN partitioning and offloading on heterogeneous edge systems | | |
| Andreas Kosmas Kakolyris, Manolis Katsaragakis, Dimosthenis Masouros and Dimitrios Soudris |
| Pruning and Early-Exit Co-Optimization for CNN Acceleration on FPGAs | | |
| Guilherme Korol, Michael Guilherme Jordan, Mateus Beck Rutzig, Jeronimo Castrillon and Antonio Carlos Schneider Beck |
| Lattice Quantization | | |
| Cl�ment Metz, Thibault Allenet, Johannes Thiele, Antoine Dupret and Olivier Bichler |
| Mitigating Heterogeneities in Federated Edge Learning with Resource-independence Aggregation | | |
| Zhao Yang and Qingshuang Sun |
| Multispectral Feature Fusion for Deep Object Detection on Embedded NVIDIA Platforms | | |
| Thomas Kotrba, Martin Lechner, Omair Sarwar and Axel Jantsch |
| RankSearch: An Automatic Rank Search towards Optimal Tensor Compression for Video LSTM Networks on Edge | | |
| Changhai Man, Cheng Chang, Chenchen Ding, Ao Shen, Hongwei Ren, Ziyi Guan, Yuan Cheng, Shaobo Luo, Rumin Zhang, Ngai Wong and Hao Yu |
| High level synthesis and verification |
| Towards High-Level Synthesis of Quantum Circuits | | |
| Chao Lu, Christian Pilato and Kanad Basu |
| MIRROR: MaxImizing the Re-usability of RTL thrOugh RTL to C CompileR | | |
| Md Imtiaz Rashid and Benjamin Carrion Schaefer |
| High-Level Synthesis versus Hardware Construction | | |
| Alexander Kamkin, Mikhail Chupilko, Mikhail Lebedev, Sergey Smolov and Georgi Gaydadjiev |
| TPP: Accelerate Application Launch via Two-Phase Prefetching on Smartphone | | |
| Ying Yuan, Zhipeng Tan, Shitong Wei, Lihua Yang, Wenjie Qi, Xuanzhi Wang and Cong Liu |
| Using High-Level Synthesis to model SystemVerilog procedural timing controls | | |
| Luca Ezio Pozzoni, Fabrizio Ferrandi, Loris Mendola, Alfio Antonino Palazzo and Francesco Pappalardo |
| R-LDPC: Refining Behavior Descriptions in HLS to Implement High-throughput LDPC Decoder | | |
| yifan zhang, Qiang Cao, Jie Yao and Hong Jiang |
| An Automated Verification Framework for HalideIR-Based Compiler Transformations | | |
| Yanzhao Wang, Fei Xie, Zhenkun Yang, Jeremy Casas, Pasquale Cocchini and Jin Yang |
| ChiselFV: A Formal Verification Framework for Chisel | | |
| Mufan Xiang, Yongjian Li and Yongxin Zhao |
| EMNAPE: Efficient Multi-Dimensional Neural Architecture Pruning for EdgeAI | | |
| Hao Kong, Xiangzhong Luo, SHUO HUAI, Di Liu, Ravi Subramaniam, Christian Makaya, Qian Lin and Weichen Liu |
| Metric Temporal Logic with Resettable Skewed Clocks | | |
| Alberto Bombardelli and Stefano Tonetta |
| Polynomial Formal Verification of Floating Point Adders | | |
| Jan Kleinekathöfer, Alireza Mahzoon and Rolf Drechsler |
| Late Breaking Results: new ideas for low power and reliable computing |
| An Ultra-Low-Power Serial Implementation for Sigmoid and Tanh Using CORDIC Algorithm | | |
| Yaoxing Chang, Petar Jokic, Stephane Emery and Luca Benini |
| Process Variation Resilient Current-Domain Analog In Memory Computing | | |
| Kailash Prasad, Sai Shubham, Aditya Biswas and Joycee Mekie |
| Analysis of Quantization Across DNN Accelerator Architecture Paradigms | | |
| Tom Glint, Chandan Kumar Jha, Manu Awasthi and Joycee Mekie |
| Divide and Verify: Using a Divide-and-Conquer Strategy for Polynomial Formal Verification of Complex Circuits | | |
| Rolf Drechsler and Alireza Mahzoon |
| Improving Design Understanding of Processors leveraging Datapath Clustering | | |
| Katharina Ruep and Daniel Grosse |
| Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory | | |
| Bruno Ferres, Oussama Oulkaid, Ludovic Henrio, Mehdi Khosravian, Matthieu Moy, Gabriel Radanne and Pascal Raymond |
| Exploration of Decision Sub-Network Architectures for FPGA-based Dynamic DNNs | | |
| Anastasios Dimitriou, Mingyu Hu, Jonathon Hare and Geoff Merrett |
| Focus session: Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level |
| Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level | | |
| Behnaz Ranjbar, Florian Klemme, Paul R. Genssler, Hussam Amrouch, Jinhyo Jung, Shail Dave, HwiSoo So, Kyoungwoo Lee, Aviral Shrivastava, Ji-Yung Lin, Pieter Weckx, Subrat Mishra, Francky Catthoor, Dwaipayan Biswas and Akash Kumar |
