DATE 2007 AUTHOR INDEX
[A]
[B]
[C]
[D]
[E]
[F]
[G]
[H]
[I]
[J]
[K]
[L]
[M]
[N]
[O]
[P]
[Q]
[R]
[S]
[T]
[V]
[W]
[X]
[Y]
[Z]
- Aaraj,
N.
-
Energy and Execution Time Analysis of a Software-based Trusted Platform Module [p. 1128]
- Abadir,
M.S.
-
Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability [p. 1538]
- Abbasfar,
A.-A.
-
A New Technique for Characterization of Digital-to-Analog Converters in High-Speed Systems [p. 433]
- Aboulhamid,
M.
-
Seamless Hardware/Software Performance Co-Monitoring in a Codesign Simulation Environment
with RTOS Support [p. 876]
- Acquaviva,
A.
-
Dynamic Reconfiguration in Sensor Networks with Regenerative Energy Sources [p. 1054]
- Aggarwal,
V.
-
Simulation-based Reusable Posynomial Models for MOS Transistor Parameters [p. 69]
- Ahmed,
W.
-
Design Space Exploration of Partially Re-Configurable Embedded Processors [p. 319]
- Aitken,
R.
-
DFM/DFY: Should You Trust the Surgeon or the Family Doctor? [p. 439]
-
Worst-Case Design and Margin for Embedded SRAM [p. 1289]
- Aktouf,
C.
-
Remote Testing and Diagnosis of System-on-Chips Using Network Management Frameworks [p. 373]
- Alachiotis,
N.
-
A Decoupled Architecture of Processors with Scratch-Pad Memory Hierarchy [p. 612]
- Alam,
M.
-
An Area Optimized Reconfigurable Encryptor for AES-Rijndael [p. 1116]
- Alessio,
E.
-
Modeling and Simulation Alternatives for the Design of Networked Embedded Systems [p. 1030]
- Al-Hashimi,
B.M.
-
Joint Consideration of Fault-Tolerance, Energy-Efficiency and Performance in On-Chip Networks [p. 1647]
- Alho,
T.
-
Compact Hardware Design of Whirlpool Hashing Core [p. 1247]
- Alles,
M.
-
Low Complexity LDPC Code Decoders for Next Generation Standards [p. 331]
- Al-Sammane,
G.
-
A Symbolic Methodology for the Verification of Analog and Mixed Signal Designs [p. 249]
- Altheimer,
M.
-
Design and DFT of a High-Speed Area-Efficient Embedded Asynchronous FIFO [p. 853]
- Aminzadeh,
H.
-
Design of High-Resolution MOSFET-Only Pipelined ADCs with Digital Calibration [p. 427]
- Amirkhany,
A.
-
A New Technique for Characterization of Digital-to-Analog Converters in High-Speed Systems [p. 433]
- Ammari,
A.
-
Experimental Evaluation of Protections against Laser-induced Faults and Consequences
on Fault Modeling [p. 1587]
- Anders,
J.
-
Re-Configuration of Sub-blocks for Effective Application of Time Domain Tests [p. 707]
- Angiolini,
F.
-
Improving the Fault Tolerance of Nanometric PLA Designs [p. 570]
- Anis,
E.
-
Low Cost Debug Architecture Using Lossy Compression for Silicon Debug [p. 225]
- Antonau,
A.
-
Use of Statistical Timing Analysis on Real Designs [p. 1605]
- Arbelo,
C.
-
Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture:
The H.264/AVC Deblocking Filter [p. 177]
- Arning,
R.
-
The Methodological and Technological Dimensions of Technology Transfer for Embedded Systems
in Aeronautics and Space [p. 1108]
- Arslan,
T.
-
Pipelined Implementation of a Real Time Programmable Encoder for Low Density Parity
Check Code on a Reconfigurable Instruction Cell Architecture [p. 349]
-
A New Pipelined Implementation for Minimum Norm Sorting Used in Square Root
Algorithm for MIMO-VBLAST Systems [p. 1569]
- Ascheid,
G.
-
Design Space Exploration of Partially Re-Configurable Embedded Processors [p. 319]
-
SoftSIMD . Exploiting Subword Parallelism Using Source Code Transformations [p. 1349]
- Askar,
S.
-
Data-Flow Transformations Using Taylor Expansion Diagrams [p. 455]
- Atasu,
K.
-
Optimizing Instruction-set Extensible Processors under Data Bandwidth Constraints [p. 588]
- Atienza,
D.
-
Improving the Fault Tolerance of Nanometric PLA Designs [p. 570]
- Attariyan,
M.
-
Low-cost Protection for SER Upsets and Silicon Defects [p. 1146]
- Aulagnier,
D.
-
RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
- Austin,
T.
-
Low-cost Protection for SER Upsets and Silicon Defects [p. 1146]
- Azemard,
N.
-
Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops [p. 1012]
- Azimane,
M.
-
Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO [p. 859]
- Azzoni,
P.
-
Yield-aware Placement Optimization [p. 1232]
- Babighian,
P.
-
PowerQuest: Trace Driven Data Mining for Power Optimization [p. 1078]
- Baghdadi,
A.
-
Butterfly and Benes-Based On-Chip Communication Networks for Multiprocessor Turbo Decoding [p. 654]
- Baguena,
L.
-
Development of on Board, Highly Flexible, Galileo Signal Generator ASIC [p. 679]
- Bahar,
R.I.
-
Techniques for Designing Noise-Tolerant Multi-Level Combinational Circuits [p. 576]
-
Accurate Timing Analysis Using SAT and Pattern-Dependent Delay Models [p. 1018]
- Balakrishnan,
K.J.
-
Test Cost Reduction for SoC Using a Combined Approach to Test Data Compression and
Test Scheduling [p. 39]
- Balasa,
F.
-
Mapping Multi-Dimensional Signals into Hierarchical Memory Organizations [p. 385]
- Balfour,
J.D.
-
Register Pointer Architecture for Efficient Embedded Processors [p. 600]
- Banda,
S.
-
Behavioral Modeling of Delay-Locked Loops and Its Application to Jitter Optimization in
Ultra Wide-Band Impulse Radio Systems [p. 1430]
- Bañeres,
D.
-
Layout-Aware Gate Duplication and Buffer Insertion [p. 1367]
- Banerjee,
N.
-
Process Variation Tolerant Low Power DCT Architecture [p. 630]
- Bantegnie,
E.
-
Towards Total Open Source in Aeronautics and Space? [p. 1556]
- Barajas,
E.
-
Behavioral Modeling of Delay-Locked Loops and Its Application to Jitter Optimization in
Ultra Wide-Band Impulse Radio Systems [p. 1430]
- Barba,
J.
-
Lightweight Middleware for Seamless HW-SW Interoperability, with Application to
Wireless Sensor Networks [p. 1042]
- Barke,
E.
-
CMCal: An Accurate Analytical Approach for the Analysis of Process Variations with
Non-Gaussian Parameters and Nonlinear Functions [p. 243]
- Barragan Asian,
M.J.
-
BIST Method for Die-Level Process Parameter Variation Monitoring in Analog/Mixed-Signal
Integrated Circuits [p. 1303]
- Barros,
E.
-
A One-Shot Configurable-Cache Tuner for Improved Energy and Performance [p. 755]
- Baschirotto,
A.
-
Experimental Validation of a Tuning Algorithm for High-Speed Filters [p. 421]
- Basten,
T.
-
A Calculator for Pareto Points [p. 285]
-
Congestion-Controlled Best-Effort Communication for Networks-on-Chip [p. 948]
- Bastian,
M.
-
Slow Write Driver Faults in 65nm SRAM Technology: Analysis and March Test Solution [p. 528]
- Batra,
P.
-
Novel Test Infrastructure and Methodology Used for Accelerated Bring-Up and In-System
Characterization of the Multi-Gigahertz Interfaces on the Cell Processor [p. 725]
- Bauer,
A.
-
Tool-Support for the Analysis of Hybrid Systems and Models [p. 924]
- Baumgartner,
J.
-
Formal Verification of a Pervasive Interconnect Bus System in a High-Performance Microprocessor [p. 219]
- Bazargan,
K.
-
Microarchitecture Floorplanning for Sub-threshold Leakage Reduction [p. 1238]
- Bellocq,
P.
-
Development of on Board, Highly Flexible, Galileo Signal Generator ASIC [p. 679]
- Benini,
L.
-
Improving the Fault Tolerance of Nanometric PLA Designs [p. 570]
-
Capturing the Interaction of the Communication, Memory and I/O Subsystems in Memory-Centric
Industrial MPSoC Platforms [p. 660]
-
Adaptive Power Management in Energy Harvesting Systems [p. 773]
-
Dynamic Reconfiguration in Sensor Networks with Regenerative Energy Sources [p. 1054]
-
Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing [p. 1544]
- Bepoix,
A.
-
Development of on Board, Highly Flexible, Galileo Signal Generator ASIC [p. 679]
- Berekovic,
M.
-
Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture:
The H.264/AVC Deblocking Filter [p. 177]
- Bertacco,
V.
-
Engineering Trust with Semantic Guardians [p. 743]
-
Low-cost Protection for SER Upsets and Silicon Defects [p. 1146]
- Bertoletti,
M.
-
Yield-aware Placement Optimization [p. 1232]
- Bertozzi,
D.
-
Capturing the Interaction of the Communication, Memory and I/O Subsystems in Memory-Centric
Industrial MPSoC Platforms [p. 660]
- Bhunia,
S.
-
Low-Overhead Circuit Synthesis for Temperature Adaptation Using Dynamic Voltage Scheduling [p. 1532]
- Bjerregaard,
T.
-
A Scalable, Timing-Safe, Network-on-Chip Architecture with an Integrated Clock Distribution Method [p. 648]
- Bjesse,
B.
-
A Compositional Approach to the Combination of Combinational and Sequential Equivalence
Checking of Circuits without Known Reset States [p. 1170]
- Black-Schaffer,
D.
-
Register Pointer Architecture for Efficient Embedded Processors [p. 600]
- Bloem,
R.
-
Automatic Hardware Synthesis from Specifications: A Case Study [p. 1188]
- Bois,
G.
-
Seamless Hardware/Software Performance Co-Monitoring in a Codesign Simulation Environment
with RTOS Support [p. 876]
- Bolotin,
E.
-
Routing Table Minimization for Irregular Mesh NoCs [p. 942]
- Bombieri,
N.
-
Incremental ABV for Functional Validation of TL-to-RTL Design Refinement [p. 882]
- Bondarev,
E.
-
CARAT: A Toolkit for Design and Performance Analysis of Component-Based Embedded Systems [p. 1024]
- Bonny,
T.
-
Efficient Code Density through Look-up Table Compression [p. 809]
- Bonzini,
P.
-
Polynomial-Time Subgraph Enumeration for Automated Instruction Set Extension [p. 1331]
- Borkar,
S.
-
Microprocessors in the Era of Terascale Integration [p. 237]
- Borremans,
J.
-
Nonlinearity Analysis of Analog/RF Circuits Using Combined Multisine and Volterra Analysis [p. 261]
- Boschi,
G.
-
Using an Innovative SOC-level FMEA Methodology to Design in Compliance with IEC61508 [p. 492]
- Bota,
S.A.
-
Dynamic Critical Resistance: A Timing-Based Critical Resistance Model for Statistical
Delay Testing of Nanometer ICs [p. 1271]
- Botti,
J.
-
Flying Embedded: The Industrial Scene and Challenges for Embedded Systems in Aeronautics
and Space [p. 1246]
- Bouchebaba,
Y.
-
(408) System Level Assessment of an Optical NoC in an MPSoC Platform [p. 1084]
- Boutillon,
E.
-
Data-Flow Transformations Using Taylor Expansion Diagrams [p. 455]
- Brack,
T.
-
Low Complexity LDPC Code Decoders for Next Generation Standards [p. 331]
- Brandenburg,
M.
-
From Algorithm to First 3.5G Call in Record Time . A Novel System Design Approach Based
on Virtual Prototyping and Its Consequences for Interdisciplinary System Design Teams [p. 828]
- Breuer,
M.A.
-
Reduction of Detected Acceptable Faults for Yield Improvement via Error-Tolerance [p. 1599]
- Brière,
M.
-
(408) System Level Assessment of an Optical NoC in an MPSoC Platform [p. 1084]
- Bringmann,
O.
-
Timing Simulation of Interconnected AUTOSAR Software-Components [p. 474]
- Bronckers,
S.
-
Simulation Methodology and Experimental Verification for the Analysis of Substrate Noise on LC-VCO's [p. 1520]
- Brooks,
D.M.
-
Understanding Voltage Variations in Chip Multiprocessors Using a Distributed Power-Delivery Network [p. 624]
- Brooks,
R.
-
Performance Aware Secure Code Partitioning [p. 1122]
- Brunelli,
D.
-
Adaptive Power Management in Energy Harvesting Systems [p. 773]
- Bücker,
M.
-
Low Power Design on Algorithmic and Architectural Level: A Case Study of an HSDPA Baseband
Digital Signal Processing System [p. 1406]
- Butt,
S.A.
-
System Level Clock Tree Synthesis for Power Optimization [p. 1677]
- Cabodi,
G.
-
Boosting the Role of Inductive Invariants in Model Checking [p. 1319]
- Cai,
W.
-
A Sparse Grid Based Spectral Stochastic Collocation Method for Variations-Aware Capacitance
Extraction of Interconnects under Nanometer Process Technology [p. 1514]
- Cai,
Y.
-
Statistical Model Order Reduction for Interconnect Circuits Considering Spatial Correlations [p. 1508]
- Cairò,
I.
-
Behavioral Modeling of Delay-Locked Loops and Its Application to Jitter Optimization in
Ultra Wide-Band Impulse Radio Systems [p. 1430]
- Cakici,
T.
-
Processor Tolerant Beta-Ratio Modulation for Ultra-Dynamic Voltage Scaling [p. 1550]
- Calder,
B.
-
Transient Fault Prediction Based on Anomalies in Processor Events [p. 1140]
- Calimera,
A.
-
Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing [p. 1544]
- Campi,
F.
-
A Dynamically Adaptive DSP for Heterogeneous Reconfigurable Platforms[p. 9]
-
Implementation of AES/Rijndael on a Dynamically Reconfigurable Architecture [p. 355]
- Cao,
Y
-
Fast Statistical Circuit Analysis with Finite-Point Based Transistor Model [p. 1391]
- Carbonero,
J.L.
-
Evaluation of Test Measures for LNA Production Testing Using a Multinormal Statistical Model [p. 731]
- Carro,
L.
-
A Low-SER Efficient Core Processor Architecture for Future Technologies [p. 1448]
- Casper,
J.
-
ATLAS: A Chip-Multiprocessor with Transactional Memory Support [p. 3]
- Caspi,
P.
-
Development and Industrialization [p. 1403]
- Casu,
M.R.
-
An Effective AMS Top-Down Methodology Applied to the Design of a Mixed-Signal
UWB System-on-Chip [p. 1424]
- Catthoor,
F.
-
Fast Memory Footprint Estimation Based on Maximal Dependency Vector Calculation [p. 379]
-
Middleware Design Optimization of Wireless Protocols Based on the Exploitation of Dynamic
Input Patterns [p. 1036]
-
Very Wide Register: An Asymmetric Register File Organization for Low Power Embedded Processors [p. 1066]
- Caubit,
G.
-
Portable Multimedia SoC Design: A Global Challenge [p. 831]
- Chakrabarty,
K.
-
SoC Testing Using LFSR Reseeding, and Scan-Slice-Based TAM Optimization and Test Scheduling [p. 201]
-
A Cross-Referencing-Based Droplet Manipulation Method for High-Throughput and
Pin-Constrained Digital Microfluidic Arrays [p. 552]
-
Heterogeneous Systems on Chip and Systems in Package [p. 737]
- Chakraborty,
S.
-
Accounting for Cache-Related Preemption Delay in Dynamic Priority Schedulability Analysis [p. 1623]
- Chakradhar,
S.T.
-
Unknown Blocking Scheme for Low Control Data Volume and High Observability [p. 33]
- Chang,
Y.-J.
-
Improve CAM Power Efficiency Using Decoupled Match Line Scheme [p. 165]
- Chatha,
K.S.
-
(287) An ILP Formulation for System-Level Application Mapping on Network Processor Architectures [p. 99]
- Chattopadhyay,
A.
-
Design Space Exploration of Partially Re-Configurable Embedded Processors [p. 319]
- Chaudron,
M.
-
CARAT: A Toolkit for Design and Performance Analysis of Component-Based Embedded Systems [p. 1024]
- Chen,
J.-J.
-
Energy-Efficient Real-Time Task Scheduling with Task Rejection [p. 1629]
- Chen,
K.
-
Compositional Specification of Behavioral Semantics [p. 906]
- Chen,
M.
-
Fast Statistical Circuit Analysis with Finite-Point Based Transistor Model [p. 1391]
- Cheng,
K.-T.
-
Testable Design for Advanced Serial-Link Transceivers [p. 695]
-
A Two-Tone Test Method for Continuous-Time Adaptive Equalizers [p. 1283]
-
A Framework for System Reliability Analysis Considering Both System Error Tolerance and
Component Test Quality [p. 1581]
- Cheng,
X.
-
Clock Domain Crossing Fault Model and Coverage Metric for Validation of SoC Design [p. 1385]
- Choi,
G.
-
Minimum-Energy LDPC Decoder for Real-Time Mobile Application [p. 343]
- Chong,
Y.J.
-
Automatic Application Specific Floating-point Unit Generation [p. 461]
- Choudhary,
A.
-
An FPGA Implementation of Decision Tree Classification [p. 189]
- Choudhury,
M.
-
Single-ended Coding Techniques for Off-chip Interconnects to Commodity Memory [p. 1072]
-
Accurate and Scalable Reliability Analysis of Logic Circuits [p. 1454]
- Chowdhury,
M.H.
-
Analysis of Power Consumption and BER of Flip-flop Based Interconnect Pipelining [p. 1218]
- Ciccarelli,
L.
-
A Dynamically Adaptive DSP for Heterogeneous Reconfigurable Platforms[p. 9]
- Cidon,
I.
-
Routing Table Minimization for Irregular Mesh NoCs [p. 942]
- Ciesielski,
M.
-
Data-Flow Transformations Using Taylor Expansion Diagrams [p. 455]
- Ciordas,
C.
-
Congestion-Controlled Best-Effort Communication for Networks-on-Chip [p. 948]
- Claus,
C.
-
Using Partial-Run-Time Reconfigurable Hardware to Accelerate Video Processing in
Driver Assistance Systems [p. 498]
- Coeffe,
V.
-
Portable Multimedia SoC Design: A Global Challenge [p. 831]
- Coenen,
M.
-
Undisrupted Quality-of-Service during Reconfiguration of Multiple Applications in Networks on Chip [p. 954]
- Colucci,
F.
-
Using an Innovative SOC-level FMEA Methodology to Design in Compliance with IEC61508 [p. 492]
- Combot,
E.
-
New Safety Critical Radio Altimeter for Airbus and Related Design Flow [p. 684]
- Constantinides,
K.
-
Low-cost Protection for SER Upsets and Silicon Defects [p. 1146]
- Corporaal,
H.
-
(394) An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems on Chip [p. 117]
-
Very Wide Register: An Asymmetric Register File Organization for Low Power Embedded Processors [p. 1066]
- Corsi,
F.
-
Experimental Validation of a Tuning Algorithm for High-Speed Filters [p. 421]
- Cortadella,
J.
-
Layout-Aware Gate Duplication and Buffer Insertion [p. 1367]
- Cosculluela,
R.
-
Behavioral Modeling of Delay-Locked Loops and Its Application to Jitter Optimization in
Ultra Wide-Band Impulse Radio Systems [p. 1430]
- Coskun,
A.
-
Transient Fault Prediction Based on Anomalies in Processor Events [p. 1140]
- Courtois,
B.
-
Heterogeneous Systems on Chip and Systems in Package [p. 737]
- Coutinho,
D.
-
Behavioral Modeling of Delay-Locked Loops and Its Application to Jitter Optimization in
Ultra Wide-Band Impulse Radio Systems [p. 1430]
- Crepaldi,
M.
-
An Effective AMS Top-Down Methodology Applied to the Design of a Mixed-Signal
UWB System-on-Chip [p. 1424]
- Cucu,
L.
-
Feasibility Intervals for Multiprocessor Fixed-Priority Scheduling of Arbitrary Deadline
Periodic Systems [p. 1635]
- Cui,
J.
-
An Efficient Algorithm for Online Management of 2D Area of Partially Reconfigurable FPGAs [p. 129]
- D'Ascoli,
F.
-
Low-g Accelerometer Fast Prototyping for Automotive Applications [p. 486]
- Dabrowski
J.
-
Boosting SER Test for RF Transceivers by Simple DSP Technique [p. 719]
- Daembkes,
H.
-
The Methodological and Technological Dimensions of Technology Transfer for Embedded Systems
in Aeronautics and Space [p. 1108]
- Daga,
J.-M.
-
Evaluation of Design for Reliability Techniques in Embedded Flash Memories [p. 1593]
- Dalirsani,
A.
-
Using the Inter- and Intra-Switch Regularity in NoC Switch Testing [p. 361]
- Dally,
W.J.
-
Register Pointer Architecture for Efficient Embedded Processors [p. 600]
- D'Amico,
S.
-
Experimental Validation of a Tuning Algorithm for High-Speed Filters [p. 421]
- Danaie,
M.
-
Design of High-Resolution MOSFET-Only Pipelined ADCs with Digital Calibration [p. 427]
- Daniel,
L.
-
pFFT in FastMaxwell: A Fast Impedance Extraction Solver for 3D Conductor Structures over Substrate [p. 1194]
-
Optimization-based Wideband Basis Functions for Efficient Interconnect Extraction [p. 1200]
- Das,
T.
-
Sensitivity Analysis for Fault-analysis and Tolerance in RF Front-end Circuitry [p. 1277]
- de Benito,
C.
-
Dynamic Critical Resistance: A Timing-Based Critical Resistance Model for Statistical
Delay Testing of Nanometer ICs [p. 1271]
- de Kock
E.
-
A Process Splitting Transformation for Kahn Process Networks [p. 1355]
- De Locht,
L.
-
Nonlinearity Analysis of Analog/RF Circuits Using Combined Multisine and Volterra Analysis [p. 261]
- De Marinis,
M.
-
Low-g Accelerometer Fast Prototyping for Automotive Applications [p. 486]
- De Micheli
G.
-
Improving the Fault Tolerance of Nanometric PLA Designs [p. 570]
- De Nanclas,
M.
-
Seamless Hardware/Software Performance Co-Monitoring in a Codesign Simulation Environment
with RTOS Support [p. 876]
- de With,
P.H.N.
-
CARAT: A Toolkit for Design and Performance Analysis of Component-Based Embedded Systems [p. 1024]
- Dedeken,
F.
-
Enabling Certification for Dynamic Partial Reconfiguration Using a Minimal Flow [p. 983]
- Del Corona,
I.
-
FPGA-based Networking Systems for High Data-rate and Reliable In-vehicle Communications [p. 480]
- Deledda,
A.
-
A Dynamically Adaptive DSP for Heterogeneous Reconfigurable Platforms[p. 9]
-
Implementation of AES/Rijndael on a Dynamically Reconfigurable Architecture [p. 355]
- Delorme,
N.
-
Heterogeneous Systems on Chip and Systems in Package [p. 737]
- Demuytere,
P.
-
Development of an ASIP Enabling Flows in Ethernet Access Using a Retargetable Compilation Flow [p. 1418]
- Deng,
Q.
-
An Efficient Algorithm for Online Management of 2D Area of Partially Reconfigurable FPGAs [p. 129]
- Deprettere,
E.
-
Performance Analysis of Multimedia Applications Using Correlated Streams [p. 912]
- Derbek,
V.
-
Simulation Platform for UHF RFID [p. 918]
- Destro,
P.
-
(231) A Smooth Refinement Flow for Co-Designing HW and SW Threads [p. 105]
- Devanathan,
V.R.
-
On Power-profiling and Pattern Generation for Power-safe Scan Tests [p. 534]
- Di Ciano,
M.
-
RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
- Di Natale,
M.
-
(694) Synthesis of Task and Message Activation Models in Real-Time Distributed Automotive Systems [p. 93]
-
Towards a Methodology for the Quantitative Evaluation of Automotive Architectures [p. 504]
- Dick,
R.P.
-
Accurate Temperature-Dependent Integrated Circuit Leakage Power Estimation Is Easy [p. 1526]
- Dielissen,
J.
-
Non-Fractional Parallelism in LDPC Decoder Implementations [p. 337]
- Dierker,
C.
-
Reconfigurable System-on-Chip Data Processing Units for Space Imaging Instruments [p. 977]
- Dimond,
R.G.
-
Optimizing Instruction-set Extensible Processors under Data Bandwidth Constraints [p. 588]
- Dingankar,
A.
-
Design Fault Directed Test Generation for Microprocessor Validation [p. 761]
- Dirk,
S.
-
(374) Hard- and Software Modularity of the NOVA MPSoC Platform [p. 1102]
- Dittmann,
F.
-
Hard Real-Time Reconfiguration Port Scheduling [p. 123]
- Dobili,
A.
-
Flexibility-oriented Design Methodology for Reconfigurable Delta Sigma Modulators [p. 415]
- Domic,
A.
-
DFM/DFY: Should You Trust the Surgeon or the Family Doctor? [p. 439]
- Dragone,
N.
-
Yield-aware Placement Optimization [p. 1232]
- Drechsler,
R.
-
Estimating Functional Coverage in Bounded Model Checking [p. 1176]
- Dubois,
T.
-
Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO [p. 859]
- Ducharme,
P.
-
Method for Reducing Jitter in Multi-Gigahertz ATE [p. 701]
- Ducrey,
S.
-
Portable Multimedia SoC Design: A Global Challenge [p. 831]
- Dündar,
G.
-
A Coefficient Optimization and Architecture Selection Tool for ∑Δ Modulators in MATLAB [p. 87]
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Optimizing Instruction-set Extensible Processors under Data Bandwidth Constraints [p. 588]
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Development of on Board, Highly Flexible, Galileo Signal Generator ASIC [p. 679]
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(161) Functional and Timing Validation of Partially Bypassed Processor Pipelines [p. 1164]
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Assessing Carbon Nanotube Bundle Interconnect for Future FPGA Architectures [p. 307]
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From Algorithm to First 3.5G Call in Record Time . A Novel System Design Approach Based
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Impact of Description Language, Abstraction Layer, and Value Representation on
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Implementation of a Transaction Level Assertion Framework in SystemC [p. 894]
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J.
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From Algorithm to First 3.5G Call in Record Time . A Novel System Design Approach Based
on Virtual Prototyping and Its Consequences for Interdisciplinary System Design Teams [p. 828]
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An Efficient Methodology for Hierarchical Synthesis of Mixed-Signal Systems with Fully Integrated
Building Block Topology Selection [p. 81]
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Resource Prediction for Media Stream Decoding [p. 594]
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Joint Consideration of Fault-Tolerance, Energy-Efficiency and Performance in On-Chip Networks [p. 1647]
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Improving Utilization of Reconfigurable Resources Using Two-Dimensional Compaction [p. 135]
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Improving Utilization of Reconfigurable Resources Using Two-Dimensional Compaction [p. 135]
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Bus Access Optimisation for FlexRay-based Distributed Embedded Systems [p. 51]
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Optimized Integration of Test Compression and Sharing for SoC Testing [p. 207]
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A Shift Register Based Clause Evaluator for Reconfigurable SAT Solver [p. 153]
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New Safety Critical Radio Altimeter for Airbus and Related Design Flow [p. 684]
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Scalable Reconfigurable Channel Decoder Architecture for Future Wireless Handsets [p. 1563]
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E.S.
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An ADC-BiST Scheme Using Sequential Code Analysis [p. 713]
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A.T.
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A New Pipelined Implementation for Minimum Norm Sorting Used in Square Root
Algorithm for MIMO-VBLAST Systems [p. 1569]
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Performance Analysis of Complex Systems by Integration of Dataflow Graphs and
Compositional Performance Analysis [p. 273]
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Impact of Description Language, Abstraction Layer, and Value Representation on
Simulation Performance [p. 767]
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Implementation of a Transaction Level Assertion Framework in SystemC [p. 894]
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Statistical Model Order Reduction for Interconnect Circuits Considering Spatial Correlations [p. 1508]
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A New Hybrid Solution to Boost SAT Solver Performance [p. 1307]
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Overcoming Glitches and Dissipation Timing Skews in Design of DPA-Resistant Cryptographic
Hardware [p. 1265]
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Low Complexity LDPC Code Decoders for Next Generation Standards [p. 331]
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FPGA-based Networking Systems for High Data-rate and Reliable In-vehicle Communications [p. 480]
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Low-g Accelerometer Fast Prototyping for Automotive Applications [p. 486]
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Pulse Propagation for the Detection of Small Delay Defects [p. 1295]
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Microarchitectural Support for Program Code Integrity Monitoring in Application-specific
Instruction Set Processors [p. 815]
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Automatic Model Generation for Black Box Real-Time Systems [p. 930]
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Clock Domain Crossing Fault Model and Coverage Metric for Validation of SoC Design [p. 1385]
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Identification of Process/Design Issues during 0.18 μm Technology Qualification for
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Experimental Evaluation of Protections against Laser-induced Faults and Consequences
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Reconfigurable System-on-Chip Data Processing Units for Space Imaging Instruments [p. 977]
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Seamless Hardware/Software Performance Co-Monitoring in a Codesign Simulation Environment
with RTOS Support [p. 876]
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Industrial Applications [p. 1244]
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Seamless Hardware/Software Performance Co-Monitoring in a Codesign Simulation Environment
with RTOS Support [p. 876]
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Life Begins at 65 - Unless You Are Mixed Signal? [p. 936]
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Hard Real-Time Reconfiguration Port Scheduling [p. 123]
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CMCal: An Accurate Analytical Approach for the Analysis of Process Variations with
Non-Gaussian Parameters and Nonlinear Functions [p. 243]
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An SoC Test Scheduling Algorithm Using Reconfigurable Union Wrappers [p. 231]
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(231) A Smooth Refinement Flow for Co-Designing HW and SW Threads [p. 105]
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Incremental ABV for Functional Validation of TL-to-RTL Design Refinement [p. 882]
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Modeling and Simulation Alternatives for the Design of Networked Embedded Systems [p. 1030]
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A Middleware-centric Design Flow for Networked Embedded Systems [p. 1048]
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Yield-aware Placement Optimization [p. 1232]
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Challenges of Digital Consumer and Mobile SOC's: More Moore Possible? [p. 1]
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Enabling Certification for Dynamic Partial Reconfiguration Using a Minimal Flow [p. 983]
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RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
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(408) System Level Assessment of an Optical NoC in an MPSoC Platform [p. 1084]
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Transaction Level Modeling of SCA Compliant Software Defined Radio Waveforms and
Platforms PIM/PSM [p. 966]
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Interrupt and Low-level Programming Support for Expanding the Application Domain of
Statically-Scheduled Horizontally-Microcoded Architectures in Embedded Systems [p. 1337]
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Enabling Certification for Dynamic Partial Reconfiguration Using a Minimal Flow [p. 983]
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Testing in the Year 2020 [p. 960]
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Automatic Hardware Synthesis from Specifications: A Case Study [p. 1188]
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RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
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RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
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Automatic Test Pattern Generation for Maximal Circuit Noise in Multiple Aggressor Crosstalk Faults [p. 540]
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S.
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System-Level Process Variation Driven Throughput Analysis for Single and Multiple
Voltage-Frequency Island Designs [p. 403]
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A New Technique for Characterization of Digital-to-Analog Converters in High-Speed Systems [p. 433]
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Towards Total Open Source in Aeronautics and Space? [p. 1556]
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Assessing Carbon Nanotube Bundle Interconnect for Future FPGA Architectures [p. 307]
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A Tiny and Efficient Wireless Ad-hoc Protocol for Low-cost Sensor Networks [p. 1557]
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ATLAS: A Chip-Multiprocessor with Transactional Memory Support [p. 3]
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DRIM: A Low Power Dynamically Reconfigurable Instruction Memory Hierarchy for
Embedded Systems [p. 1343]
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A Calculator for Pareto Points [p. 285]
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Introducing New Verification Methods into a Company's Design Flow: An Industrial User's Point of View [p. 689]
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Efficient and Scalable Compiler-Directed Energy Optimization for Realtime Applications [p. 785]
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An Area Optimized Reconfigurable Encryptor for AES-Rijndael [p. 1116]
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Low-Overhead Circuit Synthesis for Temperature Adaptation Using Dynamic Voltage Scheduling [p. 1532]
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A.
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Low-g Accelerometer Fast Prototyping for Automotive Applications [p. 486]
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G.
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An Efficient Methodology for Hierarchical Synthesis of Mixed-Signal Systems with Fully Integrated
Building Block Topology Selection [p. 81]
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A New Asymmetric SRAM Cell to Reduce Soft Errors and Leakage Power in FPGA [p. 1460]
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Routing Table Minimization for Irregular Mesh NoCs [p. 942]
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Slow Write Driver Faults in 65nm SRAM Technology: Analysis and March Test Solution [p. 528]
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(408) System Level Assessment of an Optical NoC in an MPSoC Platform [p. 1084]
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(694) Synthesis of Task and Message Activation Models in Real-Time Distributed Automotive Systems [p. 93]
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Towards a Methodology for the Quantitative Evaluation of Automotive Architectures [p. 504]
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Reliability-Aware System Synthesis [p. 409]
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Executable System-Level Specification Models Containing UML-Based Behavioral Patterns [p. 301]
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T.
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Formal Verification of a Pervasive Interconnect Bus System in a High-Performance Microprocessor [p. 219]
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Evaluation of Design for Reliability Techniques in Embedded Flash Memories [p. 1593]
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Architectural Leakage-Aware Management of Partitioned Scratchpad Memories [p. 1665]
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Data-Flow Transformations Using Taylor Expansion Diagrams [p. 455]
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System Level Power Optimization of Sigma-Delta Modulator [p. 297]
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J. L.
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Behavioral Modeling of Delay-Locked Loops and Its Application to Jitter Optimization in
Ultra Wide-Band Impulse Radio Systems [p. 1430]
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Feasibility Intervals for Multiprocessor Fixed-Priority Scheduling of Arbitrary Deadline
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Congestion-Controlled Best-Effort Communication for Networks-on-Chip [p. 948]
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Undisrupted Quality-of-Service during Reconfiguration of Multiple Applications in Networks on Chip [p. 954]
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A One-Shot Configurable-Cache Tuner for Improved Energy and Performance [p. 755]
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Utilization of SECDED for Soft Error and Variation-Induced Defect Tolerance in Caches [p. 1134]
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Generating and Executing Multi-Exit Custom Instructions for an Adaptive Extensible Processor [p. 325]
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A Decoupled Architecture of Processors with Scratch-Pad Memory Hierarchy [p. 612]
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Use of Statistical Timing Analysis on Real Designs [p. 1605]
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Trade-Off Design of Analog Circuits Using Goal Attainment and "Wave Front" Sequential Quadratic
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Mapping the Physical Layer of Radio Standards to Multiprocessor Architectures [p. 1412]
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M.
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An Effective AMS Top-Down Methodology Applied to the Design of a Mixed-Signal
UWB System-on-Chip [p. 1424]
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Computing Synchronizer Failure Probabilities [p. 1361]
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(142) Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations
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(374) Hard- and Software Modularity of the NOVA MPSoC Platform [p. 1102]
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Accurate Timing Analysis Using SAT and Pattern-Dependent Delay Models [p. 1018]
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Re-Configuration of Sub-blocks for Effective Application of Time Domain Tests [p. 707]
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Estimating Functional Coverage in Bounded Model Checking [p. 1176]
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An FPGA Based All-Digital Transmitter with Radio Frequency Output for Software Defined Radio [p. 21]
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Energy Evaluation of Software Implementations of Block Ciphers under Memory Constraints [p. 1110]
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An Efficient Algorithm for Online Management of 2D Area of Partially Reconfigurable FPGAs [p. 129]
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DFM/DFY: Should You Trust the Surgeon or the Family Doctor? [p. 439]
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Yield-aware Placement Optimization [p. 1232]
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L.
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Efficient Computation of the Worst-Delay Corner [p. 1617]
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Implementation of AES/Rijndael on a Dynamically Reconfigurable Architecture [p. 355]
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Data-Flow Transformations Using Taylor Expansion Diagrams [p. 455]
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(521) Speeding Up SystemC Simulation through Process Splitting [p. 111]
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Understanding Voltage Variations in Chip Multiprocessors Using a Distributed Power-Delivery Network [p. 624]
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CATS: Cycle Accurate Transaction-driven Simulation with Multiple Processor Simulators [p. 749]
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CATS: Cycle Accurate Transaction-driven Simulation with Multiple Processor Simulators [p. 749]
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A Novel Technique to Use Scratch-pad Memory for Stack Management [p. 1478]
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New Safety Critical Radio Altimeter for Airbus and Related Design Flow [p. 684]
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Cost-Aware Capacity Optimization in Dynamic Multi-Hop WSNs [p. 666]
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Compact Hardware Design of Whirlpool Hashing Core [p. 1247]
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Compact Hardware Design of Whirlpool Hashing Core [p. 1247]
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Resource Prediction for Media Stream Decoding [p. 594]
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Heterogeneous Systems on Chip and Systems in Package [p. 737]
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An Efficient Hardware Architecture for H.264 Intra Prediction Algorithm [p. 183]
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Cost-Aware Capacity Optimization in Dynamic Multi-Hop WSNs [p. 666]
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Compact Hardware Design of Whirlpool Hashing Core [p. 1247]
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(394) An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems on Chip [p. 117]
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Undisrupted Quality-of-Service during Reconfiguration of Multiple Applications in Networks on Chip [p. 954]
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Automatic Generation of Functional Coverage Models from Behavioral Verilog Descriptions [p. 900]
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Heterogeneous Systems on Chip and Systems in Package [p. 737]
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Circuit-Level Modeling and Detection of Metallic Carbon Nanotube Defects in Carbon Nanotube FETs [p. 841]
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Reliability-Aware System Synthesis [p. 409]
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Improving the Fault Tolerance of Nanometric PLA Designs [p. 570]
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Temperature-aware NBTI Modeling and the Impact of Input Vector Control on Performance Degradation [p. 546]
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Statistical Dual-Vdd Assignment for FPGA Interconnect Power Reduction [p. 636]
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An Efficient Algorithm for Online Management of 2D Area of Partially Reconfigurable FPGAs [p. 129]
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From Algorithm to First 3.5G Call in Record Time . A Novel System Design Approach Based
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Development of on Board, Highly Flexible, Galileo Signal Generator ASIC [p. 679]
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Non-Fractional Parallelism in LDPC Decoder Implementations [p. 337]
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Instruction Trace Compression for Rapid Instruction Cache Simulation [p. 803]
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Efficient Code Density through Look-up Table Compression [p. 809]
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Timing Simulation of Interconnected AUTOSAR Software-Components [p. 474]
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Area Optimization of Multi-Cycle Operators in High-Level Synthesis [p. 449]
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S.
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Low Power Design on Algorithmic and Architectural Level: A Case Study of an HSDPA Baseband
Digital Signal Processing System [p. 1406]
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M.
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Energy Evaluation of Software Implementations of Block Ciphers under Memory Constraints [p. 1110]
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An FPGA Implementation of Decision Tree Classification [p. 189]
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A Two-Tone Test Method for Continuous-Time Adaptive Equalizers [p. 1283]
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X.
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Statistical Model Order Reduction for Interconnect Circuits Considering Spatial Correlations [p. 1508]
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M. A.
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A New Technique for Characterization of Digital-to-Analog Converters in High-Speed Systems [p. 433]
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M.
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Using the Inter- and Intra-Switch Regularity in NoC Switch Testing [p. 361]
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M.S.
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A New Hybrid Solution to Boost SAT Solver Performance [p. 1307]
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T.-Y.
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Reduction of Detected Acceptable Faults for Yield Improvement via Error-Tolerance [p. 1599]
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Fast Memory Footprint Estimation Based on Maximal Dependency Vector Calculation [p. 379]
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pFFT in FastMaxwell: A Fast Impedance Extraction Solver for 3D Conductor Structures over Substrate [p. 1194]
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Optimization-based Wideband Basis Functions for Efficient Interconnect Extraction [p. 1200]
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QuteSAT: A Robust Circuit-based SAT Solver for Complex Circuit Structure [p. 1313]
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K.
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Performance Analysis of Multimedia Applications Using Correlated Streams [p. 912]
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P.-K.
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Efficient and Scalable Compiler-Directed Energy Optimization for Realtime Applications [p. 785]
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S.
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Modeling and Simulation to the Design of ZΔ Fractional-N Frequency Synthesizer [p. 291]
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Y.
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Dynamic Learning Based Scan Chain Diagnosis [p. 510]
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J.
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(394) An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems on Chip [p. 117]
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M.
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Impact of Description Language, Abstraction Layer, and Value Representation on
Simulation Performance [p. 767]
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M.
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Implementation of a Transaction Level Assertion Framework in SystemC [p. 894]
- Humenay,
E.B.
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Impact of Process Variations on Multicore Performance Symmetry [p. 1653]
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L.D.
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Utilization of SECDED for Soft Error and Variation-Induced Defect Tolerance in Caches [p. 1134]
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Emerging Solutions Technology and Business Views for the Ubiquitous Communication [p. 678]
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Instruction-Set Customization for Real-Time Embedded Systems [p. 1472]
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M.-E.
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Processor Tolerant Beta-Ratio Modulation for Ultra-Dynamic Voltage Scaling [p. 1550]
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Worst-Case Design and Margin for Embedded SRAM [p. 1289]
- Ienee,
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Automatic Synthesis of Compressor Trees: Reevaluating Large Counters [p. 443]
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A.
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Instruction Trace Compression for Rapid Instruction Cache Simulation [p. 803]
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M.
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Behavioral Modeling of Delay-Locked Loops and Its Application to Jitter Optimization in
Ultra Wide-Band Impulse Radio Systems [p. 1430]
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M.
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Task Scheduling under Performance Constraints for Reducing the Energy Consumption of GALS
Multi-Processor SoC [p. 797]
- Imanishi,
M.
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An SoC Test Scheduling Algorithm Using Reconfigurable Union Wrappers [p. 231]
- Indrusiak,
L.S.
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Executable System-Level Specification Models Containing UML-Based Behavioral Patterns [p. 301]
- Inoue,
K.
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Generating and Executing Multi-Exit Custom Instructions for an Adaptive Extensible Processor [p. 325]
- Iozzi,
F.
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Low-g Accelerometer Fast Prototyping for Automotive Applications [p. 486]
- Irie,
H.
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Utilization of SECDED for Soft Error and Variation-Induced Defect Tolerance in Caches [p. 1134]
- Ishihara,
T.
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Task Scheduling for Reliable Cache Architectures of Multiprocessor Systems [p. 1490]
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A.
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Instruction Trace Compression for Rapid Instruction Cache Simulation [p. 803]
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B.
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Error Rate Reduction in DNA Self-Assembly by Non-Constant Monomer Concentrations and Profiling [p. 847]
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N.
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An Algorithm to Minimize Leakage through Simultaneous Input Vector Control and Circuit Modification [p. 618]
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M.
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Very Wide Register: An Asymmetric Register File Organization for Low Power Embedded Processors [p. 1066]
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A.A.
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HW/SW Implementation from Abstract Architecture Models [p. 1470]
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Butterfly and Benes-Based On-Chip Communication Networks for Multiprocessor Turbo Decoding [p. 654]
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N.K.
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Energy and Execution Time Analysis of a Software-based Trusted Platform Module [p. 1128]
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B.
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Automatic Hardware Synthesis from Specifications: A Case Study [p. 1188]
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F.M.
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Fast and Accurate Routing Demand Estimation for Efficient Routability-driven Placement [p. 1226]
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R.
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Understanding Voltage Variations in Chip Multiprocessors Using a Distributed Power-Delivery Network [p. 624]
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N.P.
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Microprocessors in the Era of Terascale Integration [p. 237]
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H.
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A Novel Criticality Computation Method in Statistical Timing Analysis [p. 1611]
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L.
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Accounting for Cache-Related Preemption Delay in Dynamic Priority Schedulability Analysis [p. 1623]
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H.
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Dynamic Power Management under Uncertain Information [p. 1060]
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Design Challenges at 65nm and Beyond [p. 1466]
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A. P.
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Efficient High-Performance ASIC Implementation of JPEG-LS Encoder [p. 159]
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A Decoupled Architecture of Processors with Scratch-Pad Memory Hierarchy [p. 612]
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On Power-profiling and Pattern Generation for Power-safe Scan Tests [p. 534]
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PowerQuest: Trace Driven Data Mining for Power Optimization [p. 1078]
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A Tiny and Efficient Wireless Ad-hoc Protocol for Low-cost Sensor Networks [p. 1557]
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D.
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Design Space Exploration of Partially Re-Configurable Embedded Processors [p. 319]
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S.
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Towards a Methodology for the Quantitative Evaluation of Automotive Architectures [p. 504]
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Automatic Model Generation for Black Box Real-Time Systems [p. 930]
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M.
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Performance Aware Secure Code Partitioning [p. 1122]
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Memory Bank Aware Dynamic Loop Scheduling [p. 1671]
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A.
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Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture:
The H.264/AVC Deblocking Filter [p. 177]
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J.-C.
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Distributed Power-Management Techniques for Wireless Network Video Systems [p. 564]
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R.
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Testing in the Year 2020 [p. 960]
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G.
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Process Variation Tolerant Low Power DCT Architecture [p. 630]
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R.
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Logic Level Fault Tolerance Approaches Targeting Nanoelectronics PLAs [p. 865]
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Design Space Exploration of Partially Re-Configurable Embedded Processors [p. 319]
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D.C.
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Method for Reducing Jitter in Multi-Gigahertz ATE [p. 701]
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K.
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A Decomposition-based Constraint Optimization Approach for Statically Scheduling Task
Graphs with Communication Delays to Multiprocessors [p. 57]
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Z.
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Pipelined Implementation of a Real Time Programmable Encoder for Low Density Parity
Check Code on a Reconfigurable Instruction Cell Architecture [p. 349]
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A New Pipelined Implementation for Minimum Norm Sorting Used in Square Root
Algorithm for MIMO-VBLAST Systems [p. 1569]
- Khatri,
S.P.
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An Algorithm to Minimize Leakage through Simultaneous Input Vector Control and Circuit Modification [p. 618]
- Khazaka,
R.
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Efficient Nonlinear Distortion Analysis of RF Circuits [p. 255]
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Reversible Circuit Technology Mapping from Non-reversible Specifications [p. 558]
- Kienhuis,
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A Process Splitting Transformation for Kahn Process Networks [p. 1355]
- Kienle,
F.
-
Low Complexity LDPC Code Decoders for Next Generation Standards [p. 331]
- Kim,
D.
-
CATS: Cycle Accurate Transaction-driven Simulation with Multiple Processor Simulators [p. 749]
- Kim,
Y.-B.
-
Error Rate Reduction in DNA Self-Assembly by Non-Constant Monomer Concentrations and Profiling [p. 847]
- Kimmich,
G.
-
Portable Multimedia SoC Design: A Global Challenge [p. 831]
- King,
K.-J.
-
Energy-Efficient Real-Time Task Scheduling with Task Rejection [p. 1629]
- Kinzelbach,
H.
-
CMCal: An Accurate Analytical Approach for the Analysis of Process Variations with
Non-Gaussian Parameters and Nonlinear Functions [p. 243]
- Kirolos,
S.
-
Thermally Robust Clocking Schemes for 3D Integrated Circuits [p. 1206]
- Kishinevsky,
M.
-
Layout-Aware Gate Duplication and Buffer Insertion [p. 1367]
- Kivilcim Coskun,
A.
-
Temperature Aware Task Scheduling in MPSoCs [p. 1659]
- Kjeldsberg,
P.G.
-
Fast Memory Footprint Estimation Based on Maximal Dependency Vector Calculation [p. 379]
- Knijnenburg,
P.M.W.
-
Feasibility of Combined Area and Performance Optimization for Superscalar Processors Using
Random Search [p. 606]
- Kodakara,
S.V.
-
Design Fault Directed Test Generation for Microprocessor Validation [p. 761]
- Kohvakka,
M.
-
Cost-Aware Capacity Optimization in Dynamic Multi-Hop WSNs [p. 666]
- Kokkeler,
A. B. J.
-
Cyclostationary Feature Detection on a Tiled-SoC [p. 171]
- Kolodny,
A.
-
Routing Table Minimization for Irregular Mesh NoCs [p. 942]
- Kondo,
M.
-
Task Scheduling under Performance Constraints for Reducing the Energy Consumption of GALS
Multi-Processor SoC [p. 797]
- Kopetz,
H.
-
The ARTEMIS Cross-Domain Architecture for Embedded Systems [p. 1468]
- Koufopavlou,
O.
-
Optimization of the "FOCUS" Inband-FEC Architecture for 10-Gbps SDH/SONET Optical
Communication Channels [p. 1575]
- Kozyrakis,
C.
-
ATLAS: A Chip-Multiprocessor with Transactional Memory Support [p. 3]
-
Register Pointer Architecture for Efficient Embedded Processors [p. 600]
- Kraemer,
S.
-
SoftSIMD . Exploiting Subword Parallelism Using Source Code Transformations [p. 1349]
- Kraus,
W.
-
Statistical Simulation of High-Frequency Bipolar Circuits [p. 1397]
- Krause,
M.
-
Timing Simulation of Interconnected AUTOSAR Software-Components [p. 474]
- Krishnaiah,
G.
-
Scalable Reconfigurable Channel Decoder Architecture for Future Wireless Handsets [p. 1563]
- Krishnan,
S.
-
Re-Configuration of Sub-blocks for Effective Application of Time Domain Tests [p. 707]
- Kroening,
D.
-
Image Computation and Predicate Refinement for RTL Verilog Using Word Level Proofs [p. 1325]
- Krol,
T.
-
Cyclostationary Feature Detection on a Tiled-SoC [p. 171]
- Kühne,
U.
-
Estimating Functional Coverage in Bounded Model Checking [p. 1176]
- Kumar,
A.
-
(394) An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems on Chip [p. 117]
- Kundu,
S.
-
Automatic Test Pattern Generation for Maximal Circuit Noise in Multiple Aggressor Crosstalk Faults [p. 540]
- Kunkel,
J.
-
Life Begins at 65 - Unless You Are Mixed Signal? [p. 936]
- Kuo,
T.-W.
-
Energy-Efficient Real-Time Task Scheduling with Task Rejection [p. 1629]
- Kuorilehto,
M.
-
Cost-Aware Capacity Optimization in Dynamic Multi-Hop WSNs [p. 666]
- Kuper,
J.
-
Cyclostationary Feature Detection on a Tiled-SoC [p. 171]
- Kurra,
S.
-
The Impact of Loop Unrolling on Controller Delay in High Level Synthesis [p. 391]
- La Barba,
V.
-
RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
- Ladier,
G.
-
Towards Total Open Source in Aeronautics and Space? [p. 1556]
- Lajolo,
M.
-
Hardware Scheduling Support in SMP Architectures [p. 642]
- Lambrechts,
A.
-
Very Wide Register: An Asymmetric Register File Organization for Low Power Embedded Processors [p. 1066]
- Landrault,
C.
-
Slow Write Driver Faults in 65nm SRAM Technology: Analysis and March Test Solution [p. 528]
- Langendörfer,
P.
-
An Efficient Polynomial Multiplier in GF(2m) and Its Application to ECC Designs [p. 1253]
- Langmann,
U.
-
Low Power Design on Algorithmic and Architectural Level: A Case Study of an HSDPA Baseband
Digital Signal Processing System [p. 1406]
- Laouamri,
O.
-
Remote Testing and Diagnosis of System-on-Chips Using Network Management Frameworks [p. 373]
- Larsson,
A.
-
Optimized Integration of Test Compression and Sharing for SoC Testing [p. 207]
- Larsson,
E.
-
Optimized Integration of Test Compression and Sharing for SoC Testing [p. 207]
-
Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO [p. 859]
- Lasbouygues,
B.
-
Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops [p. 1012]
- Lataire,
J.
-
Optimizing Analog Filter Designs for Minimum Nonlinear Distortions Using Multisine Excitations [p. 267]
- Le,
T.
-
Formal Verification of a Pervasive Interconnect Bus System in a High-Performance Microprocessor [p. 219]
- Lee,
C.-C.
-
QuteSAT: A Robust Circuit-based SAT Solver for Complex Circuit Structure [p. 1313]
- Lee,
K.-J.
-
Reduction of Detected Acceptable Faults for Yield Improvement via Error-Tolerance [p. 1599]
- Legat,
J.-D.
-
Enabling Certification for Dynamic Partial Reconfiguration Using a Minimal Flow [p. 983]
- Legat,
J.-D.
-
RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
- Lehnigk-Emden,
T.
-
Low Complexity LDPC Code Decoders for Next Generation Standards [p. 331]
- Lenge,
E.
-
Accurate Timing Analysis Using SAT and Pattern-Dependent Delay Models [p. 1018]
- Leupers,
R.
-
Design Space Exploration of Partially Re-Configurable Embedded Processors [p. 319]
-
SoftSIMD . Exploiting Subword Parallelism Using Source Code Transformations [p. 1349]
- Leveugle,
R.
-
Experimental Evaluation of Protections against Laser-induced Faults and Consequences
on Fault Modeling [p. 1587]
- Lewis,
D.
-
Identification of Process/Design Issues during 0.18 μm Technology Qualification for
Space Application [p. 989]
- Li,
W.
-
Verification-Guided Soft Error Resilience [p. 1442]
- Liao,
Y.-H.
-
Improve CAM Power Efficiency Using Decoupled Match Line Scheme [p. 165]
- Liberati,
R.
-
RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
- Liberati,
R.
-
RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
- Liégeon,
E.
-
Development of on Board, Highly Flexible, Galileo Signal Generator ASIC [p. 679]
- Lilja,
D.
-
Design Fault Directed Test Generation for Microprocessor Validation [p. 761]
- Lim,
H.-B.
-
DRIM: A Low Power Dynamically Reconfigurable Instruction Memory Hierarchy for
Embedded Systems [p. 1343]
- Lin,
C.
-
Design Closure Driven Delay Relaxation Based on Convex Cost Network Flow [p. 63]
- Lin,
K.J.
-
Overcoming Glitches and Dissipation Timing Skews in Design of DPA-Resistant Cryptographic
Hardware [p. 1265]
- Lin,
M.
-
Testable Design for Advanced Serial-Link Transceivers [p. 695]
- Lin,
R.-B.
-
Double-Via-Driven Standard Cell Library Design [p. 1212]
- Lin,
T.
-
Use of Statistical Timing Analysis on Real Designs [p. 1605]
- Lin,
T.-H.
-
Double-Via-Driven Standard Cell Library Design [p. 1212]
-
QuteSAT: A Robust Circuit-based SAT Solver for Complex Circuit Structure [p. 1313]
- Lin,
T.-Y.
-
Double-Via-Driven Standard Cell Library Design [p. 1212]
- Lin,
Y.
-
Statistical Dual-Vdd Assignment for FPGA Interconnect Power Reduction [p. 636]
- Link,
G.
-
Thermally Robust Clocking Schemes for 3D Integrated Circuits [p. 1206]
- L'Insalata,
N.E.
-
Low Complexity LDPC Code Decoders for Next Generation Standards [p. 331]
- Lisboa,
C.A.
-
A Low-SER Efficient Core Processor Architecture for Future Technologies [p. 1448]
- Lissel,
R.
-
Introducing New Verification Methods into a Company's Design Flow: An Industrial User's Point of View [p. 689]
- Liu,
F.
-
Fast Statistical Circuit Analysis with Finite-Point Based Transistor Model [p. 1391]
- Liu,
Y.
-
Accurate Temperature-Dependent Integrated Circuit Leakage Power Estimation Is Easy [p. 1526]
- Lo,
C.C.
-
Overcoming Glitches and Dissipation Timing Skews in Design of DPA-Resistant Cryptographic
Hardware [p. 1265]
- Lodi,
A.
-
A Dynamically Adaptive DSP for Heterogeneous Reconfigurable Platforms[p. 9]
- Lodi,
A.
-
Implementation of AES/Rijndael on a Dynamically Reconfigurable Architecture [p. 355]
- Loghi,
M.
-
Architectural Leakage-Aware Management of Partitioned Scratchpad Memories [p. 1665]
- Lombardi,
F.
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Circuit-Level Modeling and Detection of Metallic Carbon Nanotube Defects in Carbon Nanotube FETs [p. 841]
-
Error Rate Reduction in DNA Self-Assembly by Non-Constant Monomer Concentrations and Profiling [p. 847]
- Lombardo,
P.
-
Dynamic Reconfiguration in Sensor Networks with Regenerative Energy Sources [p. 1054]
- Lonardi,
S.
-
Two-Level Microprocessor-Accelerator Partitioning [p. 313]
-
Clock-Frequency Assignment for Multiple Clock Domain Systems-on-a-Chip [p. 397]
-
Soft-core Processor Customization Using the Design of Experiments Paradigm [p. 821]
- López,
J.C.
-
Lightweight Middleware for Seamless HW-SW Interoperability, with Application to
Wireless Sensor Networks [p. 1042]
- López,
J. F.
-
Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture:
The H.264/AVC Deblocking Filter [p. 177]
- López,
S.
-
Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture:
The H.264/AVC Deblocking Filter [p. 177]
- Lotfi,
R.
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Design of High-Resolution MOSFET-Only Pipelined ADCs with Digital Calibration [p. 427]
- Lucian,
I.I.
-
Mapping Multi-Dimensional Signals into Hierarchical Memory Organizations [p. 385]
- Luk,
W.
-
Optimizing Instruction-set Extensible Processors under Data Bandwidth Constraints [p. 588]
- Lukasiewycz,
M.
-
Reliability-Aware System Synthesis [p. 409]
- Luo,
H.
-
Temperature-aware NBTI Modeling and the Impact of Input Vector Control on Performance Degradation [p. 546]
- Luo,
R.
-
Temperature-aware NBTI Modeling and the Impact of Input Vector Control on Performance Degradation [p. 546]
- Lysecky,
R.
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Low-Power Warp Processor for Power Efficient High-Performance Embedded Systems [p. 141]
- Ma,
H.
-
Modeling and Simulation to the Design of ZΔ Fractional-N Frequency Synthesizer [p. 291]
- Macii,
A.
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Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing [p. 1544]
- Macii,
E.
-
Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing [p. 1544]
- Macii,
E.
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Architectural Leakage-Aware Management of Partitioned Scratchpad Memories [p. 1665]
- Magarshack,
P.
-
DFM/DFY: Should You Trust the Surgeon or the Family Doctor? [p. 439]
- Maingot,
V.
-
Experimental Evaluation of Protections against Laser-induced Faults and Consequences
on Fault Modeling [p. 1587]
- Mamagkakis,
S.
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Middleware Design Optimization of Wireless Protocols Based on the Exploitation of Dynamic
Input Patterns [p. 1036]
- Manet,
P.
-
Enabling Certification for Dynamic Partial Reconfiguration Using a Minimal Flow [p. 983]
-
RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
- Mangassarian,
H.
-
Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability [p. 1538]
- Marculescu,
D.
-
An 0.9 X 1.2", Low Power, Energy-Harvesting System with Custom Multi-Channel
Communication Interface [p. 15]
-
System-Level Process Variation Driven Throughput Analysis for Single and Multiple
Voltage-Frequency Island Designs [p. 403]
-
Soft Error Rate Analysis for Sequential Circuits [p. 1436]
- Marculescu,
R.
-
Distributed Power-Management Techniques for Wireless Network Video Systems [p. 564]
-
(768) Analytical Router Modeling for Networks-on-Chip Performance Analysis [p. 1096]
- Mariani,
R.
-
Using an Innovative SOC-level FMEA Methodology to Design in Compliance with IEC61508 [p. 492]
- Marinissen,
E.J.
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Design and DFT of a High-Speed Area-Efficient Embedded Asynchronous FIFO [p. 853]
-
Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO [p. 859]
- Marino,
C.
-
Low-g Accelerometer Fast Prototyping for Automotive Applications [p. 486]
- Marzocca,
C.
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Experimental Validation of a Tuning Algorithm for High-Speed Filters [p. 421]
- Massoud,
Y.
-
Assessing Carbon Nanotube Bundle Interconnect for Future FPGA Architectures [p. 307]
-
Thermally Robust Clocking Schemes for 3D Integrated Circuits [p. 1206]
- Matarrese,
G.
-
Experimental Validation of a Tuning Algorithm for High-Speed Filters [p. 421]
- Mateo,
D.
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Behavioral Modeling of Delay-Locked Loops and Its Application to Jitter Optimization in
Ultra Wide-Band Impulse Radio Systems [p. 1430]
- Mathaikutty,
D.A.
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Design Fault Directed Test Generation for Microprocessor Validation [p. 761]
- Maufroid,
D.
-
RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
- Maurine,
P.
-
Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops [p. 1012]
- Mavroidis,
I.
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Efficient Testbench Code Synthesis for a Hardware Emulator System [p. 888]
- Medardoni,
S.
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Capturing the Interaction of the Communication, Memory and I/O Subsystems in Memory-Centric
Industrial MPSoC Platforms [p. 660]
- Medwed,
M.
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Energy Evaluation of Software Implementations of Block Ciphers under Memory Constraints [p. 1110]
- Mehdipour,
F.
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Generating and Executing Multi-Exit Custom Instructions for an Adaptive Extensible Processor [p. 325]
- Mehrara,
M.
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Low-cost Protection for SER Upsets and Silicon Defects [p. 1146]
- Meijer,
S.
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A Process Splitting Transformation for Kahn Process Networks [p. 1355]
- Melani,
M.
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Low-g Accelerometer Fast Prototyping for Automotive Applications [p. 486]
- Memik,
G.
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An FPGA Based All-Digital Transmitter with Radio Frequency Output for Software Defined Radio [p. 21]
-
An FPGA Implementation of Decision Tree Classification [p. 189]
- Memik,
S.O.
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Self-Heating-Aware Optimal Wire Sizing under Elmore Delay Model [p. 1373]
- Mencer,
O.
-
Optimizing Instruction-set Extensible Processors under Data Bandwidth Constraints [p. 588]
- Mendias,
J.M.
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Area Optimization of Multi-Cycle Operators in High-Level Synthesis [p. 449]
- Merkenbraeck,
D.
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Enabling Certification for Dynamic Partial Reconfiguration Using a Minimal Flow [p. 983]
- Metra,
C.
-
Pulse Propagation for the Detection of Small Delay Defects [p. 1295]
- Meyr,
H.
-
Design Space Exploration of Partially Re-Configurable Embedded Processors [p. 319]
-
SoftSIMD . Exploiting Subword Parallelism Using Source Code Transformations [p. 1349]
- Mi,
N.
-
Statistical Model Order Reduction for Interconnect Circuits Considering Spatial Correlations [p. 1508]
- Michail, H.
-
A Decoupled Architecture of Processors with Scratch-Pad Memory Hierarchy [p. 612]
- Michalik,
H.
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Reconfigurable System-on-Chip Data Processing Units for Space Imaging Instruments [p. 977]
- Mieyeville,
F.
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(408) System Level Assessment of an Optical NoC in an MPSoC Platform [p. 1084]
- Mignolet,
J.-Y.
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Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture:
The H.264/AVC Deblocking Filter [p. 177]
- Milidonis,
A.
-
A Decoupled Architecture of Processors with Scratch-Pad Memory Hierarchy [p. 612]
- Minier,
D.
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Method for Reducing Jitter in Multi-Gigahertz ATE [p. 701]
- Mir,
S.
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Evaluation of Test Measures for LNA Production Testing Using a Multinormal Statistical Model [p. 731]
- Miremadi,
S.G.
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Joint Consideration of Fault-Tolerance, Energy-Efficiency and Performance in On-Chip Networks [p. 1647]
- Miro Panades,
I.
-
(142) Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations
of a Network on Chip Architecture [p. 1090]
- Mishra,
P.
-
An Efficient Code Compression Technique Using Application-Aware Bitmask and Dictionary
Selection Methods [p. 582]
- Miskov-Zivanov,
N.
-
Soft Error Rate Analysis for Sequential Circuits [p. 1436]
- Mitra,
S.
-
Verification-Guided Soft Error Resilience [p. 1442]
- Mitra,
T.
-
Instruction-Set Customization for Real-Time Embedded Systems [p. 1472]
- Mogal,
H.
-
Microarchitecture Floorplanning for Sub-threshold Leakage Reduction [p. 1238]
- Mohanram,
K.
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Single-ended Coding Techniques for Off-chip Interconnects to Commodity Memory [p. 1072]
-
Accurate and Scalable Reliability Analysis of Logic Circuits [p. 1454]
- Moitrel,
P.
-
Experimental Evaluation of Protections against Laser-induced Faults and Consequences
on Fault Modeling [p. 1587]
- Molina,
M.C.
-
Area Optimization of Multi-Cycle Operators in High-Level Synthesis [p. 449]
- Mondal,
M.
-
Thermally Robust Clocking Schemes for 3D Integrated Circuits [p. 1206]
- Moon,
I.-H.
-
A Compositional Approach to the Combination of Combinational and Sequential Equivalence
Checking of Circuits without Known Reset States [p. 1170]
- Moselhy,
T.
-
pFFT in FastMaxwell: A Fast Impedance Extraction Solver for 3D Conductor Structures over Substrate [p. 1194]
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Optimization-based Wideband Basis Functions for Efficient Interconnect Extraction [p. 1200]
- Moser,
C.
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Adaptive Power Management in Energy Harvesting Systems [p. 773]
- Moss,
L.
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Seamless Hardware/Software Performance Co-Monitoring in a Codesign Simulation Environment
with RTOS Support [p. 876]
- Mourtel,
C.
-
Experimental Evaluation of Protections against Laser-induced Faults and Consequences
on Fault Modeling [p. 1587]
- Moussa,
H.
-
Butterfly and Benes-Based On-Chip Communication Networks for Multiprocessor Turbo Decoding [p. 654]
- Moya,
F.
-
Lightweight Middleware for Seamless HW-SW Interoperability, with Application to
Wireless Sensor Networks [p. 1042]
- Mucci,
C.
-
A Dynamically Adaptive DSP for Heterogeneous Reconfigurable Platforms[p. 9]
-
Implementation of AES/Rijndael on a Dynamically Reconfigurable Architecture [p. 355]
- Mueller,
D.
-
Trade-Off Design of Analog Circuits Using Goal Attainment and "Wave Front" Sequential Quadratic
Programming [p. 75]
- Mueller,
R.
-
Towards Total Open Source in Aeronautics and Space? [p. 1556]
- Mukhopadhayay,
D.
-
An Area Optimized Reconfigurable Encryptor for AES-Rijndael [p. 1116]
- Mukund,
P.R.
-
Sensitivity Analysis for Fault-analysis and Tolerance in RF Front-end Circuitry [p. 1277]
- Mulertt,
O.
-
RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
- Müller,
F.
-
Using Partial-Run-Time Reconfigurable Hardware to Accelerate Video Processing in
Driver Assistance Systems [p. 498]
- Muller,
O.
-
Butterfly and Benes-Based On-Chip Communication Networks for Multiprocessor Turbo Decoding [p. 654]
- Mundy,
J.
-
Techniques for Designing Noise-Tolerant Multi-Level Combinational Circuits [p. 576]
- Münker,
C.
-
Life Begins at 65 - Unless You Are Mixed Signal? [p. 936]
- Murakami,
K.
-
Generating and Executing Multi-Exit Custom Instructions for an Adaptive Extensible Processor [p. 325]
-
Task Scheduling for Reliable Cache Architectures of Multiprocessor Systems [p. 1490]
- Mutyam,
M.
-
Working with Process Variation Aware Caches [p. 1152]
- Nácul,
A.C.
-
Hardware Scheduling Support in SMP Architectures [p. 642]
- Naguib,
Y. N.
-
(521) Speeding Up SystemC Simulation through Process Splitting [p. 111]
- Nahapetian,
A.
-
Dynamic Reconfiguration in Sensor Networks with Regenerative Energy Sources [p. 1054]
- Naidu,
S.
-
Use of Statistical Timing Analysis on Real Designs [p. 1605]
- Najjar,
W.
-
A One-Shot Configurable-Cache Tuner for Improved Energy and Performance [p. 755]
- Najm,
F.N.
-
Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability [p. 1538]
- Nakamura,
H.
-
Task Scheduling under Performance Constraints for Reducing the Energy Consumption of GALS
Multi-Processor SoC [p. 797]
- Nandra,
N.
-
Life Begins at 65 - Unless You Are Mixed Signal? [p. 936]
- Nanya,
T.
-
Task Scheduling under Performance Constraints for Reducing the Energy Consumption of GALS
Multi-Processor SoC [p. 797]
- Narayanan,
R.
-
An FPGA Implementation of Decision Tree Classification [p. 189]
- Narayanan,
S.H.K.
-
Performance Aware Secure Code Partitioning [p. 1122]
- Narayanan,
V.
-
Working with Process Variation Aware Caches [p. 1152]
- Narayanasamy,
S.
-
Transient Fault Prediction Based on Anomalies in Processor Events [p. 1140]
- Nardi,
A.
-
Use of Statistical Timing Analysis on Real Designs [p. 1605]
- Naumann,
A.
-
Was Darwin Wrong? Has Design Evolution Stopped at the RTL Level...or Will Software and Custom Processors (or System-Level Design) Extend Moore's Law? [p. 2]
- Navabi,
Z.
-
Using the Inter- and Intra-Switch Regularity in NoC Switch Testing [p. 361]
- Neema,
S.
-
Compositional Specification of Behavioral Semantics [p. 906]
- Nepal,
K.
-
Techniques for Designing Noise-Tolerant Multi-Level Combinational Circuits [p. 576]
- Ney,
A.
-
Slow Write Driver Faults in 65nm SRAM Technology: Analysis and March Test Solution [p. 528]
- Ni,
M.
-
Self-Heating-Aware Optimal Wire Sizing under Elmore Delay Model [p. 1373]
- Nicolescu,
G.
-
(408) System Level Assessment of an Optical NoC in an MPSoC Platform [p. 1084]
- Nicolici,
N.
-
Low Cost Debug Architecture Using Lossy Compression for Silicon Debug [p. 225]
- Nicollet,
E.
-
Transaction Level Modeling of SCA Compliant Software Defined Radio Waveforms and
Platforms PIM/PSM [p. 966]
- Nieuwoudt,
A.
-
Assessing Carbon Nanotube Bundle Interconnect for Future FPGA Architectures [p. 307]
- Niu,
L.
-
Peripheral-Conscious Scheduling on Energy Minimization for Weakly Hard Real-time Systems [p. 791]
- Njoroge,
N.
-
ATLAS: A Chip-Multiprocessor with Transactional Memory Support [p. 3]
- Nocco,
S.
-
Boosting the Role of Inductive Invariants in Model Checking [p. 1319]
- Noori,
H.
-
Generating and Executing Multi-Exit Custom Instructions for an Adaptive Extensible Processor [p. 325]
- Nurmi,
J.
-
Using Dynamic Voltage Scaling to Reduce the Configuration Energy of Run Time Reconfigurable
Devices [p. 147]
- Oatley,
J.L.
-
Understanding Voltage Variations in Chip Multiprocessors Using a Distributed Power-Delivery Network [p. 624]
- Öberg,
J.
-
Toward a Scalable Test Methodology for 2D-mesh Network-on-Chips [p. 367]
- O'Connor,
I.
-
Heterogeneous Systems on Chip and Systems in Package [p. 737]
-
Heterogeneous Systems on Chip and Systems in Package [p. 737]
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(408) System Level Assessment of an Optical NoC in an MPSoC Platform [p. 1084]
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(768) Analytical Router Modeling for Networks-on-Chip Performance Analysis [p. 1096]
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CMCal: An Accurate Analytical Approach for the Analysis of Process Variations with
Non-Gaussian Parameters and Nonlinear Functions [p. 243]
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A Tiny and Efficient Wireless Ad-hoc Protocol for Low-cost Sensor Networks [p. 1557]
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Industrial Applications [p. 1244]
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ATLAS: A Chip-Multiprocessor with Transactional Memory Support [p. 3]
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Simulation-based Reusable Posynomial Models for MOS Transistor Parameters [p. 69]
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Reconfigurable System-on-Chip Data Processing Units for Space Imaging Instruments [p. 977]
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(287) An ILP Formulation for System-Level Application Mapping on Network Processor Architectures [p. 99]
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Development of on Board, Highly Flexible, Galileo Signal Generator ASIC [p. 679]
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An ADC-BiST Scheme Using Sequential Code Analysis [p. 713]
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Optimizing Instruction-set Extensible Processors under Data Bandwidth Constraints [p. 588]
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Memory Bank Aware Dynamic Loop Scheduling [p. 1671]
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Portable Multimedia SoC Design: A Global Challenge [p. 831]
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Scratchpad Memories vs Locked Caches in Hard Real-Time Systems: A Quantitative
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Fast Memory Footprint Estimation Based on Maximal Dependency Vector Calculation [p. 379]
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A Framework for System Reliability Analysis Considering Both System Error Tolerance and
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The Impact of Loop Unrolling on Controller Delay in High Level Synthesis [p. 391]
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Efficient High-Performance ASIC Implementation of JPEG-LS Encoder [p. 159]
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A New Asymmetric SRAM Cell to Reduce Soft Errors and Leakage Power in FPGA [p. 1460]
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Efficient High-Performance ASIC Implementation of JPEG-LS Encoder [p. 159]
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Efficient Testbench Code Synthesis for a Hardware Emulator System [p. 888]
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Automatic Application Specific Floating-point Unit Generation [p. 461]
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Instruction Trace Compression for Rapid Instruction Cache Simulation [p. 803]
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The Methodological and Technological Dimensions of Technology Transfer for Embedded Systems
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A Novel Technique to Use Scratch-pad Memory for Stack Management [p. 1478]
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Register Pointer Architecture for Efficient Embedded Processors [p. 600]
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A Novel Technique to Use Scratch-pad Memory for Stack Management [p. 1478]
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Register Pointer Architecture for Efficient Embedded Processors [p. 600]
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Industrial Applications [p. 1244]
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Tackling an Abstraction Gap: Co-Simulating with SystemC DE and Bluespec ESL [p. 279]
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Techniques for Designing Noise-Tolerant Multi-Level Combinational Circuits [p. 576]
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DFM/DFY: Should You Trust the Surgeon or the Family Doctor? [p. 439]
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A Future of Customizable Processors: Are We There Yet? [p. 1224]
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Dynamic Power Management under Uncertain Information [p. 1060]
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Bus Access Optimisation for FlexRay-based Distributed Embedded Systems [p. 51]
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Optimized Integration of Test Compression and Sharing for SoC Testing [p. 207]
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A Middleware-centric Design Flow for Networked Embedded Systems [p. 1048]
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Identification of Process/Design Issues during 0.18 μm Technology Qualification for
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An Efficient Polynomial Multiplier in GF(2m) and Its Application to ECC Designs [p. 1253]
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Toward a Scalable Test Methodology for 2D-mesh Network-on-Chips [p. 367]
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FPGA-based Networking Systems for High Data-rate and Reliable In-vehicle Communications [p. 480]
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A Non-Intrusive Isolation Approach for Soft Cores [p. 27]
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Random Sampling of Moment Graph: A Stochastic Krylov-Reduction Algorithm [p. 1502]
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WAVSTAN: Waveform Based Variational Static Timing Analysis [p. 1000]
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Efficient Computation of the Worst-Delay Corner [p. 1617]
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Development and Industrialization [p. 1403]
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A Middleware-centric Design Flow for Networked Embedded Systems [p. 1048]
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BIST Method for Die-Level Process Parameter Variation Monitoring in Analog/Mixed-Signal
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(694) Synthesis of Task and Message Activation Models in Real-Time Distributed Automotive Systems [p. 93]
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Towards a Methodology for the Quantitative Evaluation of Automotive Architectures [p. 504]
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Optimizing Analog Filter Designs for Minimum Nonlinear Distortions Using Multisine Excitations [p. 267]
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Flexible Hardware Reduction for Elliptic Curve Cryptography in GF(2m) [p. 1259]
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Simulation Platform for UHF RFID [p. 918]
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Tool-Support for the Analysis of Hybrid Systems and Models [p. 924]
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Capturing the Interaction of the Communication, Memory and I/O Subsystems in Memory-Centric
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Automatic Hardware Synthesis from Specifications: A Case Study [p. 1188]
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A Compositional Approach to the Combination of Combinational and Sequential Equivalence
Checking of Circuits without Known Reset States [p. 1170]
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A Dynamically Adaptive DSP for Heterogeneous Reconfigurable Platforms[p. 9]
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Automatic Hardware Synthesis from Specifications: A Case Study [p. 1188]
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On Test Generation by Input Cube Avoidance [p. 522]
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Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing [p. 1544]
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Architectural Leakage-Aware Management of Partitioned Scratchpad Memories [p. 1665]
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Bus Access Optimisation for FlexRay-based Distributed Embedded Systems [p. 51]
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Bus Access Optimisation for FlexRay-based Distributed Embedded Systems [p. 51]
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Towards a Methodology for the Quantitative Evaluation of Automotive Architectures [p. 504]
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A Decoupled Architecture of Processors with Scratch-Pad Memory Hierarchy [p. 612]
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A Future of Customizable Processors: Are We There Yet? [p. 1224]
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Polynomial-Time Subgraph Enumeration for Automated Instruction Set Extension [p. 1331]
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System Level Clock Tree Synthesis for Power Optimization [p. 1677]
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(231) A Smooth Refinement Flow for Co-Designing HW and SW Threads [p. 105]
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Incremental ABV for Functional Validation of TL-to-RTL Design Refinement [p. 882]
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Slow Write Driver Faults in 65nm SRAM Technology: Analysis and March Test Solution [p. 528]
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Simulation Platform for UHF RFID [p. 918]
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Scratchpad Memories vs Locked Caches in Hard Real-Time Systems: A Quantitative
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M.
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Energy Minimization with Soft Real-time and DVS for Uniprocessor and Multiprocessor
Embedded Systems [p. 1641]
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Q.
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Stochastic Modeling and Optimization for Robust Power Management in a Partially
Observable System [p. 779]
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Development of an ASIP Enabling Flows in Ethernet Access Using a Retargetable Compilation Flow [p. 1418]
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Y.
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Using Dynamic Voltage Scaling to Reduce the Configuration Energy of Run Time Reconfigurable
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Modeling and Simulation Alternatives for the Design of Networked Embedded Systems [p. 1030]
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A Middleware-centric Design Flow for Networked Embedded Systems [p. 1048]
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Peripheral-Conscious Scheduling on Energy Minimization for Weakly Hard Real-time Systems [p. 791]
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Boosting the Role of Inductive Invariants in Model Checking [p. 1319]
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Reversible Circuit Technology Mapping from Non-reversible Specifications [p. 558]
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Very Wide Register: An Asymmetric Register File Organization for Low Power Embedded Processors [p. 1066]
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Thermally Robust Clocking Schemes for 3D Integrated Circuits [p. 1206]
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Energy and Execution Time Analysis of a Software-based Trusted Platform Module [p. 1128]
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Automatic Generation of Functional Coverage Models from Behavioral Verilog Descriptions [p. 900]
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Boosting SER Test for RF Transceivers by Simple DSP Technique [p. 719]
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Logic Level Fault Tolerance Approaches Targeting Nanoelectronics PLAs [p. 865]
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Energy and Execution Time Analysis of a Software-based Trusted Platform Module [p. 1128]
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On Power-profiling and Pattern Generation for Power-safe Scan Tests [p. 534]
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K.
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A Decomposition-based Constraint Optimization Approach for Statically Scheduling Task
Graphs with Communication Delays to Multiprocessors [p. 57]
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An Area Optimized Reconfigurable Encryptor for AES-Rijndael [p. 1116]
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Energy Evaluation of Software Implementations of Block Ciphers under Memory Constraints [p. 1110]
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On Test Generation by Input Cube Avoidance [p. 522]
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Hardware Scheduling Support in SMP Architectures [p. 642]
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M.
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Interrupt and Low-level Programming Support for Expanding the Application Domain of
Statically-Scheduled Horizontally-Microcoded Architectures in Embedded Systems [p. 1337]
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A Low-SER Efficient Core Processor Architecture for Future Technologies [p. 1448]
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Mapping the Physical Layer of Radio Standards to Multiprocessor Architectures [p. 1412]
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Thermally Robust Clocking Schemes for 3D Integrated Circuits [p. 1206]
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Development and Industrialization [p. 1403]
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Experimental Evaluation of Protections against Laser-induced Faults and Consequences
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Lightweight Middleware for Seamless HW-SW Interoperability, with Application to
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Single-ended Coding Techniques for Off-chip Interconnects to Commodity Memory [p. 1072]
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Single-ended Coding Techniques for Off-chip Interconnects to Commodity Memory [p. 1072]
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Low-g Accelerometer Fast Prototyping for Automotive Applications [p. 486]
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Nonlinearity Analysis of Analog/RF Circuits Using Combined Multisine and Volterra Analysis [p. 261]
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Simulation Methodology and Experimental Verification for the Analysis of Substrate Noise on LC-VCO's [p. 1520]
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A Dynamically Adaptive DSP for Heterogeneous Reconfigurable Platforms[p. 9]
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Timing Simulation of Interconnected AUTOSAR Software-Components [p. 474]
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System Level Clock Tree Synthesis for Power Optimization [p. 1677]
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Joint Consideration of Fault-Tolerance, Energy-Efficiency and Performance in On-Chip Networks [p. 1647]
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Dynamic Critical Resistance: A Timing-Based Critical Resistance Model for Statistical
Delay Testing of Nanometer ICs [p. 1271]
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Low Complexity LDPC Code Decoders for Next Generation Standards [p. 331]
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Enabling Certification for Dynamic Partial Reconfiguration Using a Minimal Flow [p. 983]
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Low Complexity LDPC Code Decoders for Next Generation Standards [p. 331]
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Analysis of Power Consumption and BER of Flip-flop Based Interconnect Pipelining [p. 1218]
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Process Variation Tolerant Low Power DCT Architecture [p. 630]
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Low-Overhead Circuit Synthesis for Temperature Adaptation Using Dynamic Voltage Scheduling [p. 1532]
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Processor Tolerant Beta-Ratio Modulation for Ultra-Dynamic Voltage Scaling [p. 1550]
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Accounting for Cache-Related Preemption Delay in Dynamic Priority Schedulability Analysis [p. 1623]
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Rapid and Accurate Latch Characterization via Direct Newton Solution of Setup/Hold Times [p. 1006]
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An Area Optimized Reconfigurable Encryptor for AES-Rijndael [p. 1116]
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Improve CAM Power Efficiency Using Decoupled Match Line Scheme [p. 165]
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Testing in the Year 2020 [p. 960]
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Capturing the Interaction of the Communication, Memory and I/O Subsystems in Memory-Centric
Industrial MPSoC Platforms [p. 660]
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Area Optimization of Multi-Cycle Operators in High-Level Synthesis [p. 449]
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Statistical Blockade: A Novel Method for Very Fast Monte Carlo Simulation of Rare Circuit
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A Two-Tone Test Method for Continuous-Time Adaptive Equalizers [p. 1283]
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A Shift Register Based Clause Evaluator for Reconfigurable SAT Solver [p. 153]
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Abstraction and Refinement Techniques in Automated Design Debugging [p. 1182]
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Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability [p. 1538]
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A Coefficient Optimization and Architecture Selection Tool for ∑Δ Modulators in MATLAB [p. 87]
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An Efficient Hardware Architecture for H.264 Intra Prediction Algorithm [p. 183]
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Utilization of SECDED for Soft Error and Variation-Induced Defect Tolerance in Caches [p. 1134]
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A Shift Register Based Clause Evaluator for Reconfigurable SAT Solver [p. 153]
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(252) An Enhanced Technique for the Automatic Generation of Effective Diagnosis-oriented Test
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K.
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Identification of Process/Design Issues during 0.18 μm Technology Qualification for
Space Application [p. 989]
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A.
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(694) Synthesis of Task and Message Activation Models in Real-Time Distributed Automotive Systems [p. 93]
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W.
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An Efficient Methodology for Hierarchical Synthesis of Mixed-Signal Systems with Fully Integrated
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FPGA-based Networking Systems for High Data-rate and Reliable In-vehicle Communications [p. 480]
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New Safety Critical Radio Altimeter for Airbus and Related Design Flow [p. 684]
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Transaction Level Modeling of SCA Compliant Software Defined Radio Waveforms and
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Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture:
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Dynamic Reconfiguration in Sensor Networks with Regenerative Energy Sources [p. 1054]
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Evaluation of Design for Reliability Techniques in Embedded Flash Memories [p. 1593]
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Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing [p. 1544]
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A Decomposition-based Constraint Optimization Approach for Statically Scheduling Task
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(374) Hard- and Software Modularity of the NOVA MPSoC Platform [p. 1102]
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Mapping the Physical Layer of Radio Standards to Multiprocessor Architectures [p. 1412]
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A New Technique for Characterization of Digital-to-Analog Converters in High-Speed Systems [p. 433]
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DFM/DFY: Should You Trust the Surgeon or the Family Doctor? [p. 439]
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Scalable Reconfigurable Channel Decoder Architecture for Future Wireless Handsets [p. 1563]
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Low Power Design on Algorithmic and Architectural Level: A Case Study of an HSDPA Baseband
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Design Methods for Security and Trust [p. 672]
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(252) An Enhanced Technique for the Automatic Generation of Effective Diagnosis-oriented Test
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Trade-Off Design of Analog Circuits Using Goal Attainment and "Wave Front" Sequential Quadratic
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Performance Analysis of Complex Systems by Integration of Dataflow Graphs and
Compositional Performance Analysis [p. 273]
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System Level Clock Tree Synthesis for Power Optimization [p. 1677]
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System Level Clock Tree Synthesis for Power Optimization [p. 1677]
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Statistical Simulation of High-Frequency Bipolar Circuits [p. 1397]
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From Algorithm to First 3.5G Call in Record Time . A Novel System Design Approach Based
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Time-Constrained Clustering for DSE of Clustered VLIW-ASP [p. 467]
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Impact of Description Language, Abstraction Layer, and Value Representation on
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An Efficient Methodology for Hierarchical Synthesis of Mixed-Signal Systems with Fully Integrated
Building Block Topology Selection [p. 81]
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Diagnosis, Modeling and Tolerance of Scan Chain Hold-Time Violations [p. 516]
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Statistical Simulation of High-Frequency Bipolar Circuits [p. 1397]
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J.
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Dynamic Critical Resistance: A Timing-Based Critical Resistance Model for Statistical
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CMCal: An Accurate Analytical Approach for the Analysis of Process Variations with
Non-Gaussian Parameters and Nonlinear Functions [p. 243]
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I.
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An Area Optimized Reconfigurable Encryptor for AES-Rijndael [p. 1116]
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S.-W.
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An Efficient Code Compression Technique Using Application-Aware Bitmask and Dictionary
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Automatic Model Generation for Black Box Real-Time Systems [p. 930]
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Verification-Guided Soft Error Resilience [p. 1442]
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E.H.-M.
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Energy Minimization with Soft Real-time and DVS for Uniprocessor and Multiprocessor
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Improving Utilization of Reconfigurable Resources Using Two-Dimensional Compaction [p. 135]
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M.
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A Shift Register Based Clause Evaluator for Reconfigurable SAT Solver [p. 153]
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L.
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Accurate Temperature-Dependent Integrated Circuit Leakage Power Estimation Is Easy [p. 1526]
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Z.
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Energy Minimization with Soft Real-time and DVS for Uniprocessor and Multiprocessor
Embedded Systems [p. 1641]
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N.
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Image Computation and Predicate Refinement for RTL Verilog Using Word Level Proofs [p. 1325]
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Accurate Timing Analysis Using SAT and Pattern-Dependent Delay Models [p. 1018]
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(142) Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations
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Soft-core Processor Customization Using the Design of Experiments Paradigm [p. 821]
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Z.J.
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Microarchitectural Support for Program Code Integrity Monitoring in Application-specific
Instruction Set Processors [p. 815]
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A.
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(161) Functional and Timing Validation of Partially Bypassed Processor Pipelines [p. 1164]
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Tackling an Abstraction Gap: Co-Simulating with SystemC DE and Bluespec ESL [p. 279]
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Design Fault Directed Test Generation for Microprocessor Validation [p. 761]
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Low-cost Protection for SER Upsets and Silicon Defects [p. 1146]
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L.M.
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Efficient Computation of the Worst-Delay Corner [p. 1617]
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Temperature Aware Task Scheduling in MPSoCs [p. 1659]
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A Non-Intrusive Isolation Approach for Soft Cores [p. 27]
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Diagnosis, Modeling and Tolerance of Scan Chain Hold-Time Violations [p. 516]
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N.K.
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The Impact of Loop Unrolling on Controller Delay in High Level Synthesis [p. 391]
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A.
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Statistical Blockade: A Novel Method for Very Fast Monte Carlo Simulation of Rare Circuit
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Two-Level Microprocessor-Accelerator Partitioning [p. 313]
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Clock-Frequency Assignment for Multiple Clock Domain Systems-on-a-Chip [p. 397]
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Impact of Process Variations on Multicore Performance Symmetry [p. 1653]
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Cyclostationary Feature Detection on a Tiled-SoC [p. 171]
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Event Driven Data Processing Architecture [p. 972]
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Simulation Methodology and Experimental Verification for the Analysis of Substrate Noise on LC-VCO's [p. 1520]
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J.-P.
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Using Dynamic Voltage Scaling to Reduce the Configuration Energy of Run Time Reconfigurable
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S.W.
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Memory Bank Aware Dynamic Loop Scheduling [p. 1671]
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J.
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Use of Statistical Timing Analysis on Real Designs [p. 1605]
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M.
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(252) An Enhanced Technique for the Automatic Generation of Effective Diagnosis-oriented Test
Programs for Processor [p. 1158]
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D.
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Middleware Design Optimization of Wireless Protocols Based on the Exploitation of Dynamic
Input Patterns [p. 1036]
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A Sophisticated Memory Test Engine for LCD Display Drivers [p. 213]
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J.
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A Scalable, Timing-Safe, Network-on-Chip Architecture with an Integrated Clock Distribution Method [p. 648]
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Fast and Accurate Routing Demand Estimation for Efficient Routability-driven Placement [p. 1226]
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G.
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(252) An Enhanced Technique for the Automatic Generation of Effective Diagnosis-oriented Test
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N.R.
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Radix 4 SRT Division with Quotient Prediction and Operand Scaling [p. 195]
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S.
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Rapid and Accurate Latch Characterization via Direct Newton Solution of Setup/Hold Times [p. 1006]
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An 0.9 X 1.2", Low Power, Energy-Harvesting System with Custom Multi-Channel
Communication Interface [p. 15]
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W.
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Using Partial-Run-Time Reconfigurable Hardware to Accelerate Video Processing in
Driver Assistance Systems [p. 498]
- Stefanov,
T.
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Performance Analysis of Multimedia Applications Using Correlated Streams [p. 912]
- Steger,
C.
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Simulation Platform for UHF RFID [p. 918]
- Stein,
S.
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Performance Analysis of Complex Systems by Integration of Dataflow Graphs and
Compositional Performance Analysis [p. 273]
- Steininger,
T.
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Impact of Description Language, Abstraction Layer, and Value Representation on
Simulation Performance [p. 767]
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Implementation of a Transaction Level Assertion Framework in SystemC [p. 894]
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M.B.
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A Scalable, Timing-Safe, Network-on-Chip Architecture with an Integrated Clock Distribution Method [p. 648]
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P.
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Microprocessors in the Era of Terascale Integration [p. 237]
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M.
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An Efficient Methodology for Hierarchical Synthesis of Mixed-Signal Systems with Fully Integrated
Building Block Topology Selection [p. 81]
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G.
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Capturing the Interaction of the Communication, Memory and I/O Subsystems in Memory-Centric
Industrial MPSoC Platforms [p. 660]
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T.
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Reliability-Aware System Synthesis [p. 409]
- Sugihara,
M.
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Task Scheduling for Reliable Cache Architectures of Multiprocessor Systems [p. 1490]
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J.
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Cost-Aware Capacity Optimization in Dynamic Multi-Hop WSNs [p. 666]
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P.
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Flexibility-oriented Design Methodology for Reconfigurable Delta Sigma Modulators [p. 415]
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J.
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Compositional Specification of Behavioral Semantics [p. 906]
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G.
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Timing Simulation of Interconnected AUTOSAR Software-Components [p. 474]
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Accurate Timing Analysis Using SAT and Pattern-Dependent Delay Models [p. 1018]
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S.
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A Symbolic Methodology for the Verification of Analog and Mixed Signal Designs [p. 249]
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S.
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A Coefficient Optimization and Architecture Selection Tool for ∑Δ Modulators in MATLAB [p. 87]
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S.X.-D.
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Statistical Model Order Reduction for Interconnect Circuits Considering Spatial Correlations [p. 1508]
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Y.
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Stochastic Modeling and Optimization for Robust Power Management in a Partially
Observable System [p. 779]
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S.
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A Multi-Core Debug Platform for NoC-Based Systems [p. 870]
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D.
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Efficient Nonlinear Distortion Analysis of RF Circuits [p. 255]
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Impact of Process Variations on Multicore Performance Symmetry [p. 1653]
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Tool-Support for the Analysis of Hybrid Systems and Models [p. 924]
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J.
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Reliability-Aware System Synthesis [p. 409]
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ATLAS: A Chip-Multiprocessor with Transactional Memory Support [p. 3]
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Experimental Evaluation of Protections against Laser-induced Faults and Consequences
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Adaptive Power Management in Energy Harvesting Systems [p. 773]
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L.
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Performance Analysis of Multimedia Applications Using Correlated Streams [p. 912]
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A New Pipelined Implementation for Minimum Norm Sorting Used in Square Root
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Executable System-Level Specification Models Containing UML-Based Behavioral Patterns [p. 301]
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Energy Evaluation of Software Implementations of Block Ciphers under Memory Constraints [p. 1110]
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WAVSTAN: Waveform Based Variational Static Timing Analysis [p. 1000]
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Implementation of AES/Rijndael on a Dynamically Reconfigurable Architecture [p. 355]
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FPGA-based Networking Systems for High Data-rate and Reliable In-vehicle Communications [p. 480]
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Low-g Accelerometer Fast Prototyping for Automotive Applications [p. 486]
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D.
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Clock Domain Crossing Fault Model and Coverage Metric for Validation of SoC Design [p. 1385]
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Evaluation of Test Measures for LNA Production Testing Using a Multinormal Statistical Model [p. 731]
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Novel Test Infrastructure and Methodology Used for Accelerated Bring-Up and In-System
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Evaluation of Design for Reliability Techniques in Embedded Flash Memories [p. 1593]
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RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
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Experimental Evaluation of Protections against Laser-induced Faults and Consequences
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Use of Statistical Timing Analysis on Real Designs [p. 1605]
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Double-Via-Driven Standard Cell Library Design [p. 1212]
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A Process Splitting Transformation for Kahn Process Networks [p. 1355]
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Modeling and Simulation Alternatives for the Design of Networked Embedded Systems [p. 1030]
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Optimization of the "FOCUS" Inband-FEC Architecture for 10-Gbps SDH/SONET Optical
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Two-Level Microprocessor-Accelerator Partitioning [p. 313]
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Clock-Frequency Assignment for Multiple Clock Domain Systems-on-a-Chip [p. 397]
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A One-Shot Configurable-Cache Tuner for Improved Energy and Performance [p. 755]
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Soft-core Processor Customization Using the Design of Experiments Paradigm [p. 821]
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Congestion-Controlled Best-Effort Communication for Networks-on-Chip [p. 948]
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Simulation Methodology and Experimental Verification for the Analysis of Substrate Noise on LC-VCO's [p. 1520]
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Feasibility of Combined Area and Performance Optimization for Superscalar Processors Using
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Development of an ASIP Enabling Flows in Ethernet Access Using a Retargetable Compilation Flow [p. 1418]
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Fast Memory Footprint Estimation Based on Maximal Dependency Vector Calculation [p. 379]
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Simulation Methodology and Experimental Verification for the Analysis of Substrate Noise on LC-VCO's [p. 1520]
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Optimizing Analog Filter Designs for Minimum Nonlinear Distortions Using Multisine Excitations [p. 267]
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Development of an ASIP Enabling Flows in Ethernet Access Using a Retargetable Compilation Flow [p. 1418]
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Life Begins at 65 - Unless You Are Mixed Signal? [p. 936]
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A Dynamically Adaptive DSP for Heterogeneous Reconfigurable Platforms[p. 9]
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Implementation of AES/Rijndael on a Dynamically Reconfigurable Architecture [p. 355]
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PowerQuest: Trace Driven Data Mining for Power Optimization [p. 1078]
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Impact of Description Language, Abstraction Layer, and Value Representation on
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Implementation of a Transaction Level Assertion Framework in SystemC [p. 894]
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Yield-aware Placement Optimization [p. 1232]
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Abstraction and Refinement Techniques in Automated Design Debugging [p. 1182]
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Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability [p. 1538]
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Design Methods for Security and Trust [p. 672]
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Transaction Level Modeling of SCA Compliant Software Defined Radio Waveforms and
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Development of an ASIP Enabling Flows in Ethernet Access Using a Retargetable Compilation Flow [p. 1418]
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Very Wide Register: An Asymmetric Register File Organization for Low Power Embedded Processors [p. 1066]
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Automatic Synthesis of Compressor Trees: Reevaluating Large Counters [p. 443]
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Automatic Generation of Functional Coverage Models from Behavioral Verilog Descriptions [p. 900]
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A One-Shot Configurable-Cache Tuner for Improved Energy and Performance [p. 755]
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Assessing Carbon Nanotube Bundle Interconnect for Future FPGA Architectures [p. 307]
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Thermally Robust Clocking Schemes for 3D Integrated Circuits [p. 1206]
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Lightweight Middleware for Seamless HW-SW Interoperability, with Application to
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Lightweight Middleware for Seamless HW-SW Interoperability, with Application to
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Slow Write Driver Faults in 65nm SRAM Technology: Analysis and March Test Solution [p. 528]
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A Dynamically Adaptive DSP for Heterogeneous Reconfigurable Platforms[p. 9]
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Development and Industrialization [p. 1403]
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A Sophisticated Memory Test Engine for LCD Display Drivers [p. 213]
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Engineering Trust with Semantic Guardians [p. 743]
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A Sophisticated Memory Test Engine for LCD Display Drivers [p. 213]
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Nonlinearity Analysis of Analog/RF Circuits Using Combined Multisine and Volterra Analysis [p. 261]
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A Novel Criticality Computation Method in Statistical Timing Analysis [p. 1611]
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Automatic Model Generation for Black Box Real-Time Systems [p. 930]
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Unknown Blocking Scheme for Low Control Data Volume and High Observability [p. 33]
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SoC Testing Using LFSR Reseeding, and Scan-Slice-Based TAM Optimization and Test Scheduling [p. 201]
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High-Level Test Synthesis for Delay Fault Testability [p. 45]
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Minimum-Energy LDPC Decoder for Real-Time Mobile Application [p. 343]
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Temperature-aware NBTI Modeling and the Impact of Input Vector Control on Performance Degradation [p. 546]
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SoC Testing Using LFSR Reseeding, and Scan-Slice-Based TAM Optimization and Test Scheduling [p. 201]
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Modeling and Simulation to the Design of ZΔ Fractional-N Frequency Synthesizer [p. 291]
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Life Begins at 65 - Unless You Are Mixed Signal? [p. 936]
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Task Scheduling under Performance Constraints for Reducing the Energy Consumption of GALS
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ATLAS: A Chip-Multiprocessor with Transactional Memory Support [p. 3]
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Understanding Voltage Variations in Chip Multiprocessors Using a Distributed Power-Delivery Network [p. 624]
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Unknown Blocking Scheme for Low Control Data Volume and High Observability [p. 33]
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Flexibility-oriented Design Methodology for Reconfigurable Delta Sigma Modulators [p. 415]
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Automatic Hardware Synthesis from Specifications: A Case Study [p. 1188]
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Simulation Platform for UHF RFID [p. 918]
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Low Complexity LDPC Code Decoders for Next Generation Standards [p. 331]
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Temperature Aware Task Scheduling in MPSoCs [p. 1659]
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Optimization-based Wideband Basis Functions for Efficient Interconnect Extraction [p. 1200]
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Design and DFT of a High-Speed Area-Efficient Embedded Asynchronous FIFO [p. 853]
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Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO [p. 859]
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Towards Total Open Source in Aeronautics and Space? [p. 1556]
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Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops [p. 1012]
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What If You Could Design Tomorrow's System Today? [p. 835]
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Simulation Platform for UHF RFID [p. 918]
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Statistical Simulation of High-Frequency Bipolar Circuits [p. 1397]
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Life Begins at 65 - Unless You Are Mixed Signal? [p. 936]
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A New Asymmetric SRAM Cell to Reduce Soft Errors and Leakage Power in FPGA [p. 1460]
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N.
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Fast Positive-Real Balanced Truncation of Symmetric Systems Using Cross Riccati Equations [p. 1496]
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DRIM: A Low Power Dynamically Reconfigurable Instruction Memory Hierarchy for
Embedded Systems [p. 1343]
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Design and DFT of a High-Speed Area-Efficient Embedded Asynchronous FIFO [p. 853]
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Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO [p. 859]
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QuteSAT: A Robust Circuit-based SAT Solver for Complex Circuit Structure [p. 1313]
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Q.
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Stochastic Modeling and Optimization for Robust Power Management in a Partially
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Y.
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Two-Level Microprocessor-Accelerator Partitioning [p. 313]
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Clock-Frequency Assignment for Multiple Clock Domain Systems-on-a-Chip [p. 397]
- Wu,
X.
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System Level Power Optimization of Sigma-Delta Modulator [p. 297]
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A.
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Design Closure Driven Delay Relaxation Based on Convex Cost Network Flow [p. 63]
- Xie,
Y.
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Temperature-aware NBTI Modeling and the Impact of Input Vector Control on Performance Degradation [p. 546]
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A Novel Criticality Computation Method in Statistical Timing Analysis [p. 1611]
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J.
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Analysis of Power Consumption and BER of Flip-flop Based Interconnect Pipelining [p. 1218]
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Q.
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A Multi-Core Debug Platform for NoC-Based Systems [p. 870]
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T.
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A Cross-Referencing-Based Droplet Manipulation Method for High-Throughput and
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C.
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Energy Minimization with Soft Real-time and DVS for Uniprocessor and Multiprocessor
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J.
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A Sparse Grid Based Spectral Stochastic Collocation Method for Variations-Aware Capacitance
Extraction of Interconnects under Nanometer Process Technology [p. 1514]
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C.-L.
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Energy-Efficient Real-Time Task Scheduling with Task Rejection [p. 1629]
- Yang,
H.
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Temperature-aware NBTI Modeling and the Impact of Input Vector Control on Performance Degradation [p. 546]
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Accurate Temperature-Dependent Integrated Circuit Leakage Power Estimation Is Easy [p. 1526]
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S.
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Computing Synchronizer Failure Probabilities [p. 1361]
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S.-H.
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Overcoming Glitches and Dissipation Timing Skews in Design of DPA-Resistant Cryptographic
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Z.
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An FPGA Based All-Digital Transmitter with Radio Frequency Output for Software Defined Radio [p. 21]
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T.-H.
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High-Level Test Synthesis for Delay Fault Testability [p. 45]
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T.
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Memory Bank Aware Dynamic Loop Scheduling [p. 1671]
- Yetik,
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A Coefficient Optimization and Architecture Selection Tool for ∑Δ Modulators in MATLAB [p. 87]
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P.
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Novel Test Infrastructure and Methodology Used for Accelerated Bring-Up and In-System
Characterization of the Multi-Gigahertz Interfaces on the Cell Processor [p. 725]
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T.
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An SoC Test Scheduling Algorithm Using Reconfigurable Union Wrappers [p. 231]
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C.P.
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A Two-Tone Test Method for Continuous-Time Adaptive Equalizers [p. 1283]
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M. H.
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A Symbolic Methodology for the Verification of Analog and Mixed Signal Designs [p. 249]
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M.
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An Effective AMS Top-Down Methodology Applied to the Design of a Mixed-Signal
UWB System-on-Chip [p. 1424]
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J.
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An FPGA Implementation of Decision Tree Classification [p. 189]
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N. H.
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Distributed Power-Management Techniques for Wireless Network Video Systems [p. 564]
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Techniques for Designing Noise-Tolerant Multi-Level Combinational Circuits [p. 576]
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X.
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A Sparse Grid Based Spectral Stochastic Collocation Method for Variations-Aware Capacitance
Extraction of Interconnects under Nanometer Process Technology [p. 1514]
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J.
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Using Partial-Run-Time Reconfigurable Hardware to Accelerate Video Processing in
Driver Assistance Systems [p. 498]
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M.
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CMCal: An Accurate Analytical Approach for the Analysis of Process Variations with
Non-Gaussian Parameters and Nonlinear Functions [p. 243]
- Zhao,
W.
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Fast Statistical Circuit Analysis with Finite-Point Based Transistor Model [p. 1391]
- Zheng,
W.
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(694) Synthesis of Task and Message Activation Models in Real-Time Distributed Automotive Systems [p. 93]
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Automatic Model Generation for Black Box Real-Time Systems [p. 930]
- Zhou,
D.
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A Sparse Grid Based Spectral Stochastic Collocation Method for Variations-Aware Capacitance
Extraction of Interconnects under Nanometer Process Technology [p. 1514]
- Zhou,
G.
-
Reconfigurable System-on-Chip Data Processing Units for Space Imaging Instruments [p. 977]
- Zhou,
H.
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Design Closure Driven Delay Relaxation Based on Convex Cost Network Flow [p. 63]
- Zhou,
Q.
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Test Cost Reduction for SoC Using a Combined Approach to Test Data Compression and
Test Scheduling [p. 39]
- Zhou,
Z.
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Clock Domain Crossing Fault Model and Coverage Metric for Validation of SoC Design [p. 1385]
- Zhu,
He.
-
A Sparse Grid Based Spectral Stochastic Collocation Method for Variations-Aware Capacitance
Extraction of Interconnects under Nanometer Process Technology [p. 1514]
- Zhu,
Ho.
-
Mapping Multi-Dimensional Signals into Hierarchical Memory Organizations [p. 385]
- Zhu,
Q.
-
(161) Functional and Timing Validation of Partially Bypassed Processor Pipelines [p. 1164]
- Zhu,
Z.
-
Random Sampling of Moment Graph: A Stochastic Krylov-Reduction Algorithm [p. 1502]
- Zilic,
Z.
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Reversible Circuit Technology Mapping from Non-reversible Specifications [p. 558]
- Zjajo,
A.
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BIST Method for Die-Level Process Parameter Variation Monitoring in Analog/Mixed-Signal
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