DATE 2007 AUTHOR INDEX

[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [V] [W] [X] [Y] [Z]


A

Aaraj, N.
PDF icon Energy and Execution Time Analysis of a Software-based Trusted Platform Module [p. 1128]
Abadir, M.S.
PDF icon Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability [p. 1538]
Abbasfar, A.-A.
PDF icon A New Technique for Characterization of Digital-to-Analog Converters in High-Speed Systems [p. 433]
Aboulhamid, M.
PDF icon Seamless Hardware/Software Performance Co-Monitoring in a Codesign Simulation Environment with RTOS Support [p. 876]
Acquaviva, A.
PDF icon Dynamic Reconfiguration in Sensor Networks with Regenerative Energy Sources [p. 1054]
Aggarwal, V.
PDF icon Simulation-based Reusable Posynomial Models for MOS Transistor Parameters [p. 69]
Ahmed, W.
PDF icon Design Space Exploration of Partially Re-Configurable Embedded Processors [p. 319]
Aitken, R.
PDF icon DFM/DFY: Should You Trust the Surgeon or the Family Doctor? [p. 439]
PDF icon Worst-Case Design and Margin for Embedded SRAM [p. 1289]
Aktouf, C.
PDF icon Remote Testing and Diagnosis of System-on-Chips Using Network Management Frameworks [p. 373]
Alachiotis, N.
PDF icon A Decoupled Architecture of Processors with Scratch-Pad Memory Hierarchy [p. 612]
Alam, M.
PDF icon An Area Optimized Reconfigurable Encryptor for AES-Rijndael [p. 1116]
Alessio, E.
PDF icon Modeling and Simulation Alternatives for the Design of Networked Embedded Systems [p. 1030]
Al-Hashimi, B.M.
PDF icon Joint Consideration of Fault-Tolerance, Energy-Efficiency and Performance in On-Chip Networks [p. 1647]
Alho, T.
PDF icon Compact Hardware Design of Whirlpool Hashing Core [p. 1247]
Alles, M.
PDF icon Low Complexity LDPC Code Decoders for Next Generation Standards [p. 331]
Al-Sammane, G.
PDF icon A Symbolic Methodology for the Verification of Analog and Mixed Signal Designs [p. 249]
Altheimer, M.
PDF icon Design and DFT of a High-Speed Area-Efficient Embedded Asynchronous FIFO [p. 853]
Aminzadeh, H.
PDF icon Design of High-Resolution MOSFET-Only Pipelined ADCs with Digital Calibration [p. 427]
Amirkhany, A.
PDF icon A New Technique for Characterization of Digital-to-Analog Converters in High-Speed Systems [p. 433]
Ammari, A.
PDF icon Experimental Evaluation of Protections against Laser-induced Faults and Consequences on Fault Modeling [p. 1587]
Anders, J.
PDF icon Re-Configuration of Sub-blocks for Effective Application of Time Domain Tests [p. 707]
Angiolini, F.
PDF icon Improving the Fault Tolerance of Nanometric PLA Designs [p. 570]
Anis, E.
PDF icon Low Cost Debug Architecture Using Lossy Compression for Silicon Debug [p. 225]
Antonau, A.
PDF icon Use of Statistical Timing Analysis on Real Designs [p. 1605]
Arbelo, C.
PDF icon Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture: The H.264/AVC Deblocking Filter [p. 177]
Arning, R.
PDF icon The Methodological and Technological Dimensions of Technology Transfer for Embedded Systems in Aeronautics and Space [p. 1108]
Arslan, T.
PDF icon Pipelined Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Architecture [p. 349]
PDF icon A New Pipelined Implementation for Minimum Norm Sorting Used in Square Root Algorithm for MIMO-VBLAST Systems [p. 1569]
Ascheid, G.
PDF icon Design Space Exploration of Partially Re-Configurable Embedded Processors [p. 319]
PDF icon SoftSIMD . Exploiting Subword Parallelism Using Source Code Transformations [p. 1349]
Askar, S.
PDF icon Data-Flow Transformations Using Taylor Expansion Diagrams [p. 455]
Atasu, K.
PDF icon Optimizing Instruction-set Extensible Processors under Data Bandwidth Constraints [p. 588]
Atienza, D.
PDF icon Improving the Fault Tolerance of Nanometric PLA Designs [p. 570]
Attariyan, M.
PDF icon Low-cost Protection for SER Upsets and Silicon Defects [p. 1146]
Aulagnier, D.
PDF icon RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
Austin, T.
PDF icon Low-cost Protection for SER Upsets and Silicon Defects [p. 1146]
Azemard, N.
PDF icon Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops [p. 1012]
Azimane, M.
PDF icon Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO [p. 859]
Azzoni, P.
PDF icon Yield-aware Placement Optimization [p. 1232]

B

Babighian, P.
PDF icon PowerQuest: Trace Driven Data Mining for Power Optimization [p. 1078]
Baghdadi, A.
PDF icon Butterfly and Benes-Based On-Chip Communication Networks for Multiprocessor Turbo Decoding [p. 654]
Baguena, L.
PDF icon Development of on Board, Highly Flexible, Galileo Signal Generator ASIC [p. 679]
Bahar, R.I.
PDF icon Techniques for Designing Noise-Tolerant Multi-Level Combinational Circuits [p. 576]
PDF icon Accurate Timing Analysis Using SAT and Pattern-Dependent Delay Models [p. 1018]
Balakrishnan, K.J.
PDF icon Test Cost Reduction for SoC Using a Combined Approach to Test Data Compression and Test Scheduling [p. 39]
Balasa, F.
PDF icon Mapping Multi-Dimensional Signals into Hierarchical Memory Organizations [p. 385]
Balfour, J.D.
PDF icon Register Pointer Architecture for Efficient Embedded Processors [p. 600]
Banda, S.
PDF icon Behavioral Modeling of Delay-Locked Loops and Its Application to Jitter Optimization in Ultra Wide-Band Impulse Radio Systems [p. 1430]
Bañeres, D.
PDF icon Layout-Aware Gate Duplication and Buffer Insertion [p. 1367]
Banerjee, N.
PDF icon Process Variation Tolerant Low Power DCT Architecture [p. 630]
Bantegnie, E.
PDF icon Towards Total Open Source in Aeronautics and Space? [p. 1556]
Barajas, E.
PDF icon Behavioral Modeling of Delay-Locked Loops and Its Application to Jitter Optimization in Ultra Wide-Band Impulse Radio Systems [p. 1430]
Barba, J.
PDF icon Lightweight Middleware for Seamless HW-SW Interoperability, with Application to Wireless Sensor Networks [p. 1042]
Barke, E.
PDF icon CMCal: An Accurate Analytical Approach for the Analysis of Process Variations with Non-Gaussian Parameters and Nonlinear Functions [p. 243]
Barragan Asian, M.J.
PDF icon BIST Method for Die-Level Process Parameter Variation Monitoring in Analog/Mixed-Signal Integrated Circuits [p. 1303]
Barros, E.
PDF icon A One-Shot Configurable-Cache Tuner for Improved Energy and Performance [p. 755]
Baschirotto, A.
PDF icon Experimental Validation of a Tuning Algorithm for High-Speed Filters [p. 421]
Basten, T.
PDF icon A Calculator for Pareto Points [p. 285]
PDF icon Congestion-Controlled Best-Effort Communication for Networks-on-Chip [p. 948]
Bastian, M.
PDF icon Slow Write Driver Faults in 65nm SRAM Technology: Analysis and March Test Solution [p. 528]
Batra, P.
PDF icon Novel Test Infrastructure and Methodology Used for Accelerated Bring-Up and In-System Characterization of the Multi-Gigahertz Interfaces on the Cell Processor [p. 725]
Bauer, A.
PDF icon Tool-Support for the Analysis of Hybrid Systems and Models [p. 924]
Baumgartner, J.
PDF icon Formal Verification of a Pervasive Interconnect Bus System in a High-Performance Microprocessor [p. 219]
Bazargan, K.
PDF icon Microarchitecture Floorplanning for Sub-threshold Leakage Reduction [p. 1238]
Bellocq, P.
PDF icon Development of on Board, Highly Flexible, Galileo Signal Generator ASIC [p. 679]
Benini, L.
PDF icon Improving the Fault Tolerance of Nanometric PLA Designs [p. 570]
PDF icon Capturing the Interaction of the Communication, Memory and I/O Subsystems in Memory-Centric Industrial MPSoC Platforms [p. 660]
PDF icon Adaptive Power Management in Energy Harvesting Systems [p. 773]
PDF icon Dynamic Reconfiguration in Sensor Networks with Regenerative Energy Sources [p. 1054]
PDF icon Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing [p. 1544]
Bepoix, A.
PDF icon Development of on Board, Highly Flexible, Galileo Signal Generator ASIC [p. 679]
Berekovic, M.
PDF icon Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture: The H.264/AVC Deblocking Filter [p. 177]
Bertacco, V.
PDF icon Engineering Trust with Semantic Guardians [p. 743]
PDF icon Low-cost Protection for SER Upsets and Silicon Defects [p. 1146]
Bertoletti, M.
PDF icon Yield-aware Placement Optimization [p. 1232]
Bertozzi, D.
PDF icon Capturing the Interaction of the Communication, Memory and I/O Subsystems in Memory-Centric Industrial MPSoC Platforms [p. 660]
Bhunia, S.
PDF icon Low-Overhead Circuit Synthesis for Temperature Adaptation Using Dynamic Voltage Scheduling [p. 1532]
Bjerregaard, T.
PDF icon A Scalable, Timing-Safe, Network-on-Chip Architecture with an Integrated Clock Distribution Method [p. 648]
Bjesse, B.
PDF icon A Compositional Approach to the Combination of Combinational and Sequential Equivalence Checking of Circuits without Known Reset States [p. 1170]
Black-Schaffer, D.
PDF icon Register Pointer Architecture for Efficient Embedded Processors [p. 600]
Bloem, R.
PDF icon Automatic Hardware Synthesis from Specifications: A Case Study [p. 1188]
Bois, G.
PDF icon Seamless Hardware/Software Performance Co-Monitoring in a Codesign Simulation Environment with RTOS Support [p. 876]
Bolotin, E.
PDF icon Routing Table Minimization for Irregular Mesh NoCs [p. 942]
Bombieri, N.
PDF icon Incremental ABV for Functional Validation of TL-to-RTL Design Refinement [p. 882]
Bondarev, E.
PDF icon CARAT: A Toolkit for Design and Performance Analysis of Component-Based Embedded Systems [p. 1024]
Bonny, T.
PDF icon Efficient Code Density through Look-up Table Compression [p. 809]
Bonzini, P.
PDF icon Polynomial-Time Subgraph Enumeration for Automated Instruction Set Extension [p. 1331]
Borkar, S.
PDF icon Microprocessors in the Era of Terascale Integration [p. 237]
Borremans, J.
PDF icon Nonlinearity Analysis of Analog/RF Circuits Using Combined Multisine and Volterra Analysis [p. 261]
Boschi, G.
PDF icon Using an Innovative SOC-level FMEA Methodology to Design in Compliance with IEC61508 [p. 492]
Bota, S.A.
PDF icon Dynamic Critical Resistance: A Timing-Based Critical Resistance Model for Statistical Delay Testing of Nanometer ICs [p. 1271]
Botti, J.
PDF icon Flying Embedded: The Industrial Scene and Challenges for Embedded Systems in Aeronautics and Space [p. 1246]
Bouchebaba, Y.
PDF icon (408) System Level Assessment of an Optical NoC in an MPSoC Platform [p. 1084]
Boutillon, E.
PDF icon Data-Flow Transformations Using Taylor Expansion Diagrams [p. 455]
Brack, T.
PDF icon Low Complexity LDPC Code Decoders for Next Generation Standards [p. 331]
Brandenburg, M.
PDF icon From Algorithm to First 3.5G Call in Record Time . A Novel System Design Approach Based on Virtual Prototyping and Its Consequences for Interdisciplinary System Design Teams [p. 828]
Breuer, M.A.
PDF icon Reduction of Detected Acceptable Faults for Yield Improvement via Error-Tolerance [p. 1599]
Brière, M.
PDF icon (408) System Level Assessment of an Optical NoC in an MPSoC Platform [p. 1084]
Bringmann, O.
PDF icon Timing Simulation of Interconnected AUTOSAR Software-Components [p. 474]
Bronckers, S.
PDF icon Simulation Methodology and Experimental Verification for the Analysis of Substrate Noise on LC-VCO's [p. 1520]
Brooks, D.M.
PDF icon Understanding Voltage Variations in Chip Multiprocessors Using a Distributed Power-Delivery Network [p. 624]
Brooks, R.
PDF icon Performance Aware Secure Code Partitioning [p. 1122]
Brunelli, D.
PDF icon Adaptive Power Management in Energy Harvesting Systems [p. 773]
Bücker, M.
PDF icon Low Power Design on Algorithmic and Architectural Level: A Case Study of an HSDPA Baseband Digital Signal Processing System [p. 1406]
Butt, S.A.
PDF icon System Level Clock Tree Synthesis for Power Optimization [p. 1677]

C

Cabodi, G.
PDF icon Boosting the Role of Inductive Invariants in Model Checking [p. 1319]
Cai, W.
PDF icon A Sparse Grid Based Spectral Stochastic Collocation Method for Variations-Aware Capacitance Extraction of Interconnects under Nanometer Process Technology [p. 1514]
Cai, Y.
PDF icon Statistical Model Order Reduction for Interconnect Circuits Considering Spatial Correlations [p. 1508]
Cairò, I.
PDF icon Behavioral Modeling of Delay-Locked Loops and Its Application to Jitter Optimization in Ultra Wide-Band Impulse Radio Systems [p. 1430]
Cakici, T.
PDF icon Processor Tolerant Beta-Ratio Modulation for Ultra-Dynamic Voltage Scaling [p. 1550]
Calder, B.
PDF icon Transient Fault Prediction Based on Anomalies in Processor Events [p. 1140]
Calimera, A.
PDF icon Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing [p. 1544]
Campi, F.
PDF icon A Dynamically Adaptive DSP for Heterogeneous Reconfigurable Platforms[p. 9]
PDF icon Implementation of AES/Rijndael on a Dynamically Reconfigurable Architecture [p. 355]
Cao, Y
PDF icon Fast Statistical Circuit Analysis with Finite-Point Based Transistor Model [p. 1391]
Carbonero, J.L.
PDF icon Evaluation of Test Measures for LNA Production Testing Using a Multinormal Statistical Model [p. 731]
Carro, L.
PDF icon A Low-SER Efficient Core Processor Architecture for Future Technologies [p. 1448]
Casper, J.
PDF icon ATLAS: A Chip-Multiprocessor with Transactional Memory Support [p. 3]
Caspi, P.
PDF icon Development and Industrialization [p. 1403]
Casu, M.R.
PDF icon An Effective AMS Top-Down Methodology Applied to the Design of a Mixed-Signal UWB System-on-Chip [p. 1424]
Catthoor, F.
PDF icon Fast Memory Footprint Estimation Based on Maximal Dependency Vector Calculation [p. 379]
PDF icon Middleware Design Optimization of Wireless Protocols Based on the Exploitation of Dynamic Input Patterns [p. 1036]
PDF icon Very Wide Register: An Asymmetric Register File Organization for Low Power Embedded Processors [p. 1066]
Caubit, G.
PDF icon Portable Multimedia SoC Design: A Global Challenge [p. 831]
Chakrabarty, K.
PDF icon SoC Testing Using LFSR Reseeding, and Scan-Slice-Based TAM Optimization and Test Scheduling [p. 201]
PDF icon A Cross-Referencing-Based Droplet Manipulation Method for High-Throughput and Pin-Constrained Digital Microfluidic Arrays [p. 552]
PDF icon Heterogeneous Systems on Chip and Systems in Package [p. 737]
Chakraborty, S.
PDF icon Accounting for Cache-Related Preemption Delay in Dynamic Priority Schedulability Analysis [p. 1623]
Chakradhar, S.T.
PDF icon Unknown Blocking Scheme for Low Control Data Volume and High Observability [p. 33]
Chang, Y.-J.
PDF icon Improve CAM Power Efficiency Using Decoupled Match Line Scheme [p. 165]
Chatha, K.S.
PDF icon (287) An ILP Formulation for System-Level Application Mapping on Network Processor Architectures [p. 99]
Chattopadhyay, A.
PDF icon Design Space Exploration of Partially Re-Configurable Embedded Processors [p. 319]
Chaudron, M.
PDF icon CARAT: A Toolkit for Design and Performance Analysis of Component-Based Embedded Systems [p. 1024]
Chen, J.-J.
PDF icon Energy-Efficient Real-Time Task Scheduling with Task Rejection [p. 1629]
Chen, K.
PDF icon Compositional Specification of Behavioral Semantics [p. 906]
Chen, M.
PDF icon Fast Statistical Circuit Analysis with Finite-Point Based Transistor Model [p. 1391]
Cheng, K.-T.
PDF icon Testable Design for Advanced Serial-Link Transceivers [p. 695]
PDF icon A Two-Tone Test Method for Continuous-Time Adaptive Equalizers [p. 1283]
PDF icon A Framework for System Reliability Analysis Considering Both System Error Tolerance and Component Test Quality [p. 1581]
Cheng, X.
PDF icon Clock Domain Crossing Fault Model and Coverage Metric for Validation of SoC Design [p. 1385]
Choi, G.
PDF icon Minimum-Energy LDPC Decoder for Real-Time Mobile Application [p. 343]
Chong, Y.J.
PDF icon Automatic Application Specific Floating-point Unit Generation [p. 461]
Choudhary, A.
PDF icon An FPGA Implementation of Decision Tree Classification [p. 189]
Choudhury, M.
PDF icon Single-ended Coding Techniques for Off-chip Interconnects to Commodity Memory [p. 1072]
PDF icon Accurate and Scalable Reliability Analysis of Logic Circuits [p. 1454]
Chowdhury, M.H.
PDF icon Analysis of Power Consumption and BER of Flip-flop Based Interconnect Pipelining [p. 1218]
Ciccarelli, L.
PDF icon A Dynamically Adaptive DSP for Heterogeneous Reconfigurable Platforms[p. 9]
Cidon, I.
PDF icon Routing Table Minimization for Irregular Mesh NoCs [p. 942]
Ciesielski, M.
PDF icon Data-Flow Transformations Using Taylor Expansion Diagrams [p. 455]
Ciordas, C.
PDF icon Congestion-Controlled Best-Effort Communication for Networks-on-Chip [p. 948]
Claus, C.
PDF icon Using Partial-Run-Time Reconfigurable Hardware to Accelerate Video Processing in Driver Assistance Systems [p. 498]
Coeffe, V.
PDF icon Portable Multimedia SoC Design: A Global Challenge [p. 831]
Coenen, M.
PDF icon Undisrupted Quality-of-Service during Reconfiguration of Multiple Applications in Networks on Chip [p. 954]
Colucci, F.
PDF icon Using an Innovative SOC-level FMEA Methodology to Design in Compliance with IEC61508 [p. 492]
Combot, E.
PDF icon New Safety Critical Radio Altimeter for Airbus and Related Design Flow [p. 684]
Constantinides, K.
PDF icon Low-cost Protection for SER Upsets and Silicon Defects [p. 1146]
Corporaal, H.
PDF icon (394) An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems on Chip [p. 117]
PDF icon Very Wide Register: An Asymmetric Register File Organization for Low Power Embedded Processors [p. 1066]
Corsi, F.
PDF icon Experimental Validation of a Tuning Algorithm for High-Speed Filters [p. 421]
Cortadella, J.
PDF icon Layout-Aware Gate Duplication and Buffer Insertion [p. 1367]
Cosculluela, R.
PDF icon Behavioral Modeling of Delay-Locked Loops and Its Application to Jitter Optimization in Ultra Wide-Band Impulse Radio Systems [p. 1430]
Coskun, A.
PDF icon Transient Fault Prediction Based on Anomalies in Processor Events [p. 1140]
Courtois, B.
PDF icon Heterogeneous Systems on Chip and Systems in Package [p. 737]
Coutinho, D.
PDF icon Behavioral Modeling of Delay-Locked Loops and Its Application to Jitter Optimization in Ultra Wide-Band Impulse Radio Systems [p. 1430]
Crepaldi, M.
PDF icon An Effective AMS Top-Down Methodology Applied to the Design of a Mixed-Signal UWB System-on-Chip [p. 1424]
Cucu, L.
PDF icon Feasibility Intervals for Multiprocessor Fixed-Priority Scheduling of Arbitrary Deadline Periodic Systems [p. 1635]
Cui, J.
PDF icon An Efficient Algorithm for Online Management of 2D Area of Partially Reconfigurable FPGAs [p. 129]

D

D'Ascoli, F.
PDF icon Low-g Accelerometer Fast Prototyping for Automotive Applications [p. 486]
Dabrowski J.
PDF icon Boosting SER Test for RF Transceivers by Simple DSP Technique [p. 719]
Daembkes, H.
PDF icon The Methodological and Technological Dimensions of Technology Transfer for Embedded Systems in Aeronautics and Space [p. 1108]
Daga, J.-M.
PDF icon Evaluation of Design for Reliability Techniques in Embedded Flash Memories [p. 1593]
Dalirsani, A.
PDF icon Using the Inter- and Intra-Switch Regularity in NoC Switch Testing [p. 361]
Dally, W.J.
PDF icon Register Pointer Architecture for Efficient Embedded Processors [p. 600]
D'Amico, S.
PDF icon Experimental Validation of a Tuning Algorithm for High-Speed Filters [p. 421]
Danaie, M.
PDF icon Design of High-Resolution MOSFET-Only Pipelined ADCs with Digital Calibration [p. 427]
Daniel, L.
PDF icon pFFT in FastMaxwell: A Fast Impedance Extraction Solver for 3D Conductor Structures over Substrate [p. 1194]
PDF icon Optimization-based Wideband Basis Functions for Efficient Interconnect Extraction [p. 1200]
Das, T.
PDF icon Sensitivity Analysis for Fault-analysis and Tolerance in RF Front-end Circuitry [p. 1277]
de Benito, C.
PDF icon Dynamic Critical Resistance: A Timing-Based Critical Resistance Model for Statistical Delay Testing of Nanometer ICs [p. 1271]
de Kock E.
PDF icon A Process Splitting Transformation for Kahn Process Networks [p. 1355]
De Locht, L.
PDF icon Nonlinearity Analysis of Analog/RF Circuits Using Combined Multisine and Volterra Analysis [p. 261]
De Marinis, M.
PDF icon Low-g Accelerometer Fast Prototyping for Automotive Applications [p. 486]
De Micheli G.
PDF icon Improving the Fault Tolerance of Nanometric PLA Designs [p. 570]
De Nanclas, M.
PDF icon Seamless Hardware/Software Performance Co-Monitoring in a Codesign Simulation Environment with RTOS Support [p. 876]
de With, P.H.N.
PDF icon CARAT: A Toolkit for Design and Performance Analysis of Component-Based Embedded Systems [p. 1024]
Dedeken, F.
PDF icon Enabling Certification for Dynamic Partial Reconfiguration Using a Minimal Flow [p. 983]
Del Corona, I.
PDF icon FPGA-based Networking Systems for High Data-rate and Reliable In-vehicle Communications [p. 480]
Deledda, A.
PDF icon A Dynamically Adaptive DSP for Heterogeneous Reconfigurable Platforms[p. 9]
PDF icon Implementation of AES/Rijndael on a Dynamically Reconfigurable Architecture [p. 355]
Delorme, N.
PDF icon Heterogeneous Systems on Chip and Systems in Package [p. 737]
Demuytere, P.
PDF icon Development of an ASIP Enabling Flows in Ethernet Access Using a Retargetable Compilation Flow [p. 1418]
Deng, Q.
PDF icon An Efficient Algorithm for Online Management of 2D Area of Partially Reconfigurable FPGAs [p. 129]
Deprettere, E.
PDF icon Performance Analysis of Multimedia Applications Using Correlated Streams [p. 912]
Derbek, V.
PDF icon Simulation Platform for UHF RFID [p. 918]
Destro, P.
PDF icon (231) A Smooth Refinement Flow for Co-Designing HW and SW Threads [p. 105]
Devanathan, V.R.
PDF icon On Power-profiling and Pattern Generation for Power-safe Scan Tests [p. 534]
Di Ciano, M.
PDF icon RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
Di Natale, M.
PDF icon (694) Synthesis of Task and Message Activation Models in Real-Time Distributed Automotive Systems [p. 93]
PDF icon Towards a Methodology for the Quantitative Evaluation of Automotive Architectures [p. 504]
Dick, R.P.
PDF icon Accurate Temperature-Dependent Integrated Circuit Leakage Power Estimation Is Easy [p. 1526]
Dielissen, J.
PDF icon Non-Fractional Parallelism in LDPC Decoder Implementations [p. 337]
Dierker, C.
PDF icon Reconfigurable System-on-Chip Data Processing Units for Space Imaging Instruments [p. 977]
Dimond, R.G.
PDF icon Optimizing Instruction-set Extensible Processors under Data Bandwidth Constraints [p. 588]
Dingankar, A.
PDF icon Design Fault Directed Test Generation for Microprocessor Validation [p. 761]
Dirk, S.
PDF icon (374) Hard- and Software Modularity of the NOVA MPSoC Platform [p. 1102]
Dittmann, F.
PDF icon Hard Real-Time Reconfiguration Port Scheduling [p. 123]
Dobili, A.
PDF icon Flexibility-oriented Design Methodology for Reconfigurable Delta Sigma Modulators [p. 415]
Domic, A.
PDF icon DFM/DFY: Should You Trust the Surgeon or the Family Doctor? [p. 439]
Dragone, N.
PDF icon Yield-aware Placement Optimization [p. 1232]
Drechsler, R.
PDF icon Estimating Functional Coverage in Bounded Model Checking [p. 1176]
Dubois, T.
PDF icon Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO [p. 859]
Ducharme, P.
PDF icon Method for Reducing Jitter in Multi-Gigahertz ATE [p. 701]
Ducrey, S.
PDF icon Portable Multimedia SoC Design: A Global Challenge [p. 831]
Dündar, G.
PDF icon A Coefficient Optimization and Architecture Selection Tool for ∑Δ Modulators in MATLAB [p. 87]
PDF icon Optimizing Instruction-set Extensible Processors under Data Bandwidth Constraints [p. 588]
Dusserre, J. M.
PDF icon Development of on Board, Highly Flexible, Galileo Signal Generator ASIC [p. 679]
Dutt, N.
PDF icon (161) Functional and Timing Validation of Partially Bypassed Processor Pipelines [p. 1164]

E

Eachempati, S.
PDF icon Assessing Carbon Nanotube Bundle Interconnect for Future FPGA Architectures [p. 307]
Eckart, T.
PDF icon From Algorithm to First 3.5G Call in Record Time . A Novel System Design Approach Based on Virtual Prototyping and Its Consequences for Interdisciplinary System Design Teams [p. 828]
Ecker, W.
PDF icon Impact of Description Language, Abstraction Layer, and Value Representation on Simulation Performance [p. 767]
PDF icon Implementation of a Transaction Level Assertion Framework in SystemC [p. 894]
Eckmüller, J.
PDF icon From Algorithm to First 3.5G Call in Record Time . A Novel System Design Approach Based on Virtual Prototyping and Its Consequences for Interdisciplinary System Design Teams [p. 828]
Eeckelaert, T.
PDF icon An Efficient Methodology for Hierarchical Synthesis of Mixed-Signal Systems with Fully Integrated Building Block Topology Selection [p. 81]
Eeckhout, L.
PDF icon Resource Prediction for Media Stream Decoding [p. 594]
Ejlali, A.
PDF icon Joint Consideration of Fault-Tolerance, Energy-Efficiency and Performance in On-Chip Networks [p. 1647]
El Farag, A.A.
PDF icon Improving Utilization of Reconfigurable Resources Using Two-Dimensional Compaction [p. 135]
El-Boghdadi, H.M.
PDF icon Improving Utilization of Reconfigurable Resources Using Two-Dimensional Compaction [p. 135]
Eles, P.
PDF icon Bus Access Optimisation for FlexRay-based Distributed Embedded Systems [p. 51]
PDF icon Optimized Integration of Test Compression and Sharing for SoC Testing [p. 207]
El-Kharashi, M. W.
PDF icon A Shift Register Based Clause Evaluator for Reconfigurable SAT Solver [p. 153]
Emeriau, S.
PDF icon New Safety Critical Radio Altimeter for Airbus and Related Design Flow [p. 684]
Engin, N.
PDF icon Scalable Reconfigurable Channel Decoder Architecture for Future Wireless Handsets [p. 1563]
Erdogan, E.S.
PDF icon An ADC-BiST Scheme Using Sequential Code Analysis [p. 713]
Erdogan, A.T.
PDF icon A New Pipelined Implementation for Minimum Norm Sorting Used in Square Root Algorithm for MIMO-VBLAST Systems [p. 1569]
Ernst, R.
PDF icon Performance Analysis of Complex Systems by Integration of Dataflow Graphs and Compositional Performance Analysis [p. 273]
Esen, V.
PDF icon Impact of Description Language, Abstraction Layer, and Value Representation on Simulation Performance [p. 767]
Esen, V.
PDF icon Implementation of a Transaction Level Assertion Framework in SystemC [p. 894]

F

Fan, J.
PDF icon Statistical Model Order Reduction for Interconnect Circuits Considering Spatial Correlations [p. 1508]
Fang, L.
PDF icon A New Hybrid Solution to Boost SAT Solver Performance [p. 1307]
Fang, S.C.
PDF icon Overcoming Glitches and Dissipation Timing Skews in Design of DPA-Resistant Cryptographic Hardware [p. 1265]
Fanucci, L.
PDF icon Low Complexity LDPC Code Decoders for Next Generation Standards [p. 331]
Fanucci, L.
PDF icon FPGA-based Networking Systems for High Data-rate and Reliable In-vehicle Communications [p. 480]
Fanucci, L.
PDF icon Low-g Accelerometer Fast Prototyping for Automotive Applications [p. 486]
Favalli, M.
PDF icon Pulse Propagation for the Detection of Small Delay Defects [p. 1295]
Fei, Y.
PDF icon Microarchitectural Support for Program Code Integrity Monitoring in Application-specific Instruction Set Processors [p. 815]
Feng, T.H.
PDF icon Automatic Model Generation for Black Box Real-Time Systems [p. 930]
Feng, Y.
PDF icon Clock Domain Crossing Fault Model and Coverage Metric for Validation of SoC Design [p. 1385]
Ferrigno, J.
PDF icon Identification of Process/Design Issues during 0.18 μm Technology Qualification for Space Application [p. 989]
Feyt, N.
PDF icon Experimental Evaluation of Protections against Laser-induced Faults and Consequences on Fault Modeling [p. 1587]
Fiethe, B.
PDF icon Reconfigurable System-on-Chip Data Processing Units for Space Imaging Instruments [p. 977]
Filion, L.
PDF icon Seamless Hardware/Software Performance Co-Monitoring in a Codesign Simulation Environment with RTOS Support [p. 876]
Flament, D.
PDF icon Industrial Applications [p. 1244]
Fontaine, S.
PDF icon Seamless Hardware/Software Performance Co-Monitoring in a Codesign Simulation Environment with RTOS Support [p. 876]
Franca, J.
PDF icon Life Begins at 65 - Unless You Are Mixed Signal? [p. 936]
Frank, S.
PDF icon Hard Real-Time Reconfiguration Port Scheduling [p. 123]
Frerichs, M.
PDF icon CMCal: An Accurate Analytical Approach for the Analysis of Process Variations with Non-Gaussian Parameters and Nonlinear Functions [p. 243]
Fujiwara, H.
PDF icon An SoC Test Scheduling Algorithm Using Reconfigurable Union Wrappers [p. 231]
Fummi, F.
PDF icon (231) A Smooth Refinement Flow for Co-Designing HW and SW Threads [p. 105]
PDF icon Incremental ABV for Functional Validation of TL-to-RTL Design Refinement [p. 882]
PDF icon Modeling and Simulation Alternatives for the Design of Networked Embedded Systems [p. 1030]
PDF icon A Middleware-centric Design Flow for Networked Embedded Systems [p. 1048]
PDF icon Yield-aware Placement Optimization [p. 1232]
Furuyama, T.
PDF icon Challenges of Digital Consumer and Mobile SOC's: More Moore Possible? [p. 1]

G

Gabriel, Y.
PDF icon Enabling Certification for Dynamic Partial Reconfiguration Using a Minimal Flow [p. 983]
Gabriel, Y.
PDF icon RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
Gaffiot, F.
PDF icon (408) System Level Assessment of an Optical NoC in an MPSoC Platform [p. 1084]
Gailliard, G.
PDF icon Transaction Level Modeling of SCA Compliant Software Defined Radio Waveforms and Platforms PIM/PSM [p. 966]
Gajski, D.
PDF icon Interrupt and Low-level Programming Support for Expanding the Application Domain of Statically-Scheduled Horizontally-Microcoded Architectures in Embedded Systems [p. 1337]
Galerin, D.
PDF icon Enabling Certification for Dynamic Partial Reconfiguration Using a Minimal Flow [p. 983]
Galivanche, R.
PDF icon Testing in the Year 2020 [p. 960]
Galler, S.
PDF icon Automatic Hardware Synthesis from Specifications: A Case Study [p. 1188]
Gamrat, C.
PDF icon RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
PDF icon RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
Ganeshpure, K.P.
PDF icon Automatic Test Pattern Generation for Maximal Circuit Noise in Multiple Aggressor Crosstalk Faults [p. 540]
Garg S.
PDF icon System-Level Process Variation Driven Throughput Analysis for Single and Multiple Voltage-Frequency Island Designs [p. 403]
Garlepp, B. W.
PDF icon A New Technique for Characterization of Digital-to-Analog Converters in High-Speed Systems [p. 433]
Gasperoni, F.
PDF icon Towards Total Open Source in Aeronautics and Space? [p. 1556]
Gayasen, A.
PDF icon Assessing Carbon Nanotube Bundle Interconnect for Future FPGA Architectures [p. 307]
Gburzynski, P.
PDF icon A Tiny and Efficient Wireless Ad-hoc Protocol for Low-cost Sensor Networks [p. 1557]
Ge, D.
PDF icon ATLAS: A Chip-Multiprocessor with Transactional Memory Support [p. 3]
Ge, Z.
PDF icon DRIM: A Low Power Dynamically Reconfigurable Instruction Memory Hierarchy for Embedded Systems [p. 1343]
Geilen, M.
PDF icon A Calculator for Pareto Points [p. 285]
Gerlach, J.
PDF icon Introducing New Verification Methods into a Company's Design Flow: An Industrial User's Point of View [p. 689]
Ghiasi, S.
PDF icon Efficient and Scalable Compiler-Directed Energy Optimization for Realtime Applications [p. 785]
Ghosh, S.
PDF icon An Area Optimized Reconfigurable Encryptor for AES-Rijndael [p. 1116]
PDF icon Low-Overhead Circuit Synthesis for Temperature Adaptation Using Dynamic Voltage Scheduling [p. 1532]
Giambastiani, A.
PDF icon Low-g Accelerometer Fast Prototyping for Automotive Applications [p. 486]
Gielen, G.
PDF icon An Efficient Methodology for Hierarchical Synthesis of Mixed-Signal Systems with Fully Integrated Building Block Topology Selection [p. 81]
Gill, B.S.
PDF icon A New Asymmetric SRAM Cell to Reduce Soft Errors and Leakage Power in FPGA [p. 1460]
Ginosar, R.
PDF icon Routing Table Minimization for Irregular Mesh NoCs [p. 942]
Girard, P.
PDF icon Slow Write Driver Faults in 65nm SRAM Technology: Analysis and March Test Solution [p. 528]
Girodias, B.
PDF icon (408) System Level Assessment of an Optical NoC in an MPSoC Platform [p. 1084]
Giusto, P.
PDF icon (694) Synthesis of Task and Message Activation Models in Real-Time Distributed Automotive Systems [p. 93]
PDF icon Towards a Methodology for the Quantitative Evaluation of Automotive Architectures [p. 504]
Glass, M.
PDF icon Reliability-Aware System Synthesis [p. 409]
Glesner, M.
PDF icon Executable System-Level Specification Models Containing UML-Based Behavioral Patterns [p. 301]
Glökler, T.
PDF icon Formal Verification of a Pervasive Interconnect Bus System in a High-Performance Microprocessor [p. 219]
Godard, B.
PDF icon Evaluation of Design for Reliability Techniques in Embedded Flash Memories [p. 1593]
Golubeva O.
PDF icon Architectural Leakage-Aware Management of Partitioned Scratchpad Memories [p. 1665]
Gomez-Prado, D.
PDF icon Data-Flow Transformations Using Taylor Expansion Diagrams [p. 455]
Gong, F.
PDF icon System Level Power Optimization of Sigma-Delta Modulator [p. 297]
González, J. L.
PDF icon Behavioral Modeling of Delay-Locked Loops and Its Application to Jitter Optimization in Ultra Wide-Band Impulse Radio Systems [p. 1430]
Goossens, J.
PDF icon Feasibility Intervals for Multiprocessor Fixed-Priority Scheduling of Arbitrary Deadline Periodic Systems [p. 1635]
Goossens, K.
PDF icon Congestion-Controlled Best-Effort Communication for Networks-on-Chip [p. 948]
PDF icon Undisrupted Quality-of-Service during Reconfiguration of Multiple Applications in Networks on Chip [p. 954]
Gordon-Ross, A.
PDF icon A One-Shot Configurable-Cache Tuner for Improved Energy and Performance [p. 755]
Goshima, M.
PDF icon Utilization of SECDED for Soft Error and Variation-Induced Defect Tolerance in Caches [p. 1134]
Goudarzi, M.
PDF icon Generating and Executing Multi-Exit Custom Instructions for an Adaptive Extensible Processor [p. 325]
Goutis, C.E.
PDF icon A Decoupled Architecture of Processors with Scratch-Pad Memory Hierarchy [p. 612]
Gradinaru, S.
PDF icon Use of Statistical Timing Analysis on Real Designs [p. 1605]
Graeb, H.
PDF icon Trade-Off Design of Analog Circuits Using Goal Attainment and "Wave Front" Sequential Quadratic Programming [p. 75]
Grassmann, C.
PDF icon Mapping the Physical Layer of Radio Standards to Multiprocessor Architectures [p. 1412]
Graziano, M.
PDF icon An Effective AMS Top-Down Methodology Applied to the Design of a Mixed-Signal UWB System-on-Chip [p. 1424]
Greenstreet, M.
PDF icon Computing Synchronizer Failure Probabilities [p. 1361]
Greiner, A.
PDF icon (142) Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations of a Network on Chip Architecture [p. 1090]
Gries, M.
PDF icon (374) Hard- and Software Modularity of the NOVA MPSoC Platform [p. 1102]
Grodstein, J.
PDF icon Accurate Timing Analysis Using SAT and Pattern-Dependent Delay Models [p. 1018]
Gronthoud, G.
PDF icon Re-Configuration of Sub-blocks for Effective Application of Time Domain Tests [p. 707]
GroΒe, D.
PDF icon Estimating Functional Coverage in Bounded Model Checking [p. 1176]
Grosspietsch, J.
PDF icon An FPGA Based All-Digital Transmitter with Radio Frequency Output for Software Defined Radio [p. 21]
GroΒschädl, J.
PDF icon Energy Evaluation of Software Implementations of Block Ciphers under Memory Constraints [p. 1110]
Gu, Z.
PDF icon An Efficient Algorithm for Online Management of 2D Area of Partially Reconfigurable FPGAs [p. 129]
Guardiani, C.
PDF icon DFM/DFY: Should You Trust the Surgeon or the Family Doctor? [p. 439]
PDF icon Yield-aware Placement Optimization [p. 1232]
Guerra e Silva, L.
PDF icon Efficient Computation of the Worst-Delay Corner [p. 1617]
Guerrieri, R.
PDF icon Implementation of AES/Rijndael on a Dynamically Reconfigurable Architecture [p. 355]
Guillot, J.
PDF icon Data-Flow Transformations Using Taylor Expansion Diagrams [p. 455]
Guindi, R. S.
PDF icon (521) Speeding Up SystemC Simulation through Process Splitting [p. 111]
Gupta, M.S.
PDF icon Understanding Voltage Variations in Chip Multiprocessors Using a Distributed Power-Delivery Network [p. 624]
Gupta, R.
PDF icon CATS: Cycle Accurate Transaction-driven Simulation with Multiple Processor Simulators [p. 749]

H

Ha, S.
PDF icon CATS: Cycle Accurate Transaction-driven Simulation with Multiple Processor Simulators [p. 749]
PDF icon A Novel Technique to Use Scratch-pad Memory for Stack Management [p. 1478]
Hairion, D.
PDF icon New Safety Critical Radio Altimeter for Airbus and Related Design Flow [p. 684]
Hämäläinen, T.D.
PDF icon Cost-Aware Capacity Optimization in Dynamic Multi-Hop WSNs [p. 666]
PDF icon Compact Hardware Design of Whirlpool Hashing Core [p. 1247]
Hämäläinen, P.
PDF icon Compact Hardware Design of Whirlpool Hashing Core [p. 1247]
Hamers, J.
PDF icon Resource Prediction for Media Stream Decoding [p. 594]
Hampton, M.
PDF icon Heterogeneous Systems on Chip and Systems in Package [p. 737]
Hamzaoglu, I.
PDF icon An Efficient Hardware Architecture for H.264 Intra Prediction Algorithm [p. 183]
Hännikäinen, M.
PDF icon Cost-Aware Capacity Optimization in Dynamic Multi-Hop WSNs [p. 666]
PDF icon Compact Hardware Design of Whirlpool Hashing Core [p. 1247]
Hansson, A.
PDF icon (394) An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems on Chip [p. 117]
PDF icon Undisrupted Quality-of-Service during Reconfiguration of Multiple Applications in Networks on Chip [p. 954]
Harris, I.G.
PDF icon Automatic Generation of Functional Coverage Models from Behavioral Verilog Descriptions [p. 900]
Hartung, J.
PDF icon Heterogeneous Systems on Chip and Systems in Package [p. 737]
Hashempour, H.
PDF icon Circuit-Level Modeling and Detection of Metallic Carbon Nanotube Defects in Carbon Nanotube FETs [p. 841]
Haubelt, C.
PDF icon Reliability-Aware System Synthesis [p. 409]
Haykel Ben Jamaa, M.
PDF icon Improving the Fault Tolerance of Nanometric PLA Designs [p. 570]
He, K.
PDF icon Temperature-aware NBTI Modeling and the Impact of Input Vector Control on Performance Degradation [p. 546]
He, L.
PDF icon Statistical Dual-Vdd Assignment for FPGA Interconnect Power Reduction [p. 636]
He, X.
PDF icon An Efficient Algorithm for Online Management of 2D Area of Partially Reconfigurable FPGAs [p. 129]
Heinen, S.
PDF icon From Algorithm to First 3.5G Call in Record Time . A Novel System Design Approach Based on Virtual Prototyping and Its Consequences for Interdisciplinary System Design Teams [p. 828]
Heiries, V.
PDF icon Development of on Board, Highly Flexible, Galileo Signal Generator ASIC [p. 679]
Hekstra, A.
PDF icon Non-Fractional Parallelism in LDPC Decoder Implementations [p. 337]
Henkel, J.
PDF icon Instruction Trace Compression for Rapid Instruction Cache Simulation [p. 803]
PDF icon Efficient Code Density through Look-up Table Compression [p. 809]
Hergenhan, A.
PDF icon Timing Simulation of Interconnected AUTOSAR Software-Components [p. 474]
Hermida, R.
PDF icon Area Optimization of Multi-Cycle Operators in High-Level Synthesis [p. 449]
Hessel, S.
PDF icon Low Power Design on Algorithmic and Architectural Level: A Case Study of an HSDPA Baseband Digital Signal Processing System [p. 1406]
Hofmann, M.
PDF icon Energy Evaluation of Software Implementations of Block Ciphers under Memory Constraints [p. 1110]
Honbo, D.
PDF icon An FPGA Implementation of Decision Tree Classification [p. 189]
Hong, D.
PDF icon A Two-Tone Test Method for Continuous-Time Adaptive Equalizers [p. 1283]
Hong, X.
PDF icon Statistical Model Order Reduction for Interconnect Circuits Considering Spatial Correlations [p. 1508]
Horowitz, M. A.
PDF icon A New Technique for Characterization of Digital-to-Analog Converters in High-Speed Systems [p. 433]
Hosseinabady, M.
PDF icon Using the Inter- and Intra-Switch Regularity in NoC Switch Testing [p. 361]
Hsiao, M.S.
PDF icon A New Hybrid Solution to Boost SAT Solver Performance [p. 1307]
Hsieh, T.-Y.
PDF icon Reduction of Detected Acceptable Faults for Yield Improvement via Error-Tolerance [p. 1599]
Hu, Q.
PDF icon Fast Memory Footprint Estimation Based on Maximal Dependency Vector Calculation [p. 379]
Hu, X.
PDF icon pFFT in FastMaxwell: A Fast Impedance Extraction Solver for 3D Conductor Structures over Substrate [p. 1194]
PDF icon Optimization-based Wideband Basis Functions for Efficient Interconnect Extraction [p. 1200]
Huang, C.-Y.
PDF icon QuteSAT: A Robust Circuit-based SAT Solver for Complex Circuit Structure [p. 1313]
Huang, K.
PDF icon Performance Analysis of Multimedia Applications Using Correlated Streams [p. 912]
Huang, P.-K.
PDF icon Efficient and Scalable Compiler-Directed Energy Optimization for Realtime Applications [p. 785]
Huang, S.
PDF icon Modeling and Simulation to the Design of ZΔ Fractional-N Frequency Synthesizer [p. 291]
Huang, Y.
PDF icon Dynamic Learning Based Scan Chain Diagnosis [p. 510]
Huisken, J.
PDF icon (394) An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems on Chip [p. 117]
Hull, M.
PDF icon Impact of Description Language, Abstraction Layer, and Value Representation on Simulation Performance [p. 767]
Hull, M.
PDF icon Implementation of a Transaction Level Assertion Framework in SystemC [p. 894]
Humenay, E.B.
PDF icon Impact of Process Variations on Multicore Performance Symmetry [p. 1653]
Hung, L.D.
PDF icon Utilization of SECDED for Soft Error and Variation-Induced Defect Tolerance in Caches [p. 1134]
Huomo, H.
PDF icon Emerging Solutions Technology and Business Views for the Ubiquitous Communication [p. 678]
Huynh, H.P.
PDF icon Instruction-Set Customization for Real-Time Embedded Systems [p. 1472]
Hwang, M.-E.
PDF icon Processor Tolerant Beta-Ratio Modulation for Ultra-Dynamic Voltage Scaling [p. 1550]

I

Idgunji, S.
PDF icon Worst-Case Design and Margin for Embedded SRAM [p. 1289]
Ienee, P.
PDF icon Automatic Synthesis of Compressor Trees: Reevaluating Large Counters [p. 443]
Ignjatovic, A.
PDF icon Instruction Trace Compression for Rapid Instruction Cache Simulation [p. 803]
Ikeda, M.
PDF icon Behavioral Modeling of Delay-Locked Loops and Its Application to Jitter Optimization in Ultra Wide-Band Impulse Radio Systems [p. 1430]
Imai, M.
PDF icon Task Scheduling under Performance Constraints for Reducing the Energy Consumption of GALS Multi-Processor SoC [p. 797]
Imanishi, M.
PDF icon An SoC Test Scheduling Algorithm Using Reconfigurable Union Wrappers [p. 231]
Indrusiak, L.S.
PDF icon Executable System-Level Specification Models Containing UML-Based Behavioral Patterns [p. 301]
Inoue, K.
PDF icon Generating and Executing Multi-Exit Custom Instructions for an Adaptive Extensible Processor [p. 325]
Iozzi, F.
PDF icon Low-g Accelerometer Fast Prototyping for Automotive Applications [p. 486]
Irie, H.
PDF icon Utilization of SECDED for Soft Error and Variation-Induced Defect Tolerance in Caches [p. 1134]
Ishihara, T.
PDF icon Task Scheduling for Reliable Cache Architectures of Multiprocessor Systems [p. 1490]

J

Janapsatya, A.
PDF icon Instruction Trace Compression for Rapid Instruction Cache Simulation [p. 803]
Jang, B.
PDF icon Error Rate Reduction in DNA Self-Assembly by Non-Constant Monomer Concentrations and Profiling [p. 847]
Jayakumar, N.
PDF icon An Algorithm to Minimize Leakage through Simultaneous Input Vector Control and Circuit Modification [p. 618]
Jayapala, M.
PDF icon Very Wide Register: An Asymmetric Register File Organization for Low Power Embedded Processors [p. 1066]
Jerraya, A.A.
PDF icon HW/SW Implementation from Abstract Architecture Models [p. 1470]
Jezequel, M.
PDF icon Butterfly and Benes-Based On-Chip Communication Networks for Multiprocessor Turbo Decoding [p. 654]
Jha, N.K.
PDF icon Energy and Execution Time Analysis of a Software-based Trusted Platform Module [p. 1128]
Jobstmann, B.
PDF icon Automatic Hardware Synthesis from Specifications: A Case Study [p. 1188]
Johannes, F.M.
PDF icon Fast and Accurate Routing Demand Estimation for Efficient Routability-driven Placement [p. 1226]
Joseph, R.
PDF icon Understanding Voltage Variations in Chip Multiprocessors Using a Distributed Power-Delivery Network [p. 624]
Jouppi, N.P.
PDF icon Microprocessors in the Era of Terascale Integration [p. 237]
Ju, H.
PDF icon A Novel Criticality Computation Method in Statistical Timing Analysis [p. 1611]
Ju, L.
PDF icon Accounting for Cache-Related Preemption Delay in Dynamic Priority Schedulability Analysis [p. 1623]
Jung, H.
PDF icon Dynamic Power Management under Uncertain Information [p. 1060]

K

Kahng, A.B.
PDF icon Design Challenges at 65nm and Beyond [p. 1466]
Kakarountas, A. P.
PDF icon Efficient High-Performance ASIC Implementation of JPEG-LS Encoder [p. 159]
Kakarountas, A.P.
PDF icon A Decoupled Architecture of Processors with Scratch-Pad Memory Hierarchy [p. 612]
Kamakoti, V.
PDF icon On Power-profiling and Pattern Generation for Power-safe Scan Tests [p. 534]
Kamhi, G.
PDF icon PowerQuest: Trace Driven Data Mining for Power Optimization [p. 1078]
Kaminska, B.
PDF icon A Tiny and Efficient Wireless Ad-hoc Protocol for Low-cost Sensor Networks [p. 1557]
Kammler, D.
PDF icon Design Space Exploration of Partially Re-Configurable Embedded Processors [p. 319]
Kanajan, S.
PDF icon Towards a Methodology for the Quantitative Evaluation of Automotive Architectures [p. 504]
PDF icon Automatic Model Generation for Black Box Real-Time Systems [p. 930]
Kandemir, M.
PDF icon Performance Aware Secure Code Partitioning [p. 1122]
PDF icon Memory Bank Aware Dynamic Loop Scheduling [p. 1671]
Kanstein, A.
PDF icon Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture: The H.264/AVC Deblocking Filter [p. 177]
Kao, J.-C.
PDF icon Distributed Power-Management Techniques for Wireless Network Video Systems [p. 564]
Kapur, R.
PDF icon Testing in the Year 2020 [p. 960]
Karakonstantis, G.
PDF icon Process Variation Tolerant Low Power DCT Architecture [p. 630]
Karri, R.
PDF icon Logic Level Fault Tolerance Approaches Targeting Nanoelectronics PLAs [p. 865]
Karuri, K.
PDF icon Design Space Exploration of Partially Re-Configurable Embedded Processors [p. 319]
Keezer, D.C.
PDF icon Method for Reducing Jitter in Multi-Gigahertz ATE [p. 701]
Keutzer, K.
PDF icon A Decomposition-based Constraint Optimization Approach for Statically Scheduling Task Graphs with Communication Delays to Multiprocessors [p. 57]
Khan, Z.
PDF icon Pipelined Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Architecture [p. 349]
PDF icon A New Pipelined Implementation for Minimum Norm Sorting Used in Square Root Algorithm for MIMO-VBLAST Systems [p. 1569]
Khatri, S.P.
PDF icon An Algorithm to Minimize Leakage through Simultaneous Input Vector Control and Circuit Modification [p. 618]
Khazaka, R.
PDF icon Efficient Nonlinear Distortion Analysis of RF Circuits [p. 255]
Khazamiphur, A.
PDF icon Reversible Circuit Technology Mapping from Non-reversible Specifications [p. 558]
Kienhuis, B.
PDF icon A Process Splitting Transformation for Kahn Process Networks [p. 1355]
Kienle, F.
PDF icon Low Complexity LDPC Code Decoders for Next Generation Standards [p. 331]
Kim, D.
PDF icon CATS: Cycle Accurate Transaction-driven Simulation with Multiple Processor Simulators [p. 749]
Kim, Y.-B.
PDF icon Error Rate Reduction in DNA Self-Assembly by Non-Constant Monomer Concentrations and Profiling [p. 847]
Kimmich, G.
PDF icon Portable Multimedia SoC Design: A Global Challenge [p. 831]
King, K.-J.
PDF icon Energy-Efficient Real-Time Task Scheduling with Task Rejection [p. 1629]
Kinzelbach, H.
PDF icon CMCal: An Accurate Analytical Approach for the Analysis of Process Variations with Non-Gaussian Parameters and Nonlinear Functions [p. 243]
Kirolos, S.
PDF icon Thermally Robust Clocking Schemes for 3D Integrated Circuits [p. 1206]
Kishinevsky, M.
PDF icon Layout-Aware Gate Duplication and Buffer Insertion [p. 1367]
Kivilcim Coskun, A.
PDF icon Temperature Aware Task Scheduling in MPSoCs [p. 1659]
Kjeldsberg, P.G.
PDF icon Fast Memory Footprint Estimation Based on Maximal Dependency Vector Calculation [p. 379]
Knijnenburg, P.M.W.
PDF icon Feasibility of Combined Area and Performance Optimization for Superscalar Processors Using Random Search [p. 606]
Kodakara, S.V.
PDF icon Design Fault Directed Test Generation for Microprocessor Validation [p. 761]
Kohvakka, M.
PDF icon Cost-Aware Capacity Optimization in Dynamic Multi-Hop WSNs [p. 666]
Kokkeler, A. B. J.
PDF icon Cyclostationary Feature Detection on a Tiled-SoC [p. 171]
Kolodny, A.
PDF icon Routing Table Minimization for Irregular Mesh NoCs [p. 942]
Kondo, M.
PDF icon Task Scheduling under Performance Constraints for Reducing the Energy Consumption of GALS Multi-Processor SoC [p. 797]
Kopetz, H.
PDF icon The ARTEMIS Cross-Domain Architecture for Embedded Systems [p. 1468]
Koufopavlou, O.
PDF icon Optimization of the "FOCUS" Inband-FEC Architecture for 10-Gbps SDH/SONET Optical Communication Channels [p. 1575]
Kozyrakis, C.
PDF icon ATLAS: A Chip-Multiprocessor with Transactional Memory Support [p. 3]
PDF icon Register Pointer Architecture for Efficient Embedded Processors [p. 600]
Kraemer, S.
PDF icon SoftSIMD . Exploiting Subword Parallelism Using Source Code Transformations [p. 1349]
Kraus, W.
PDF icon Statistical Simulation of High-Frequency Bipolar Circuits [p. 1397]
Krause, M.
PDF icon Timing Simulation of Interconnected AUTOSAR Software-Components [p. 474]
Krishnaiah, G.
PDF icon Scalable Reconfigurable Channel Decoder Architecture for Future Wireless Handsets [p. 1563]
Krishnan, S.
PDF icon Re-Configuration of Sub-blocks for Effective Application of Time Domain Tests [p. 707]
Kroening, D.
PDF icon Image Computation and Predicate Refinement for RTL Verilog Using Word Level Proofs [p. 1325]
Krol, T.
PDF icon Cyclostationary Feature Detection on a Tiled-SoC [p. 171]
Kühne, U.
PDF icon Estimating Functional Coverage in Bounded Model Checking [p. 1176]
Kumar, A.
PDF icon (394) An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems on Chip [p. 117]
Kundu, S.
PDF icon Automatic Test Pattern Generation for Maximal Circuit Noise in Multiple Aggressor Crosstalk Faults [p. 540]
Kunkel, J.
PDF icon Life Begins at 65 - Unless You Are Mixed Signal? [p. 936]
Kuo, T.-W.
PDF icon Energy-Efficient Real-Time Task Scheduling with Task Rejection [p. 1629]
Kuorilehto, M.
PDF icon Cost-Aware Capacity Optimization in Dynamic Multi-Hop WSNs [p. 666]
Kuper, J.
PDF icon Cyclostationary Feature Detection on a Tiled-SoC [p. 171]
Kurra, S.
PDF icon The Impact of Loop Unrolling on Controller Delay in High Level Synthesis [p. 391]

L

La Barba, V.
PDF icon RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
Ladier, G.
PDF icon Towards Total Open Source in Aeronautics and Space? [p. 1556]
Lajolo, M.
PDF icon Hardware Scheduling Support in SMP Architectures [p. 642]
Lambrechts, A.
PDF icon Very Wide Register: An Asymmetric Register File Organization for Low Power Embedded Processors [p. 1066]
Landrault, C.
PDF icon Slow Write Driver Faults in 65nm SRAM Technology: Analysis and March Test Solution [p. 528]
Langendörfer, P.
PDF icon An Efficient Polynomial Multiplier in GF(2m) and Its Application to ECC Designs [p. 1253]
Langmann, U.
PDF icon Low Power Design on Algorithmic and Architectural Level: A Case Study of an HSDPA Baseband Digital Signal Processing System [p. 1406]
Laouamri, O.
PDF icon Remote Testing and Diagnosis of System-on-Chips Using Network Management Frameworks [p. 373]
Larsson, A.
PDF icon Optimized Integration of Test Compression and Sharing for SoC Testing [p. 207]
Larsson, E.
PDF icon Optimized Integration of Test Compression and Sharing for SoC Testing [p. 207]
PDF icon Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO [p. 859]
Lasbouygues, B.
PDF icon Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops [p. 1012]
Lataire, J.
PDF icon Optimizing Analog Filter Designs for Minimum Nonlinear Distortions Using Multisine Excitations [p. 267]
Le, T.
PDF icon Formal Verification of a Pervasive Interconnect Bus System in a High-Performance Microprocessor [p. 219]
Lee, C.-C.
PDF icon QuteSAT: A Robust Circuit-based SAT Solver for Complex Circuit Structure [p. 1313]
Lee, K.-J.
PDF icon Reduction of Detected Acceptable Faults for Yield Improvement via Error-Tolerance [p. 1599]
Legat, J.-D.
PDF icon Enabling Certification for Dynamic Partial Reconfiguration Using a Minimal Flow [p. 983]
Legat, J.-D.
PDF icon RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
Lehnigk-Emden, T.
PDF icon Low Complexity LDPC Code Decoders for Next Generation Standards [p. 331]
Lenge, E.
PDF icon Accurate Timing Analysis Using SAT and Pattern-Dependent Delay Models [p. 1018]
Leupers, R.
PDF icon Design Space Exploration of Partially Re-Configurable Embedded Processors [p. 319]
PDF icon SoftSIMD . Exploiting Subword Parallelism Using Source Code Transformations [p. 1349]
Leveugle, R.
PDF icon Experimental Evaluation of Protections against Laser-induced Faults and Consequences on Fault Modeling [p. 1587]
Lewis, D.
PDF icon Identification of Process/Design Issues during 0.18 μm Technology Qualification for Space Application [p. 989]
Li, W.
PDF icon Verification-Guided Soft Error Resilience [p. 1442]
Liao, Y.-H.
PDF icon Improve CAM Power Efficiency Using Decoupled Match Line Scheme [p. 165]
Liberati, R.
PDF icon RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
Liberati, R.
PDF icon RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
Liégeon, E.
PDF icon Development of on Board, Highly Flexible, Galileo Signal Generator ASIC [p. 679]
Lilja, D.
PDF icon Design Fault Directed Test Generation for Microprocessor Validation [p. 761]
Lim, H.-B.
PDF icon DRIM: A Low Power Dynamically Reconfigurable Instruction Memory Hierarchy for Embedded Systems [p. 1343]
Lin, C.
PDF icon Design Closure Driven Delay Relaxation Based on Convex Cost Network Flow [p. 63]
Lin, K.J.
PDF icon Overcoming Glitches and Dissipation Timing Skews in Design of DPA-Resistant Cryptographic Hardware [p. 1265]
Lin, M.
PDF icon Testable Design for Advanced Serial-Link Transceivers [p. 695]
Lin, R.-B.
PDF icon Double-Via-Driven Standard Cell Library Design [p. 1212]
Lin, T.
PDF icon Use of Statistical Timing Analysis on Real Designs [p. 1605]
Lin, T.-H.
PDF icon Double-Via-Driven Standard Cell Library Design [p. 1212]
PDF icon QuteSAT: A Robust Circuit-based SAT Solver for Complex Circuit Structure [p. 1313]
Lin, T.-Y.
PDF icon Double-Via-Driven Standard Cell Library Design [p. 1212]
Lin, Y.
PDF icon Statistical Dual-Vdd Assignment for FPGA Interconnect Power Reduction [p. 636]
Link, G.
PDF icon Thermally Robust Clocking Schemes for 3D Integrated Circuits [p. 1206]
L'Insalata, N.E.
PDF icon Low Complexity LDPC Code Decoders for Next Generation Standards [p. 331]
Lisboa, C.A.
PDF icon A Low-SER Efficient Core Processor Architecture for Future Technologies [p. 1448]
Lissel, R.
PDF icon Introducing New Verification Methods into a Company's Design Flow: An Industrial User's Point of View [p. 689]
Liu, F.
PDF icon Fast Statistical Circuit Analysis with Finite-Point Based Transistor Model [p. 1391]
Liu, Y.
PDF icon Accurate Temperature-Dependent Integrated Circuit Leakage Power Estimation Is Easy [p. 1526]
Lo, C.C.
PDF icon Overcoming Glitches and Dissipation Timing Skews in Design of DPA-Resistant Cryptographic Hardware [p. 1265]
Lodi, A.
PDF icon A Dynamically Adaptive DSP for Heterogeneous Reconfigurable Platforms[p. 9]
Lodi, A.
PDF icon Implementation of AES/Rijndael on a Dynamically Reconfigurable Architecture [p. 355]
Loghi, M.
PDF icon Architectural Leakage-Aware Management of Partitioned Scratchpad Memories [p. 1665]
Lombardi, F.
PDF icon Circuit-Level Modeling and Detection of Metallic Carbon Nanotube Defects in Carbon Nanotube FETs [p. 841]
PDF icon Error Rate Reduction in DNA Self-Assembly by Non-Constant Monomer Concentrations and Profiling [p. 847]
Lombardo, P.
PDF icon Dynamic Reconfiguration in Sensor Networks with Regenerative Energy Sources [p. 1054]
Lonardi, S.
PDF icon Two-Level Microprocessor-Accelerator Partitioning [p. 313]
PDF icon Clock-Frequency Assignment for Multiple Clock Domain Systems-on-a-Chip [p. 397]
PDF icon Soft-core Processor Customization Using the Design of Experiments Paradigm [p. 821]
López, J.C.
PDF icon Lightweight Middleware for Seamless HW-SW Interoperability, with Application to Wireless Sensor Networks [p. 1042]
López, J. F.
PDF icon Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture: The H.264/AVC Deblocking Filter [p. 177]
López, S.
PDF icon Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture: The H.264/AVC Deblocking Filter [p. 177]
Lotfi, R.
PDF icon Design of High-Resolution MOSFET-Only Pipelined ADCs with Digital Calibration [p. 427]
Lucian, I.I.
PDF icon Mapping Multi-Dimensional Signals into Hierarchical Memory Organizations [p. 385]
Luk, W.
PDF icon Optimizing Instruction-set Extensible Processors under Data Bandwidth Constraints [p. 588]
Lukasiewycz, M.
PDF icon Reliability-Aware System Synthesis [p. 409]
Luo, H.
PDF icon Temperature-aware NBTI Modeling and the Impact of Input Vector Control on Performance Degradation [p. 546]
Luo, R.
PDF icon Temperature-aware NBTI Modeling and the Impact of Input Vector Control on Performance Degradation [p. 546]
Lysecky, R.
PDF icon Low-Power Warp Processor for Power Efficient High-Performance Embedded Systems [p. 141]

M

Ma, H.
PDF icon Modeling and Simulation to the Design of ZΔ Fractional-N Frequency Synthesizer [p. 291]
Macii, A.
PDF icon Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing [p. 1544]
Macii, E.
PDF icon Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing [p. 1544]
Macii, E.
PDF icon Architectural Leakage-Aware Management of Partitioned Scratchpad Memories [p. 1665]
Magarshack, P.
PDF icon DFM/DFY: Should You Trust the Surgeon or the Family Doctor? [p. 439]
Maingot, V.
PDF icon Experimental Evaluation of Protections against Laser-induced Faults and Consequences on Fault Modeling [p. 1587]
Mamagkakis, S.
PDF icon Middleware Design Optimization of Wireless Protocols Based on the Exploitation of Dynamic Input Patterns [p. 1036]
Manet, P.
PDF icon Enabling Certification for Dynamic Partial Reconfiguration Using a Minimal Flow [p. 983]
PDF icon RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
Mangassarian, H.
PDF icon Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability [p. 1538]
Marculescu, D.
PDF icon An 0.9 X 1.2", Low Power, Energy-Harvesting System with Custom Multi-Channel Communication Interface [p. 15]
PDF icon System-Level Process Variation Driven Throughput Analysis for Single and Multiple Voltage-Frequency Island Designs [p. 403]
PDF icon Soft Error Rate Analysis for Sequential Circuits [p. 1436]
Marculescu, R.
PDF icon Distributed Power-Management Techniques for Wireless Network Video Systems [p. 564]
PDF icon (768) Analytical Router Modeling for Networks-on-Chip Performance Analysis [p. 1096]
Mariani, R.
PDF icon Using an Innovative SOC-level FMEA Methodology to Design in Compliance with IEC61508 [p. 492]
Marinissen, E.J.
PDF icon Design and DFT of a High-Speed Area-Efficient Embedded Asynchronous FIFO [p. 853]
PDF icon Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO [p. 859]
Marino, C.
PDF icon Low-g Accelerometer Fast Prototyping for Automotive Applications [p. 486]
Marzocca, C.
PDF icon Experimental Validation of a Tuning Algorithm for High-Speed Filters [p. 421]
Massoud, Y.
PDF icon Assessing Carbon Nanotube Bundle Interconnect for Future FPGA Architectures [p. 307]
PDF icon Thermally Robust Clocking Schemes for 3D Integrated Circuits [p. 1206]
Matarrese, G.
PDF icon Experimental Validation of a Tuning Algorithm for High-Speed Filters [p. 421]
Mateo, D.
PDF icon Behavioral Modeling of Delay-Locked Loops and Its Application to Jitter Optimization in Ultra Wide-Band Impulse Radio Systems [p. 1430]
Mathaikutty, D.A.
PDF icon Design Fault Directed Test Generation for Microprocessor Validation [p. 761]
Maufroid, D.
PDF icon RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
Maurine, P.
PDF icon Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops [p. 1012]
Mavroidis, I.
PDF icon Efficient Testbench Code Synthesis for a Hardware Emulator System [p. 888]
Medardoni, S.
PDF icon Capturing the Interaction of the Communication, Memory and I/O Subsystems in Memory-Centric Industrial MPSoC Platforms [p. 660]
Medwed, M.
PDF icon Energy Evaluation of Software Implementations of Block Ciphers under Memory Constraints [p. 1110]
Mehdipour, F.
PDF icon Generating and Executing Multi-Exit Custom Instructions for an Adaptive Extensible Processor [p. 325]
Mehrara, M.
PDF icon Low-cost Protection for SER Upsets and Silicon Defects [p. 1146]
Meijer, S.
PDF icon A Process Splitting Transformation for Kahn Process Networks [p. 1355]
Melani, M.
PDF icon Low-g Accelerometer Fast Prototyping for Automotive Applications [p. 486]
Memik, G.
PDF icon An FPGA Based All-Digital Transmitter with Radio Frequency Output for Software Defined Radio [p. 21]
PDF icon An FPGA Implementation of Decision Tree Classification [p. 189]
Memik, S.O.
PDF icon Self-Heating-Aware Optimal Wire Sizing under Elmore Delay Model [p. 1373]
Mencer, O.
PDF icon Optimizing Instruction-set Extensible Processors under Data Bandwidth Constraints [p. 588]
Mendias, J.M.
PDF icon Area Optimization of Multi-Cycle Operators in High-Level Synthesis [p. 449]
Merkenbraeck, D.
PDF icon Enabling Certification for Dynamic Partial Reconfiguration Using a Minimal Flow [p. 983]
Metra, C.
PDF icon Pulse Propagation for the Detection of Small Delay Defects [p. 1295]
Meyr, H.
PDF icon Design Space Exploration of Partially Re-Configurable Embedded Processors [p. 319]
PDF icon SoftSIMD . Exploiting Subword Parallelism Using Source Code Transformations [p. 1349]
Mi, N.
PDF icon Statistical Model Order Reduction for Interconnect Circuits Considering Spatial Correlations [p. 1508]
Michail, H.
PDF icon A Decoupled Architecture of Processors with Scratch-Pad Memory Hierarchy [p. 612]
Michalik, H.
PDF icon Reconfigurable System-on-Chip Data Processing Units for Space Imaging Instruments [p. 977]
Mieyeville, F.
PDF icon (408) System Level Assessment of an Optical NoC in an MPSoC Platform [p. 1084]
Mignolet, J.-Y.
PDF icon Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture: The H.264/AVC Deblocking Filter [p. 177]
Milidonis, A.
PDF icon A Decoupled Architecture of Processors with Scratch-Pad Memory Hierarchy [p. 612]
Minier, D.
PDF icon Method for Reducing Jitter in Multi-Gigahertz ATE [p. 701]
Mir, S.
PDF icon Evaluation of Test Measures for LNA Production Testing Using a Multinormal Statistical Model [p. 731]
Miremadi, S.G.
PDF icon Joint Consideration of Fault-Tolerance, Energy-Efficiency and Performance in On-Chip Networks [p. 1647]
Miro Panades, I.
PDF icon (142) Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations of a Network on Chip Architecture [p. 1090]
Mishra, P.
PDF icon An Efficient Code Compression Technique Using Application-Aware Bitmask and Dictionary Selection Methods [p. 582]
Miskov-Zivanov, N.
PDF icon Soft Error Rate Analysis for Sequential Circuits [p. 1436]
Mitra, S.
PDF icon Verification-Guided Soft Error Resilience [p. 1442]
Mitra, T.
PDF icon Instruction-Set Customization for Real-Time Embedded Systems [p. 1472]
Mogal, H.
PDF icon Microarchitecture Floorplanning for Sub-threshold Leakage Reduction [p. 1238]
Mohanram, K.
PDF icon Single-ended Coding Techniques for Off-chip Interconnects to Commodity Memory [p. 1072]
PDF icon Accurate and Scalable Reliability Analysis of Logic Circuits [p. 1454]
Moitrel, P.
PDF icon Experimental Evaluation of Protections against Laser-induced Faults and Consequences on Fault Modeling [p. 1587]
Molina, M.C.
PDF icon Area Optimization of Multi-Cycle Operators in High-Level Synthesis [p. 449]
Mondal, M.
PDF icon Thermally Robust Clocking Schemes for 3D Integrated Circuits [p. 1206]
Moon, I.-H.
PDF icon A Compositional Approach to the Combination of Combinational and Sequential Equivalence Checking of Circuits without Known Reset States [p. 1170]
Moselhy, T.
PDF icon pFFT in FastMaxwell: A Fast Impedance Extraction Solver for 3D Conductor Structures over Substrate [p. 1194]
PDF icon Optimization-based Wideband Basis Functions for Efficient Interconnect Extraction [p. 1200]
Moser, C.
PDF icon Adaptive Power Management in Energy Harvesting Systems [p. 773]
Moss, L.
PDF icon Seamless Hardware/Software Performance Co-Monitoring in a Codesign Simulation Environment with RTOS Support [p. 876]
Mourtel, C.
PDF icon Experimental Evaluation of Protections against Laser-induced Faults and Consequences on Fault Modeling [p. 1587]
Moussa, H.
PDF icon Butterfly and Benes-Based On-Chip Communication Networks for Multiprocessor Turbo Decoding [p. 654]
Moya, F.
PDF icon Lightweight Middleware for Seamless HW-SW Interoperability, with Application to Wireless Sensor Networks [p. 1042]
Mucci, C.
PDF icon A Dynamically Adaptive DSP for Heterogeneous Reconfigurable Platforms[p. 9]
PDF icon Implementation of AES/Rijndael on a Dynamically Reconfigurable Architecture [p. 355]
Mueller, D.
PDF icon Trade-Off Design of Analog Circuits Using Goal Attainment and "Wave Front" Sequential Quadratic Programming [p. 75]
Mueller, R.
PDF icon Towards Total Open Source in Aeronautics and Space? [p. 1556]
Mukhopadhayay, D.
PDF icon An Area Optimized Reconfigurable Encryptor for AES-Rijndael [p. 1116]
Mukund, P.R.
PDF icon Sensitivity Analysis for Fault-analysis and Tolerance in RF Front-end Circuitry [p. 1277]
Mulertt, O.
PDF icon RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
Müller, F.
PDF icon Using Partial-Run-Time Reconfigurable Hardware to Accelerate Video Processing in Driver Assistance Systems [p. 498]
Muller, O.
PDF icon Butterfly and Benes-Based On-Chip Communication Networks for Multiprocessor Turbo Decoding [p. 654]
Mundy, J.
PDF icon Techniques for Designing Noise-Tolerant Multi-Level Combinational Circuits [p. 576]
Münker, C.
PDF icon Life Begins at 65 - Unless You Are Mixed Signal? [p. 936]
Murakami, K.
PDF icon Generating and Executing Multi-Exit Custom Instructions for an Adaptive Extensible Processor [p. 325]
PDF icon Task Scheduling for Reliable Cache Architectures of Multiprocessor Systems [p. 1490]
Mutyam, M.
PDF icon Working with Process Variation Aware Caches [p. 1152]

N

Nácul, A.C.
PDF icon Hardware Scheduling Support in SMP Architectures [p. 642]
Naguib, Y. N.
PDF icon (521) Speeding Up SystemC Simulation through Process Splitting [p. 111]
Nahapetian, A.
PDF icon Dynamic Reconfiguration in Sensor Networks with Regenerative Energy Sources [p. 1054]
Naidu, S.
PDF icon Use of Statistical Timing Analysis on Real Designs [p. 1605]
Najjar, W.
PDF icon A One-Shot Configurable-Cache Tuner for Improved Energy and Performance [p. 755]
Najm, F.N.
PDF icon Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability [p. 1538]
Nakamura, H.
PDF icon Task Scheduling under Performance Constraints for Reducing the Energy Consumption of GALS Multi-Processor SoC [p. 797]
Nandra, N.
PDF icon Life Begins at 65 - Unless You Are Mixed Signal? [p. 936]
Nanya, T.
PDF icon Task Scheduling under Performance Constraints for Reducing the Energy Consumption of GALS Multi-Processor SoC [p. 797]
Narayanan, R.
PDF icon An FPGA Implementation of Decision Tree Classification [p. 189]
Narayanan, S.H.K.
PDF icon Performance Aware Secure Code Partitioning [p. 1122]
Narayanan, V.
PDF icon Working with Process Variation Aware Caches [p. 1152]
Narayanasamy, S.
PDF icon Transient Fault Prediction Based on Anomalies in Processor Events [p. 1140]
Nardi, A.
PDF icon Use of Statistical Timing Analysis on Real Designs [p. 1605]
Naumann, A.
PDF icon Was Darwin Wrong? Has Design Evolution Stopped at the RTL Level...or Will Software and Custom Processors (or System-Level Design) Extend Moore's Law? [p. 2]
Navabi, Z.
PDF icon Using the Inter- and Intra-Switch Regularity in NoC Switch Testing [p. 361]
Neema, S.
PDF icon Compositional Specification of Behavioral Semantics [p. 906]
Nepal, K.
PDF icon Techniques for Designing Noise-Tolerant Multi-Level Combinational Circuits [p. 576]
Ney, A.
PDF icon Slow Write Driver Faults in 65nm SRAM Technology: Analysis and March Test Solution [p. 528]
Ni, M.
PDF icon Self-Heating-Aware Optimal Wire Sizing under Elmore Delay Model [p. 1373]
Nicolescu, G.
PDF icon (408) System Level Assessment of an Optical NoC in an MPSoC Platform [p. 1084]
Nicolici, N.
PDF icon Low Cost Debug Architecture Using Lossy Compression for Silicon Debug [p. 225]
Nicollet, E.
PDF icon Transaction Level Modeling of SCA Compliant Software Defined Radio Waveforms and Platforms PIM/PSM [p. 966]
Nieuwoudt, A.
PDF icon Assessing Carbon Nanotube Bundle Interconnect for Future FPGA Architectures [p. 307]
Niu, L.
PDF icon Peripheral-Conscious Scheduling on Energy Minimization for Weakly Hard Real-time Systems [p. 791]
Njoroge, N.
PDF icon ATLAS: A Chip-Multiprocessor with Transactional Memory Support [p. 3]
Nocco, S.
PDF icon Boosting the Role of Inductive Invariants in Model Checking [p. 1319]
Noori, H.
PDF icon Generating and Executing Multi-Exit Custom Instructions for an Adaptive Extensible Processor [p. 325]
Nurmi, J.
PDF icon Using Dynamic Voltage Scaling to Reduce the Configuration Energy of Run Time Reconfigurable Devices [p. 147]

O

Oatley, J.L.
PDF icon Understanding Voltage Variations in Chip Multiprocessors Using a Distributed Power-Delivery Network [p. 624]
Öberg, J.
PDF icon Toward a Scalable Test Methodology for 2D-mesh Network-on-Chips [p. 367]
O'Connor, I.
PDF icon Heterogeneous Systems on Chip and Systems in Package [p. 737]
PDF icon Heterogeneous Systems on Chip and Systems in Package [p. 737]
PDF icon (408) System Level Assessment of an Optical NoC in an MPSoC Platform [p. 1084]
Ogras, U.Y.
PDF icon (768) Analytical Router Modeling for Networks-on-Chip Performance Analysis [p. 1096]
Olbrich, M.
PDF icon CMCal: An Accurate Analytical Approach for the Analysis of Process Variations with Non-Gaussian Parameters and Nonlinear Functions [p. 243]
Olesinski, W.
PDF icon A Tiny and Efficient Wireless Ad-hoc Protocol for Low-cost Sensor Networks [p. 1557]
Olive, X.
PDF icon Industrial Applications [p. 1244]
Olukotun, K.
PDF icon ATLAS: A Chip-Multiprocessor with Transactional Memory Support [p. 3]
Orailoglu, A.
O'Reilly, U.-M.
PDF icon Simulation-based Reusable Posynomial Models for MOS Transistor Parameters [p. 69]
Osterloh, B.
PDF icon Reconfigurable System-on-Chip Data Processing Units for Space Imaging Instruments [p. 977]
Ostler, C.
PDF icon (287) An ILP Formulation for System-Level Application Mapping on Network Processor Architectures [p. 99]
Oustric, C.
PDF icon Development of on Board, Highly Flexible, Galileo Signal Generator ASIC [p. 679]
Ozev, S.
PDF icon An ADC-BiST Scheme Using Sequential Code Analysis [p. 713]
Özturan, C.
PDF icon Optimizing Instruction-set Extensible Processors under Data Bandwidth Constraints [p. 588]
Ozturk, O.
PDF icon Memory Bank Aware Dynamic Loop Scheduling [p. 1671]

P

Paganini, M.
PDF icon Portable Multimedia SoC Design: A Global Challenge [p. 831]
Pais, C.
PDF icon Scratchpad Memories vs Locked Caches in Hard Real-Time Systems: A Quantitative Comparison [p. 1484]
Palkovic, M.
PDF icon Fast Memory Footprint Estimation Based on Maximal Dependency Vector Calculation [p. 379]
Pan, S.-J.
PDF icon A Framework for System Reliability Analysis Considering Both System Error Tolerance and Component Test Quality [p. 1581]
Panda, P.R.
PDF icon The Impact of Loop Unrolling on Controller Delay in High Level Synthesis [p. 391]
Pantazis, V.
PDF icon Efficient High-Performance ASIC Implementation of JPEG-LS Encoder [p. 159]
Papachristou, C.
PDF icon A New Asymmetric SRAM Cell to Reduce Soft Errors and Leakage Power in FPGA [p. 1460]
Papadonikolakis, M.
PDF icon Efficient High-Performance ASIC Implementation of JPEG-LS Encoder [p. 159]
Papaefstathiou, I.
PDF icon Efficient Testbench Code Synthesis for a Hardware Emulator System [p. 888]
Parameswaran, S.
PDF icon Automatic Application Specific Floating-point Unit Generation [p. 461]
PDF icon Instruction Trace Compression for Rapid Instruction Cache Simulation [p. 803]
Pardessus, T.
PDF icon The Methodological and Technological Dimensions of Technology Transfer for Embedded Systems in Aeronautics and Space [p. 1108]
Park, H.-W.
PDF icon A Novel Technique to Use Scratch-pad Memory for Stack Management [p. 1478]
Park, J.S.
PDF icon Register Pointer Architecture for Efficient Embedded Processors [p. 600]
Park, S.
PDF icon A Novel Technique to Use Scratch-pad Memory for Stack Management [p. 1478]
Park, S.-B.
PDF icon Register Pointer Architecture for Efficient Embedded Processors [p. 600]
Pasquet, J.-M.
PDF icon Industrial Applications [p. 1244]
Patel, H.D.
PDF icon Tackling an Abstraction Gap: Co-Simulating with SystemC DE and Bluespec ESL [p. 279]
Patterson, W.R.
PDF icon Techniques for Designing Noise-Tolerant Multi-Level Combinational Circuits [p. 576]
Pattullo, D.
PDF icon DFM/DFY: Should You Trust the Surgeon or the Family Doctor? [p. 439]
Paulin, P. G.
PDF icon A Future of Customizable Processors: Are We There Yet? [p. 1224]
Pedram, M.
PDF icon Dynamic Power Management under Uncertain Information [p. 1060]
Peng, Z.
PDF icon Bus Access Optimisation for FlexRay-based Distributed Embedded Systems [p. 51]
PDF icon Optimized Integration of Test Compression and Sharing for SoC Testing [p. 207]
Perbellini, G.
PDF icon A Middleware-centric Design Flow for Networked Embedded Systems [p. 1048]
Perdu, P.
PDF icon Identification of Process/Design Issues during 0.18 μm Technology Qualification for Space Application [p. 989]
Peter, S.
PDF icon An Efficient Polynomial Multiplier in GF(2m) and Its Application to ECC Designs [p. 1253]
Petersén, K.
PDF icon Toward a Scalable Test Methodology for 2D-mesh Network-on-Chips [p. 367]
Petri, E.
PDF icon FPGA-based Networking Systems for High Data-rate and Reliable In-vehicle Communications [p. 480]
Petrov, T.
PDF icon A Non-Intrusive Isolation Approach for Soft Cores [p. 27]
Phillips, J.
PDF icon Random Sampling of Moment Graph: A Stochastic Krylov-Reduction Algorithm [p. 1502]
Phillips, J.R.
PDF icon WAVSTAN: Waveform Based Variational Static Timing Analysis [p. 1000]
PDF icon Efficient Computation of the Worst-Delay Corner [p. 1617]
Piala, C.
PDF icon Development and Industrialization [p. 1403]
Pietrangeli, R.
PDF icon A Middleware-centric Design Flow for Networked Embedded Systems [p. 1048]
Pineda de Gyvez, J.
PDF icon BIST Method for Die-Level Process Parameter Variation Monitoring in Analog/Mixed-Signal Integrated Circuits [p. 1303]
Pinello, C.
PDF icon (694) Synthesis of Task and Message Activation Models in Real-Time Distributed Automotive Systems [p. 93]
PDF icon Towards a Methodology for the Quantitative Evaluation of Automotive Architectures [p. 504]
Pintelon, R.
PDF icon Optimizing Analog Filter Designs for Minimum Nonlinear Distortions Using Multisine Excitations [p. 267]
Piotrowski, K.
PDF icon Flexible Hardware Reduction for Elliptic Curve Cryptography in GF(2m) [p. 1259]
Pistauer, M.
PDF icon Simulation Platform for UHF RFID [p. 918]
Pister, M.
PDF icon Tool-Support for the Analysis of Hybrid Systems and Models [p. 924]
Pistritto, C.
PDF icon Capturing the Interaction of the Communication, Memory and I/O Subsystems in Memory-Centric Industrial MPSoC Platforms [p. 660]
Piterman, N.
PDF icon Automatic Hardware Synthesis from Specifications: A Case Study [p. 1188]
Pixley, C.
PDF icon A Compositional Approach to the Combination of Combinational and Sequential Equivalence Checking of Circuits without Known Reset States [p. 1170]
Pizzotti, M.
PDF icon A Dynamically Adaptive DSP for Heterogeneous Reconfigurable Platforms[p. 9]
Pnueli, A.
PDF icon Automatic Hardware Synthesis from Specifications: A Case Study [p. 1188]
Pomeranz, I.
PDF icon On Test Generation by Input Cube Avoidance [p. 522]
Poncino, M.
PDF icon Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing [p. 1544]
Poncino, M.
PDF icon Architectural Leakage-Aware Management of Partitioned Scratchpad Memories [p. 1665]
Pop, P.
PDF icon Bus Access Optimisation for FlexRay-based Distributed Embedded Systems [p. 51]
Pop, T.
PDF icon Bus Access Optimisation for FlexRay-based Distributed Embedded Systems [p. 51]
Popp, P.
PDF icon Towards a Methodology for the Quantitative Evaluation of Automotive Architectures [p. 504]
Porpodas, V.
PDF icon A Decoupled Architecture of Processors with Scratch-Pad Memory Hierarchy [p. 612]
Pozzi, L.
PDF icon A Future of Customizable Processors: Are We There Yet? [p. 1224]
PDF icon Polynomial-Time Subgraph Enumeration for Automated Instruction Set Extension [p. 1331]
Pratsch, A.
PDF icon System Level Clock Tree Synthesis for Power Optimization [p. 1677]
Pravadelli, G.
PDF icon (231) A Smooth Refinement Flow for Co-Designing HW and SW Threads [p. 105]
PDF icon Incremental ABV for Functional Validation of TL-to-RTL Design Refinement [p. 882]
Pravossoudovitch, S.
PDF icon Slow Write Driver Faults in 65nm SRAM Technology: Analysis and March Test Solution [p. 528]
Preishuber-Pfluegl, J.
PDF icon Simulation Platform for UHF RFID [p. 918]
Puaut, I.
PDF icon Scratchpad Memories vs Locked Caches in Hard Real-Time Systems: A Quantitative Comparison [p. 1484]

Q

Qiu, M.
PDF icon Energy Minimization with Soft Real-time and DVS for Uniprocessor and Multiprocessor Embedded Systems [p. 1641]
Qiu, Q.
PDF icon Stochastic Modeling and Optimization for Robust Power Management in a Partially Observable System [p. 779]
Qiu, X.-Z.
PDF icon Development of an ASIP Enabling Flows in Ethernet Access Using a Retargetable Compilation Flow [p. 1418]
Qu, Y.
PDF icon Using Dynamic Voltage Scaling to Reduce the Configuration Energy of Run Time Reconfigurable Devices [p. 147]
Quaglia, D.
PDF icon Modeling and Simulation Alternatives for the Design of Networked Embedded Systems [p. 1030]
PDF icon A Middleware-centric Design Flow for Networked Embedded Systems [p. 1048]
Quan, G.
PDF icon Peripheral-Conscious Scheduling on Energy Minimization for Weakly Hard Real-time Systems [p. 791]
Quer, S.
PDF icon Boosting the Role of Inductive Invariants in Model Checking [p. 1319]

R

Radecka, K.
PDF icon Reversible Circuit Technology Mapping from Non-reversible Specifications [p. 558]
Raghavan, P.
PDF icon Very Wide Register: An Asymmetric Register File Organization for Low Power Embedded Processors [p. 1066]
Ragheb, T.
PDF icon Thermally Robust Clocking Schemes for 3D Integrated Circuits [p. 1206]
Raghunathan, A.
PDF icon Energy and Execution Time Analysis of a Software-based Trusted Platform Module [p. 1128]
Ramineni, K.
PDF icon Automatic Generation of Functional Coverage Models from Behavioral Verilog Descriptions [p. 900]
Ramzan, R.
PDF icon Boosting SER Test for RF Transceivers by Simple DSP Technique [p. 719]
Rao, W.
PDF icon Logic Level Fault Tolerance Approaches Targeting Nanoelectronics PLAs [p. 865]
Ravi, S.
PDF icon Energy and Execution Time Analysis of a Software-based Trusted Platform Module [p. 1128]
Ravikumar, C.P.
PDF icon On Power-profiling and Pattern Generation for Power-safe Scan Tests [p. 534]
Ravindran, K.
PDF icon A Decomposition-based Constraint Optimization Approach for Statically Scheduling Task Graphs with Communication Delays to Multiprocessors [p. 57]
Ray, S.
PDF icon An Area Optimized Reconfigurable Encryptor for AES-Rijndael [p. 1116]
Rechberger, C.
PDF icon Energy Evaluation of Software Implementations of Block Ciphers under Memory Constraints [p. 1110]
Reddy, S.M.
PDF icon On Test Generation by Input Cube Avoidance [p. 522]
Regazzoni, F.
PDF icon Hardware Scheduling Support in SMP Architectures [p. 642]
Reshadi, M.
PDF icon Interrupt and Low-level Programming Support for Expanding the Application Domain of Statically-Scheduled Horizontally-Microcoded Architectures in Embedded Systems [p. 1337]
Rhod, E.L.
PDF icon A Low-SER Efficient Core Processor Architecture for Future Technologies [p. 1448]
Richter, M.
PDF icon Mapping the Physical Layer of Radio Standards to Multiprocessor Architectures [p. 1412]
Ricketts, A.J.
PDF icon Thermally Robust Clocking Schemes for 3D Integrated Circuits [p. 1206]
Riffiod, M.
PDF icon Development and Industrialization [p. 1403]
Rigaud, J.-B.
PDF icon Experimental Evaluation of Protections against Laser-induced Faults and Consequences on Fault Modeling [p. 1587]
Rincón, F.
PDF icon Lightweight Middleware for Seamless HW-SW Interoperability, with Application to Wireless Sensor Networks [p. 1042]
Ringgenberg, K.
PDF icon Single-ended Coding Techniques for Off-chip Interconnects to Commodity Memory [p. 1072]
Rixner, S.
PDF icon Single-ended Coding Techniques for Off-chip Interconnects to Commodity Memory [p. 1072]
Rocchi, A.
PDF icon Low-g Accelerometer Fast Prototyping for Automotive Applications [p. 486]
Rolain, Y.
PDF icon Nonlinearity Analysis of Analog/RF Circuits Using Combined Multisine and Volterra Analysis [p. 261]
PDF icon Simulation Methodology and Experimental Verification for the Analysis of Substrate Noise on LC-VCO's [p. 1520]
Rolandi, P.
PDF icon A Dynamically Adaptive DSP for Heterogeneous Reconfigurable Platforms[p. 9]
Rosenstiel, W.
PDF icon Timing Simulation of Interconnected AUTOSAR Software-Components [p. 474]
Rosenthal, J.
PDF icon System Level Clock Tree Synthesis for Power Optimization [p. 1677]
Rosinger, P.
PDF icon Joint Consideration of Fault-Tolerance, Energy-Efficiency and Performance in On-Chip Networks [p. 1647]
Rosselló, J.L.
PDF icon Dynamic Critical Resistance: A Timing-Based Critical Resistance Model for Statistical Delay Testing of Nanometer ICs [p. 1271]
Rossi, F.
PDF icon Low Complexity LDPC Code Decoders for Next Generation Standards [p. 331]
Rousseau, B.
PDF icon Enabling Certification for Dynamic Partial Reconfiguration Using a Minimal Flow [p. 983]
Rovini, M.
PDF icon Low Complexity LDPC Code Decoders for Next Generation Standards [p. 331]
Roy, A.
PDF icon Analysis of Power Consumption and BER of Flip-flop Based Interconnect Pipelining [p. 1218]
Roy, K.
PDF icon Process Variation Tolerant Low Power DCT Architecture [p. 630]
PDF icon Low-Overhead Circuit Synthesis for Temperature Adaptation Using Dynamic Voltage Scheduling [p. 1532]
PDF icon Processor Tolerant Beta-Ratio Modulation for Ultra-Dynamic Voltage Scaling [p. 1550]
Roychoudhury, A.
PDF icon Accounting for Cache-Related Preemption Delay in Dynamic Priority Schedulability Analysis [p. 1623]
Roychowdhury, J.
PDF icon Rapid and Accurate Latch Characterization via Direct Newton Solution of Setup/Hold Times [p. 1006]
RoyCowdhury, D.
PDF icon An Area Optimized Reconfigurable Encryptor for AES-Rijndael [p. 1116]
Ruan, S.-J.
PDF icon Improve CAM Power Efficiency Using Decoupled Match Line Scheme [p. 165]
Rubio, A.
PDF icon Testing in the Year 2020 [p. 960]
Ruggiero, M.
PDF icon Capturing the Interaction of the Communication, Memory and I/O Subsystems in Memory-Centric Industrial MPSoC Platforms [p. 660]
Ruiz-Sautua, R.
PDF icon Area Optimization of Multi-Cycle Operators in High-Level Synthesis [p. 449]
Rutenbar, R.A.
PDF icon Statistical Blockade: A Novel Method for Very Fast Monte Carlo Simulation of Rare Circuit Events, and Its Application [p. 1379]

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Sabri, S.
PDF icon A Two-Tone Test Method for Continuous-Time Adaptive Equalizers [p. 1283]
Safar, M.
PDF icon A Shift Register Based Clause Evaluator for Reconfigurable SAT Solver [p. 153]
Safarpour, S.
PDF icon Abstraction and Refinement Techniques in Automated Design Debugging [p. 1182]
PDF icon Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability [p. 1538]
Saglamdemir, O.
PDF icon A Coefficient Optimization and Architecture Selection Tool for ∑Δ Modulators in MATLAB [p. 87]
Sahin, E.
PDF icon An Efficient Hardware Architecture for H.264 Intra Prediction Algorithm [p. 183]
Sakai, S.
PDF icon Utilization of SECDED for Soft Error and Variation-Induced Defect Tolerance in Caches [p. 1134]
Salem, A.
PDF icon A Shift Register Based Clause Evaluator for Reconfigurable SAT Solver [p. 153]
Sánchez, E.
PDF icon (252) An Enhanced Technique for the Automatic Generation of Effective Diagnosis-oriented Test Programs for Processor [p. 1158]
Sanchez, K.
PDF icon Identification of Process/Design Issues during 0.18 μm Technology Qualification for Space Application [p. 989]
Sangiovanni Vincentelli, A.
PDF icon (694) Synthesis of Task and Message Activation Models in Real-Time Distributed Automotive Systems [p. 93]
Sansen, W.
PDF icon An Efficient Methodology for Hierarchical Synthesis of Mixed-Signal Systems with Fully Integrated Building Block Topology Selection [p. 81]
Saponara, S.
PDF icon FPGA-based Networking Systems for High Data-rate and Reliable In-vehicle Communications [p. 480]
Sarlotte, M.
PDF icon New Safety Critical Radio Altimeter for Airbus and Related Design Flow [p. 684]
PDF icon Transaction Level Modeling of SCA Compliant Software Defined Radio Waveforms and Platforms PIM/PSM [p. 966]
Sarmiento, R.
PDF icon Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture: The H.264/AVC Deblocking Filter [p. 177]
Sarrafzadeh, M.
PDF icon Dynamic Reconfiguration in Sensor Networks with Regenerative Energy Sources [p. 1054]
Sassatelli, G.
PDF icon Evaluation of Design for Reliability Techniques in Embedded Flash Memories [p. 1593]
Sathanur, A.
PDF icon Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing [p. 1544]
Satish, N.
PDF icon A Decomposition-based Constraint Optimization Approach for Statically Scheduling Task Graphs with Communication Delays to Multiprocessors [p. 57]
Sauer, C.
PDF icon (374) Hard- and Software Modularity of the NOVA MPSoC Platform [p. 1102]
Sauermann, M.
PDF icon Mapping the Physical Layer of Radio Standards to Multiprocessor Architectures [p. 1412]
Savoj, J.
PDF icon A New Technique for Characterization of Digital-to-Analog Converters in High-Speed Systems [p. 433]
Sawicki, J.
PDF icon DFM/DFY: Should You Trust the Surgeon or the Family Doctor? [p. 439]
Sawitzki, S.
PDF icon Scalable Reconfigurable Channel Decoder Architecture for Future Wireless Handsets [p. 1563]
Schämann, M.
PDF icon Low Power Design on Algorithmic and Architectural Level: A Case Study of an HSDPA Baseband Digital Signal Processing System [p. 1406]
Schaumont, P.
PDF icon Design Methods for Security and Trust [p. 672]
Schillaci, M.
PDF icon (252) An Enhanced Technique for the Automatic Generation of Effective Diagnosis-oriented Test Programs for Processor [p. 1158]
Schlichtmann, U.
PDF icon Trade-Off Design of Analog Circuits Using Goal Attainment and "Wave Front" Sequential Quadratic Programming [p. 75]
Schliecker, S.
PDF icon Performance Analysis of Complex Systems by Integration of Dataflow Graphs and Compositional Performance Analysis [p. 273]
Schmermbeck, S.
PDF icon System Level Clock Tree Synthesis for Power Optimization [p. 1677]
Schmidt, E.
PDF icon System Level Clock Tree Synthesis for Power Optimization [p. 1677]
Schneider, W.
PDF icon Statistical Simulation of High-Frequency Bipolar Circuits [p. 1397]
Schöllhom, A.
PDF icon From Algorithm to First 3.5G Call in Record Time . A Novel System Design Approach Based on Virtual Prototyping and Its Consequences for Interdisciplinary System Design Teams [p. 828]
Schölzel, M.
PDF icon Time-Constrained Clustering for DSE of Clustered VLIW-ASP [p. 467]
Schönberg, L.
PDF icon Impact of Description Language, Abstraction Layer, and Value Representation on Simulation Performance [p. 767]
Schoofs, R.
PDF icon An Efficient Methodology for Hierarchical Synthesis of Mixed-Signal Systems with Fully Integrated Building Block Topology Selection [p. 81]
Schremmer, P.
PDF icon Diagnosis, Modeling and Tolerance of Scan Chain Hold-Time Violations [p. 516]
Schroter, M.
PDF icon Statistical Simulation of High-Frequency Bipolar Circuits [p. 1397]
Segura, J.
PDF icon Dynamic Critical Resistance: A Timing-Based Critical Resistance Model for Statistical Delay Testing of Nanometer ICs [p. 1271]
Seider, D.
PDF icon CMCal: An Accurate Analytical Approach for the Analysis of Process Variations with Non-Gaussian Parameters and Nonlinear Functions [p. 243]
Sengupta, I.
PDF icon An Area Optimized Reconfigurable Encryptor for AES-Rijndael [p. 1116]
Seong, S.-W.
PDF icon An Efficient Code Compression Technique Using Application-Aware Bitmask and Dictionary Selection Methods [p. 582]
Seshia, S.A.
PDF icon Automatic Model Generation for Black Box Real-Time Systems [p. 930]
PDF icon Verification-Guided Soft Error Resilience [p. 1442]
Sha, E.H.-M.
PDF icon Energy Minimization with Soft Real-time and DVS for Uniprocessor and Multiprocessor Embedded Systems [p. 1641]
Shaheen, S.I.
PDF icon Improving Utilization of Reconfigurable Resources Using Two-Dimensional Compaction [p. 135]
Shalan, M.
PDF icon A Shift Register Based Clause Evaluator for Reconfigurable SAT Solver [p. 153]
Shang, L.
PDF icon Accurate Temperature-Dependent Integrated Circuit Leakage Power Estimation Is Easy [p. 1526]
Shao, Z.
PDF icon Energy Minimization with Soft Real-time and DVS for Uniprocessor and Multiprocessor Embedded Systems [p. 1641]
Sharygina, N.
PDF icon Image Computation and Predicate Refinement for RTL Verilog Using Word Level Proofs [p. 1325]
Sheffield, D.
PDF icon Accurate Timing Analysis Using SAT and Pattern-Dependent Delay Models [p. 1018]
Sheibanyrad, A.
PDF icon (142) Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations of a Network on Chip Architecture [p. 1090]
Sheldon, D.
PDF icon Soft-core Processor Customization Using the Design of Experiments Paradigm [p. 821]
Shi, Z.J.
PDF icon Microarchitectural Support for Program Code Integrity Monitoring in Application-specific Instruction Set Processors [p. 815]
Shrivastava, A.
PDF icon (161) Functional and Timing Validation of Partially Bypassed Processor Pipelines [p. 1164]
Shukla, S.K
PDF icon Tackling an Abstraction Gap: Co-Simulating with SystemC DE and Bluespec ESL [p. 279]
PDF icon Design Fault Directed Test Generation for Microprocessor Validation [p. 761]
Shyam, S.
PDF icon Low-cost Protection for SER Upsets and Silicon Defects [p. 1146]
Silveira, L.M.
PDF icon Efficient Computation of the Worst-Delay Corner [p. 1617]
Simunic Rosing, T.
PDF icon Temperature Aware Task Scheduling in MPSoCs [p. 1659]
Sinanoglu, O.
PDF icon A Non-Intrusive Isolation Approach for Soft Cores [p. 27]
PDF icon Diagnosis, Modeling and Tolerance of Scan Chain Hold-Time Violations [p. 516]
Singh, N.K.
PDF icon The Impact of Loop Unrolling on Controller Delay in High Level Synthesis [p. 391]
Singhee, A.
PDF icon Statistical Blockade: A Novel Method for Very Fast Monte Carlo Simulation of Rare Circuit Events, and Its Application [p. 1379]
Sirowy, S.
PDF icon Two-Level Microprocessor-Accelerator Partitioning [p. 313]
PDF icon Clock-Frequency Assignment for Multiple Clock Domain Systems-on-a-Chip [p. 397]
Skadron, K.
PDF icon Impact of Process Variations on Multicore Performance Symmetry [p. 1653]
Smit, G. J. M.
PDF icon Cyclostationary Feature Detection on a Tiled-SoC [p. 171]
Söderquist, I.
PDF icon Event Driven Data Processing Architecture [p. 972]
Soens, C.
PDF icon Simulation Methodology and Experimental Verification for the Analysis of Substrate Noise on LC-VCO's [p. 1520]
Soininen, J.-P.
PDF icon Using Dynamic Voltage Scaling to Reduce the Configuration Energy of Run Time Reconfigurable Devices [p. 147]
Son, S.W.
PDF icon Memory Bank Aware Dynamic Loop Scheduling [p. 1671]
Song, J.
PDF icon Use of Statistical Timing Analysis on Real Designs [p. 1605]
Sonza Reorda, M.
PDF icon (252) An Enhanced Technique for the Automatic Generation of Effective Diagnosis-oriented Test Programs for Processor [p. 1158]
Soudris, D.
PDF icon Middleware Design Optimization of Wireless Protocols Based on the Exploitation of Dynamic Input Patterns [p. 1036]
Spang, O.
PDF icon A Sophisticated Memory Test Engine for LCD Display Drivers [p. 213]
Sparsø, J.
PDF icon A Scalable, Timing-Safe, Network-on-Chip Architecture with an Integrated Clock Distribution Method [p. 648]
Spindler, P.
PDF icon Fast and Accurate Routing Demand Estimation for Efficient Routability-driven Placement [p. 1226]
Squillero, G.
PDF icon (252) An Enhanced Technique for the Automatic Generation of Effective Diagnosis-oriented Test Programs for Processor [p. 1158]
Srivastava, N.R.
PDF icon Radix 4 SRT Division with Quotient Prediction and Operand Scaling [p. 195]
Srivastava, S.
PDF icon Rapid and Accurate Latch Characterization via Direct Newton Solution of Setup/Hold Times [p. 1006]
Stanley-Marbell, P.
PDF icon An 0.9 X 1.2", Low Power, Energy-Harvesting System with Custom Multi-Channel Communication Interface [p. 15]
Stechele, W.
PDF icon Using Partial-Run-Time Reconfigurable Hardware to Accelerate Video Processing in Driver Assistance Systems [p. 498]
Stefanov, T.
PDF icon Performance Analysis of Multimedia Applications Using Correlated Streams [p. 912]
Steger, C.
PDF icon Simulation Platform for UHF RFID [p. 918]
Stein, S.
PDF icon Performance Analysis of Complex Systems by Integration of Dataflow Graphs and Compositional Performance Analysis [p. 273]
Steininger, T.
PDF icon Impact of Description Language, Abstraction Layer, and Value Representation on Simulation Performance [p. 767]
PDF icon Implementation of a Transaction Level Assertion Framework in SystemC [p. 894]
Stensgaard, M.B.
PDF icon A Scalable, Timing-Safe, Network-on-Chip Architecture with an Integrated Clock Distribution Method [p. 648]
Stenstrom, P.
PDF icon Microprocessors in the Era of Terascale Integration [p. 237]
Steyaert, M.
PDF icon An Efficient Methodology for Hierarchical Synthesis of Mixed-Signal Systems with Fully Integrated Building Block Topology Selection [p. 81]
Strano, G.
PDF icon Capturing the Interaction of the Communication, Memory and I/O Subsystems in Memory-Centric Industrial MPSoC Platforms [p. 660]
Streichert, T.
PDF icon Reliability-Aware System Synthesis [p. 409]
Sugihara, M.
PDF icon Task Scheduling for Reliable Cache Architectures of Multiprocessor Systems [p. 1490]
Suhonen, J.
PDF icon Cost-Aware Capacity Optimization in Dynamic Multi-Hop WSNs [p. 666]
Sun, P.
PDF icon Flexibility-oriented Design Methodology for Reconfigurable Delta Sigma Modulators [p. 415]
Sztipanovits, J.
PDF icon Compositional Specification of Behavioral Semantics [p. 906]

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Tabanoglu, G.
PDF icon Timing Simulation of Interconnected AUTOSAR Software-Components [p. 474]
Tadesse, D.
PDF icon Accurate Timing Analysis Using SAT and Pattern-Dependent Delay Models [p. 1018]
Tahar, S.
PDF icon A Symbolic Methodology for the Verification of Analog and Mixed Signal Designs [p. 249]
Talay, S.
PDF icon A Coefficient Optimization and Architecture Selection Tool for ∑Δ Modulators in MATLAB [p. 87]
Tan, S.X.-D.
PDF icon Statistical Model Order Reduction for Interconnect Circuits Considering Spatial Correlations [p. 1508]
Tan, Y.
PDF icon Stochastic Modeling and Optimization for Robust Power Management in a Partially Observable System [p. 779]
Tang, S.
PDF icon A Multi-Core Debug Platform for NoC-Based Systems [p. 870]
Tannir, D.
PDF icon Efficient Nonlinear Distortion Analysis of RF Circuits [p. 255]
Tarjan, D.
PDF icon Impact of Process Variations on Multicore Performance Symmetry [p. 1653]
Tautschnig, M.
PDF icon Tool-Support for the Analysis of Hybrid Systems and Models [p. 924]
Teich, J.
PDF icon Reliability-Aware System Synthesis [p. 409]
Teslyar, Y.
PDF icon ATLAS: A Chip-Multiprocessor with Transactional Memory Support [p. 3]
Teyssou, E.
PDF icon Experimental Evaluation of Protections against Laser-induced Faults and Consequences on Fault Modeling [p. 1587]
Thiele, L.
PDF icon Adaptive Power Management in Energy Harvesting Systems [p. 773]
Thiele, L.
PDF icon Performance Analysis of Multimedia Applications Using Correlated Streams [p. 912]
Thompson, J.S.
PDF icon A New Pipelined Implementation for Minimum Norm Sorting Used in Square Root Algorithm for MIMO-VBLAST Systems [p. 1569]
Thuy, A.
PDF icon Executable System-Level Specification Models Containing UML-Based Behavioral Patterns [p. 301]
Tillich, S.
PDF icon Energy Evaluation of Software Implementations of Block Ciphers under Memory Constraints [p. 1110]
Tiwary, S.K
PDF icon WAVSTAN: Waveform Based Variational Static Timing Analysis [p. 1000]
Toma, M.
PDF icon Implementation of AES/Rijndael on a Dynamically Reconfigurable Architecture [p. 355]
Tonarelli, M.
PDF icon FPGA-based Networking Systems for High Data-rate and Reliable In-vehicle Communications [p. 480]
PDF icon Low-g Accelerometer Fast Prototyping for Automotive Applications [p. 486]
Tong, D.
PDF icon Clock Domain Crossing Fault Model and Coverage Metric for Validation of SoC Design [p. 1385]
Tongbong, J.
PDF icon Evaluation of Test Measures for LNA Production Testing Using a Multinormal Statistical Model [p. 731]
Torres, A.
PDF icon Novel Test Infrastructure and Methodology Used for Accelerated Bring-Up and In-System Characterization of the Multi-Gigahertz Interfaces on the Cell Processor [p. 725]
Torres, L.
PDF icon Evaluation of Design for Reliability Techniques in Embedded Flash Memories [p. 1593]
Tosi, L.
PDF icon RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics [p. 994]
Tria, A.
PDF icon Experimental Evaluation of Protections against Laser-induced Faults and Consequences on Fault Modeling [p. 1587]
Tuncer, E.
PDF icon Use of Statistical Timing Analysis on Real Designs [p. 1605]
Tung, H.-H.
PDF icon Double-Via-Driven Standard Cell Library Design [p. 1212]
Turjan, A.
PDF icon A Process Splitting Transformation for Kahn Process Networks [p. 1355]
Turolla, M.
PDF icon Modeling and Simulation Alternatives for the Design of Networked Embedded Systems [p. 1030]
Tychopoulos, A.
PDF icon Optimization of the "FOCUS" Inband-FEC Architecture for 10-Gbps SDH/SONET Optical Communication Channels [p. 1575]

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Vahid, F.
PDF icon Two-Level Microprocessor-Accelerator Partitioning [p. 313]
PDF icon Clock-Frequency Assignment for Multiple Clock Domain Systems-on-a-Chip [p. 397]
PDF icon A One-Shot Configurable-Cache Tuner for Improved Energy and Performance [p. 755]
PDF icon Soft-core Processor Customization Using the Design of Experiments Paradigm [p. 821]
van den Brand, J.W.
PDF icon Congestion-Controlled Best-Effort Communication for Networks-on-Chip [p. 948]
Van Der Plas, G.
PDF icon Simulation Methodology and Experimental Verification for the Analysis of Substrate Noise on LC-VCO's [p. 1520]
Van Haastregt, S.
PDF icon Feasibility of Combined Area and Performance Optimization for Superscalar Processors Using Random Search [p. 606]
Van Renterghem, K.
PDF icon Development of an ASIP Enabling Flows in Ethernet Access Using a Retargetable Compilation Flow [p. 1418]
Vandecappelle, A.
PDF icon Fast Memory Footprint Estimation Based on Maximal Dependency Vector Calculation [p. 379]
Vandersteen, G.
PDF icon Simulation Methodology and Experimental Verification for the Analysis of Substrate Noise on LC-VCO's [p. 1520]
PDF icon Optimizing Analog Filter Designs for Minimum Nonlinear Distortions Using Multisine Excitations [p. 267]
Vandewege, J.
PDF icon Development of an ASIP Enabling Flows in Ethernet Access Using a Retargetable Compilation Flow [p. 1418]
Vanzi, M.
PDF icon Life Begins at 65 - Unless You Are Mixed Signal? [p. 936]
Vanzolini, L.
PDF icon A Dynamically Adaptive DSP for Heterogeneous Reconfigurable Platforms[p. 9]
Vanzolini, L.
PDF icon Implementation of AES/Rijndael on a Dynamically Reconfigurable Architecture [p. 355]
Vardi, M.
PDF icon PowerQuest: Trace Driven Data Mining for Power Optimization [p. 1078]
Velten, M.
PDF icon Impact of Description Language, Abstraction Layer, and Value Representation on Simulation Performance [p. 767]
PDF icon Implementation of a Transaction Level Assertion Framework in SystemC [p. 894]
Vendraminetto, W.
PDF icon Yield-aware Placement Optimization [p. 1232]
Veneris, A.
PDF icon Abstraction and Refinement Techniques in Automated Design Debugging [p. 1182]
PDF icon Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability [p. 1538]
Verbauwhede, I.
PDF icon Design Methods for Security and Trust [p. 672]
Verdier, F.
PDF icon Transaction Level Modeling of SCA Compliant Software Defined Radio Waveforms and Platforms PIM/PSM [p. 966]
Verhulst, D.
PDF icon Development of an ASIP Enabling Flows in Ethernet Access Using a Retargetable Compilation Flow [p. 1418]
Verkest, D.
PDF icon Very Wide Register: An Asymmetric Register File Organization for Low Power Embedded Processors [p. 1066]
Verma, A.K.
PDF icon Automatic Synthesis of Compressor Trees: Reevaluating Large Counters [p. 443]
Verma, S.
PDF icon Automatic Generation of Functional Coverage Models from Behavioral Verilog Descriptions [p. 900]
Viana, P.
PDF icon A One-Shot Configurable-Cache Tuner for Improved Energy and Performance [p. 755]
Vijaykrishnan, N.
PDF icon Assessing Carbon Nanotube Bundle Interconnect for Future FPGA Architectures [p. 307]
PDF icon Thermally Robust Clocking Schemes for 3D Integrated Circuits [p. 1206]
Villa, D.
PDF icon Lightweight Middleware for Seamless HW-SW Interoperability, with Application to Wireless Sensor Networks [p. 1042]
Villanueva, F.J.
PDF icon Lightweight Middleware for Seamless HW-SW Interoperability, with Application to Wireless Sensor Networks [p. 1042]
Virazel, A.
PDF icon Slow Write Driver Faults in 65nm SRAM Technology: Analysis and March Test Solution [p. 528]
Vitkovski, A.
PDF icon A Dynamically Adaptive DSP for Heterogeneous Reconfigurable Platforms[p. 9]
Voirin, J.-L.
PDF icon Development and Industrialization [p. 1403]
Von Staudt, H.-M.
PDF icon A Sophisticated Memory Test Engine for LCD Display Drivers [p. 213]

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Wagner, I.
PDF icon Engineering Trust with Semantic Guardians [p. 743]
Wahl, M.G.
PDF icon A Sophisticated Memory Test Engine for LCD Display Drivers [p. 213]
Wambacq, P.
PDF icon Nonlinearity Analysis of Analog/RF Circuits Using Combined Multisine and Volterra Analysis [p. 261]
Wang, F.
PDF icon A Novel Criticality Computation Method in Statistical Timing Analysis [p. 1611]
Wang, L.
PDF icon Automatic Model Generation for Black Box Real-Time Systems [p. 930]
Wang, S.
PDF icon Unknown Blocking Scheme for Low Control Data Volume and High Observability [p. 33]
PDF icon SoC Testing Using LFSR Reseeding, and Scan-Slice-Based TAM Optimization and Test Scheduling [p. 201]
Wang, S.-J.
PDF icon High-Level Test Synthesis for Delay Fault Testability [p. 45]
Wang, W.
PDF icon Minimum-Energy LDPC Decoder for Real-Time Mobile Application [p. 343]
Wang, Y.
PDF icon Temperature-aware NBTI Modeling and the Impact of Input Vector Control on Performance Degradation [p. 546]
Wang, Zha.
PDF icon SoC Testing Using LFSR Reseeding, and Scan-Slice-Based TAM Optimization and Test Scheduling [p. 201]
Wang, Zhi.
PDF icon Modeling and Simulation to the Design of ZΔ Fractional-N Frequency Synthesizer [p. 291]
Wassener, H.-J.
PDF icon Life Begins at 65 - Unless You Are Mixed Signal? [p. 936]
Watanabe, R.
PDF icon Task Scheduling under Performance Constraints for Reducing the Energy Consumption of GALS Multi-Processor SoC [p. 797]
Wee, S.
PDF icon ATLAS: A Chip-Multiprocessor with Transactional Memory Support [p. 3]
Wei, G.-Y.
PDF icon Understanding Voltage Variations in Chip Multiprocessors Using a Distributed Power-Delivery Network [p. 624]
Wei, W.
PDF icon Unknown Blocking Scheme for Low Control Data Volume and High Observability [p. 33]
Wei, Y.
PDF icon Flexibility-oriented Design Methodology for Reconfigurable Delta Sigma Modulators [p. 415]
Weiglhofer, M.
PDF icon Automatic Hardware Synthesis from Specifications: A Case Study [p. 1188]
Weiβ, R.
PDF icon Simulation Platform for UHF RFID [p. 918]
When, N.
PDF icon Low Complexity LDPC Code Decoders for Next Generation Standards [p. 331]
Whisnant, K.
PDF icon Temperature Aware Task Scheduling in MPSoCs [p. 1659]
White, J.
PDF icon Optimization-based Wideband Basis Functions for Efficient Interconnect Extraction [p. 1200]
Wielage, P.
PDF icon Design and DFT of a High-Speed Area-Efficient Embedded Asynchronous FIFO [p. 853]
PDF icon Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO [p. 859]
Wilson, A.
PDF icon Towards Total Open Source in Aeronautics and Space? [p. 1556]
Wilson, R.
PDF icon Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops [p. 1012]
Wingen, N.
PDF icon What If You Could Design Tomorrow's System Today? [p. 835]
Wischounig, D.
PDF icon Simulation Platform for UHF RFID [p. 918]
Wittkopf, H.
PDF icon Statistical Simulation of High-Frequency Bipolar Circuits [p. 1397]
Wittmann, R.
PDF icon Life Begins at 65 - Unless You Are Mixed Signal? [p. 936]
Wolff, F.G.
PDF icon A New Asymmetric SRAM Cell to Reduce Soft Errors and Leakage Power in FPGA [p. 1460]
Wong, N.
PDF icon Fast Positive-Real Balanced Truncation of Symmetric Systems Using Cross Riccati Equations [p. 1496]
Wong, W.-F.
PDF icon DRIM: A Low Power Dynamically Reconfigurable Instruction Memory Hierarchy for Embedded Systems [p. 1343]
Wouters, C.
PDF icon Design and DFT of a High-Speed Area-Efficient Embedded Asynchronous FIFO [p. 853]
PDF icon Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO [p. 859]
Wu, C.-A.
PDF icon QuteSAT: A Robust Circuit-based SAT Solver for Complex Circuit Structure [p. 1313]
Wu, Q.
PDF icon Stochastic Modeling and Optimization for Robust Power Management in a Partially Observable System [p. 779]
Wu, Y.
PDF icon Two-Level Microprocessor-Accelerator Partitioning [p. 313]
PDF icon Clock-Frequency Assignment for Multiple Clock Domain Systems-on-a-Chip [p. 397]
Wu, X.
PDF icon System Level Power Optimization of Sigma-Delta Modulator [p. 297]

X

Xie, A.
PDF icon Design Closure Driven Delay Relaxation Based on Convex Cost Network Flow [p. 63]
Xie, Y.
PDF icon Temperature-aware NBTI Modeling and the Impact of Input Vector Control on Performance Degradation [p. 546]
PDF icon A Novel Criticality Computation Method in Statistical Timing Analysis [p. 1611]
Xu, J.
PDF icon Analysis of Power Consumption and BER of Flip-flop Based Interconnect Pipelining [p. 1218]
Xu, Q.
PDF icon A Multi-Core Debug Platform for NoC-Based Systems [p. 870]
Xu, T.
PDF icon A Cross-Referencing-Based Droplet Manipulation Method for High-Throughput and Pin-Constrained Digital Microfluidic Arrays [p. 552]
Xue, C.
PDF icon Energy Minimization with Soft Real-time and DVS for Uniprocessor and Multiprocessor Embedded Systems [p. 1641]
Xue, J.
PDF icon A Sparse Grid Based Spectral Stochastic Collocation Method for Variations-Aware Capacitance Extraction of Interconnects under Nanometer Process Technology [p. 1514]

Y

Yang, C.-L.
PDF icon Energy-Efficient Real-Time Task Scheduling with Task Rejection [p. 1629]
Yang, H.
PDF icon Temperature-aware NBTI Modeling and the Impact of Input Vector Control on Performance Degradation [p. 546]
PDF icon Accurate Temperature-Dependent Integrated Circuit Leakage Power Estimation Is Easy [p. 1526]
Yang, S.
PDF icon Computing Synchronizer Failure Probabilities [p. 1361]
Yang, S.-H.
PDF icon Overcoming Glitches and Dissipation Timing Skews in Design of DPA-Resistant Cryptographic Hardware [p. 1265]
Ye, Z.
PDF icon An FPGA Based All-Digital Transmitter with Radio Frequency Output for Software Defined Radio [p. 21]
Yeh, T.-H.
PDF icon High-Level Test Synthesis for Delay Fault Testability [p. 45]
Yemliha, T.
PDF icon Memory Bank Aware Dynamic Loop Scheduling [p. 1671]
Yetik, O.
PDF icon A Coefficient Optimization and Architecture Selection Tool for ∑Δ Modulators in MATLAB [p. 87]
Yeung, P.
PDF icon Novel Test Infrastructure and Methodology Used for Accelerated Bring-Up and In-System Characterization of the Multi-Gigahertz Interfaces on the Cell Processor [p. 725]
Yoneda, T.
PDF icon An SoC Test Scheduling Algorithm Using Reconfigurable Union Wrappers [p. 231]
Yue, C.P.
PDF icon A Two-Tone Test Method for Continuous-Time Adaptive Equalizers [p. 1283]

Z

Zaki, M. H.
PDF icon A Symbolic Methodology for the Verification of Analog and Mixed Signal Designs [p. 249]
Zamboni, M.
PDF icon An Effective AMS Top-Down Methodology Applied to the Design of a Mixed-Signal UWB System-on-Chip [p. 1424]
Zambreno, J.
PDF icon An FPGA Implementation of Decision Tree Classification [p. 189]
Zamora, N. H.
PDF icon Distributed Power-Management Techniques for Wireless Network Video Systems [p. 564]
Zaslavsky, A.
PDF icon Techniques for Designing Noise-Tolerant Multi-Level Combinational Circuits [p. 576]
Zeng, X.
PDF icon A Sparse Grid Based Spectral Stochastic Collocation Method for Variations-Aware Capacitance Extraction of Interconnects under Nanometer Process Technology [p. 1514]
Zeppenfeld, J.
PDF icon Using Partial-Run-Time Reconfigurable Hardware to Accelerate Video Processing in Driver Assistance Systems [p. 498]
Zhang, M.
PDF icon CMCal: An Accurate Analytical Approach for the Analysis of Process Variations with Non-Gaussian Parameters and Nonlinear Functions [p. 243]
Zhao, W.
PDF icon Fast Statistical Circuit Analysis with Finite-Point Based Transistor Model [p. 1391]
Zheng, W.
PDF icon (694) Synthesis of Task and Message Activation Models in Real-Time Distributed Automotive Systems [p. 93]
PDF icon Automatic Model Generation for Black Box Real-Time Systems [p. 930]
Zhou, D.
PDF icon A Sparse Grid Based Spectral Stochastic Collocation Method for Variations-Aware Capacitance Extraction of Interconnects under Nanometer Process Technology [p. 1514]
Zhou, G.
PDF icon Reconfigurable System-on-Chip Data Processing Units for Space Imaging Instruments [p. 977]
Zhou, H.
PDF icon Design Closure Driven Delay Relaxation Based on Convex Cost Network Flow [p. 63]
Zhou, Q.
PDF icon Test Cost Reduction for SoC Using a Combined Approach to Test Data Compression and Test Scheduling [p. 39]
Zhou, Z.
PDF icon Clock Domain Crossing Fault Model and Coverage Metric for Validation of SoC Design [p. 1385]
Zhu, He.
PDF icon A Sparse Grid Based Spectral Stochastic Collocation Method for Variations-Aware Capacitance Extraction of Interconnects under Nanometer Process Technology [p. 1514]
Zhu, Ho.
PDF icon Mapping Multi-Dimensional Signals into Hierarchical Memory Organizations [p. 385]
Zhu, Q.
PDF icon (161) Functional and Timing Validation of Partially Bypassed Processor Pipelines [p. 1164]
Zhu, Z.
PDF icon Random Sampling of Moment Graph: A Stochastic Krylov-Reduction Algorithm [p. 1502]
Zilic, Z.
PDF icon Reversible Circuit Technology Mapping from Non-reversible Specifications [p. 558]
Zjajo, A.
PDF icon BIST Method for Die-Level Process Parameter Variation Monitoring in Analog/Mixed-Signal Integrated Circuits [p. 1303]