DATE 2014 Proceedings - Table of Contents

Sessions: [Keynotes] [2.2] [2.3] [2.4] [2.5] [2.6] [2.7] [2.8] [3.2] [3.3] [3.4] [3.5] [3.6] [3.7] [3.8] [4.2] [4.3] [4.4] [4.5] [4.6] [4.7] [5.1] [5.2] [5.3] [5.4] [5.5] [5.6] [5.7] [5.8] [6.1] [6.2] [6.3] [6.4] [6.5] [6.6] [6.7] [7.0] [7.2] [7.3] [7.4] [7.5] [7.6] [7.7] [8.1] [8.2] [8.3] [8.4] [8.5] [8.6] [8.7] [8.8] [9.1] [9.2] [9.3] [9.4] [9.5] [9.6] [9.7] [9.8] [10.1] [10.2] [10.3] [10.4] [10.5] [10.6] [10.7] [11.0] [11.1] [11.2] [11.3] [11.4] [11.5] [11.6] [11.7] [11.8] [12.1] [12.2] [12.3] [12.4] [12.5] [12.6] [12.7] [12.8]

DATE 14 Sponsors [1]
DATE Executive Committee [2]
DATE Sponsors Committee [3]
Technical Program Topic Chairs [4]
Technical Program Committee [5]
Reviewers [6]
Foreword [7]
Best Paper Awards [8]
ACM SIGDA/EDAA PH.D. Forum [9]
Call for Papers: DATE 2015 [10]

1.1.1 Keynote: System Design Challenges for Next Generation Wireless and Embedded Systems

[11] [12] David Fuller - National Instruments, US

1.1.2 Keynote: The Growing Importance of Microelectronics from a Foundry Perspective

[13] [14] Gerd Teepe - GLOBALFOUNDRIES, DE

2.2 Panel: Emerging vs. Established Technologies: A Two Sphinxes' Riddle at the Crossroads?

Organizer: Marco Casale-Rossi, Synopsys, Inc., US
Chair: Giovanni De Micheli, EPFL, CH

[15] [16] Panelists: Rob Aitken, Antun Domic, Manfred Horstmann, Robert Hum, Philippe Magarshack

2.3 Making Automotive Systems Safer and More Energy Efficient

Chairs: Bart Vermeulen, NXP Semiconductors, NL; Martin Lukasiewycz, TUM CREATE, SG

[17] [18] Emulation-Based Robustness Assessment for Automotive Smart-Power ICs: Manuel Harrant, Thomas Nirmaier, Jérôme Kirscher, Christoph Grimm, Georg Pelz
[19] [20] Startup Error Detection and Containment to Improve the Robustness of Hybrid FlexRay Networks: Alexander Kordes, Bart Vermeulen, Abhijit Deb, Michael G. Wahl
[21] [22] A Self-Propagating Wakeup Mechanism for Point-to-Point Networks with Partial Network Support: Jan R. Seyler, Thilo Streichert, Juri Warkentin, Matthias Spägele, Michael Glaβ, Jürgen Teich
[23] [24] Multi-Variant-based Design Space Exploration for Automotive Embedded Systems: Sebastian Graf, Michael Glaβ, Jürgen Teich, Christoph Lauer
[25] [26] SAFE: Security-Aware FlexRay Scheduling Engine: Gang Han, Haibo Zeng, Yaping Li, Wenhua Dou
[27] [28] Transient Errors Resiliency Analysis Technique for Automotive Safety Critical Applications: Sujan Pandey and Bart Vermeulen

2.4 Modern Challenges in Analog and Mixed-Signal Design

Chairs: Georges Gielen, KU Leuven, BE; Günhan Dündar, Bogazici University, TR

[29] [30] Electromigration-Aware and IR-Drop Avoidance Routing in Analog Multiport Terminal Structures: Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta
[31] [32] Zonotope-based Nonlinear Model Order Reduction for Fast Performance Bound Analysis of Analog Circuits with Multiple-interval-valued Parameter Variations: Yang Song, Sai Manoj P.D., Hao Yu
[33] [34] Implementation Issues in the Hierarchical Composition of Performance Models of Analog Circuits: M. Velasco-Jiménez, R. Castro-López, E. Roca, F.V. Fernández
[35] [36] Modeling of an Analog Recording System Design for ECoG and AP Signals: Nils Heidmann, Nico Hellwege, Tim Höhlein, Thomas Westphal, Dagmar Peters-Drolshagen, Steffen Paul
[37] [38] Model Based Hierarchical Optimization Strategies for Analog Design Automation: Engin Afacan, Simge Ay, F.V. Fernández, Günhan Dündar, Faik Baskaya
[39] [40] A Novel Low Power 11-bit Hybrid ADC Using Flash and Delay Line Architectures: Hsun-Cheng Lee and Jacob A. Abraham
[41] [42] Semi-Symbolic Analysis of Mixed-Signal Systems Including Discontinuities: Carna Radojicic, Christoph Grimm, Javier Moreno, Xiao Pan
[43] [44] Novel Circuit Topology Synthesis Method Using Circuit Feature Mining and Symbolic Comparison: Cristian Ferent and Alex Doboli
[45] [46] An Embedded Offset and Gain Instrument for OpAmp IPs: Jinbo Wan and Hans G. Kerkhoff

2.5 Low-Power and Efficient Architectures

Chairs: Cristina Silvano, Politecnico di Milano, IT; Todd Austin, University of Michigan, US

[47] [48] Energy-Efficient Scheduling for Memory-Intensive GPGPU Workloads: Seokwoo Song, Minseok Lee, John Kim, Woong Seo, Yeongon Cho, Soojung Ryu
[49] [50] dSVM: Energy-Efficient Distributed Scratchpad Video Memory Architecture for the Next-Generation High Efficiency Video Coding: Felipe Sampaio, Muhammad Shafique, Bruno Zatt, Sergio Bampi, Jörg Henkel
[51] [52] Feasibility Exploration of NVM Based I-Cache through MSHR Enhancements: Manu Komalan, José Ignacio Gómez Pérez, Christian Tenllado, Praveen Raghavan, Matthias Hartmann, Francky Catthoor
[53] [54] EVX: Vector Execution on Low Power EDGE Cores: Milovan Duric, Oscar Palomar, Aaron Smith, Osman Unsal, Adrian Cristal, Mateo Valero, Doug Burger
[55] [56] Program Affinity Performance Models for Performance and Utilization: Ryan W. Moore and Bruce R. Childers
[57] [58] Advanced SIMD: Extending the Reach of Contemporary SIMD Architectures: Matthias Boettcher, Bashir M. Al-Hashimi, Mbou Eyole, Giacomo Gabrielli, Alastair Reid
[59] [60] A Tightly-coupled Hardware Controller to Improve Scalability and Programmability of Shared-Memory Heterogeneous Clusters: Paolo Burgio, Robin Danilo, Andrea Marongiu, Philippe Coussy, Luca Benini

2.6 Real-Time Memory Hierarchies

Chairs: Benny Akesson, CTU Prague, CZ; Giuseppe Lipari, ENS - Cachan, FR

[61] [62] On the Correctness, Optimality and Precision of Static Probabilistic Timing Analysis: Sebastian Altmeyer, Robert I. Davis
[63] [64] WCET-Centric Dynamic Instruction Cache Locking: Huping Ding, Yun Liang, Tulika Mitra
[65] [66] Minimizing Stack Memory for Hard Real-time Applications on Multicore Platforms: Chuansheng Dong, Haibo Zeng
[67] [68] Time-predictable Execution of Multithreaded Applications on Multicore Systems: Ahmed Alhammad, Rodolfo Pellizzoni

2.7 Yield and Reliability for Robust Systems

Chairs: Joan Figueras, UPC, ES; Jose Pineda de Gyvez, NXP, NL

[69] [70] Comprehensive Analysis of Alpha and Neutron Particle-induced Soft Errors in an Embedded Processor at Nanoscales: Mojtaba Ebrahimi, Adrian Evans, Mehdi B. Tahoori, Razi Seyyedi, Enrico Costenaro, Dan Alexandrescu
[71] [72] Bias Temperature Instability Analysis of FinFET Based SRAM Cells: Seyab Khan, Innocent Agbo, Said Hamdioui, Halil Kukner, Ben Kaczer, Praveen Raghavan, Francky Catthoor
[73] [74] SSFB: A Highly-Efficient and Scalable Simulation Reduction Technique for SRAM Yield Analysis: Manish Rana, Ramon Canal
[75] [76] INFORMER: An Integrated Framework for Early-Stage Memory Robustness Analysis: Shrikanth Ganapathy, Ramon Canal, Dan Alexandrescu, Enrico Costenaro, Antonio González, Antonio Rubio
[77] [78] Wear-out Analysis of Error Correction Techniques in Phase-change Memory: Caio Hoffman, Luiz Ramos, Rodolfo Azevedo, Guido Araújo
[79] [80] Approximating the Age of RF/Analog Circuits through Re-characterization and Statistical Estimation: Doohwang Chang, Sule Ozev, Ozgur Sinanoglu, Ramesh Karri

2.8 Hot Topic: Technology Transfer towards Horizon 2020

Organizer: Rainer Leupers, RWTH Aachen, Germany
Chair: Norbert Wehn, TU Kaiserslautern, Germany

[81] [82] Technology Transfer towards Horizon 2020: Rainer Leupers

3.2 Panel: The World Is Going... Analog & Mixed-Signal! What about EDA?

Organizer: Marco Casale-Rossi, Synopsys, Inc., US.
Chair: Pietro Palella, STMicroelectronics, IT

[83] [84] Panelists: Mario Anton, Ori Galzur, Robert Hum, Rainer Kress, Paul Lo

3.3 Secure Hardware Primitives and Implementations

Chairs: Paolo Maistri, TIMA, FR; Patrick Schaumont, Virginia Tech, US

[85] [86] Lightweight Code-based Cryptography: QC-MDPC McEliece Encryption on Reconfigurable Devices: Ingo von Maurich, Tim Güneysu
[87] [88] On the Assumption of Mutual Independence of Jitter Realizations in P-Trng Stochastic Models: Patrick Haddad, Yannick Teglia, Florent Bernard, Viktor Fischer
[89] [90] Clock-Modulation Based Watermark for Protection of Embedded Processors: Jedrzej Kufel, Peter Wilson, Stephen Hill, Bashir M. Al-Hashimi, Paul N. Whatmough, James Myers

3.4 Modeling and Optimization of Power Distribution Networks

Chairs: Luca Daniel, MIT, US; Stefano Grivet-Talocia, Politecnico di Torino, IT

[91] [92] Sensitivity-based Weighting for Passivity Enforcement of Linear Macromodels in Power Integrity Applications: A. Ubolli, S. Grivet-Talocia, M. Bandinu, A. Chinea
[93] [94] Efficient Analysis of Variability Impact on Interconnect Lines and Resistor Networks: Jorge Fernández Villena, L. Miguel Silveira
[95] [96] Implicit Index-aware Model Order Reduction for RLC/RC Networks: Nicodemus Banagaaya, Giuseppe Alì, Wil. H.A. Schilders, Caren Tischendorf
[97] [98] P/G TSV Planning for IR-drop Reduction in 3D-ICs: Shengcheng Wang, Farshad Firouzi, Fabian Oboril, Mehdi B. Tahoori
[99] [100] Package Geometric Aware Thermal Analysis by Infrared-Radiation Thermal Images: Jui-Hung Chien, Hao Yu, Ruei-Siang Hsu, Hsueh-Ju Lin, Shih-Chieh Chang
[101] [102] Cost-Effective Decap Selection for Beyond Die Power Integrity: Yi-En Chen, Tu-Hsiung Tsai, Shi-Hao Chen, Hung-Ming Chen
[103] [104] Characterizing Power Delivery Systems with On/Off-Chip Voltage Regulators for Many-Core Processors: Xuan Wang, Jiang Xu, Zhe Wang, Kevin J. Chen, Xiaowen Wu, Zhehui Wang
[105] [106] Mask-Cost-Aware ECO Routing: Hsi-An Chien, Zhen-Yu Peng, Yun-Ru Wu, Ting-Hsiung Wang, Hsin-Chang Lin, Chi-Feng Wu, Ting-Chi Wang

3.5 Robust Architectures

Chairs: Todd Austin, University of Michigan, US; Muhammad Shafique, Karlsruhe Institute of Technology, DE

[107] [108] Coupling TDM NoC and DRAM Controller for Cost and Performance Optimization of Real-Time Systems: Manil Dev Gomony, Benny Akesson, Kees Goossens
[109] [110] Bus Designs for Time-Probabilistic Multicore Processors: Javier Jalle, Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla
[111] [112] Programmable Decoder and Shadow Threads: Tolerate Remote Code Injection Exploits with Diversified Redundancy: Ziyi Liu, Weidong Shi, Shouhuai Xu, Zhiqiang Lin
[113] [114] Exploiting Narrow-Width Values for Improving Non-Volatile Cache Lifetime: Guangshan Duan, Shuai Wang
[115] [116] Partial-SET: Write Speedup of PCM Main Memory: Bing Li, ShuChang Shan, Yu Hu, Xiaowei Li

3.6 Cyber Physical Systems: Security and Co-design

Chairs: Rolf Ernst, Technische Universitaet Braunschweig, DE; Anuradha Annaswamy, MIT, US

[117] [118] Attack-Resilient Sensor Fusion: Radoslav Ivanov, Miroslav Pajic, Insup Lee
[119] [120] Bandwidth-Efficient Controller-Server Co-Design with Stability Guarantees: Amir Aminifar, Enrico Bini, Petru Eles, Zebo Peng
[121] [122] Fault-tolerant Control Synthesis and Verification of Distributed Embedded Systems: Matthias Kauer, Damoon Soudbakhsh, Dip Goswami, Samarjit Chakraborty, Anuradha M. Annaswamy
[123] [124] Garbage Collection for Multi-version Index on Flash Memory: Kam-Yiu Lam, Jiantao Wang, Yuan-Hao Chang, Jen-Wei Hsieh, Po-Chun Huang, Chung Keung Poon, Chun Jiang Zhu
[125] [126] D2Cyber: A Design Automation Tool for Dependable Cybercars: Arslan Munir, Farinaz Koushanfar
[127] [128] Contract-Based Design of Control Protocols for Safety-Critical Cyber-Physical Systems: Pierluigi Nuzzo, John B. Finn, Antonio Iannopollo, Alberto L. Sangiovanni-Vincentelli

3.7 On line Strategies for Reliability

Chairs: Fabrizio Lombardi, Northwestern University, US; JIe Han, University of Alberta, CA

[129] [130] Spatial Pattern Prediction Based Management of Faulty Data Caches: Georgios Keramidas, Michail Mavropoulos, Anna Karvouniari, Dimitris Nikolos
[131] [132] Combined DVFS and Mapping Exploration for Lifetime and Soft-Error Susceptibility Improvement in MPSoCs: A. Das, A. Kumar, B. Veeravalli, C. Bolchini, A. Miele
[133] [134] DARP: Dynamically Adaptable Resilient Pipeline Design in Microprocessors: Hu Chen, Sanghamitra Roy, Koushik Chakraborty
[135] [136] A Fault Detection Mechanism in a Data-flow Scheduled Multithreaded Processor: Jian Fu, Qiang Yang, Raphael Poss, Chris R. Jesshope, Chunyuan Zhang

3.8 Hot Topic: Mission Profile Aware Design - The Solution for Successful Design of Tomorrows Automotive Electronics

Organizers: Goeran Jerke, Robert Bosch GmbH, DE; Oliver Bringmann, University of Tuebingen, DE
Chairs: Goeran Jerke, Robert Bosch GmbH, DE; Oliver Bringmann, University of Tuebingen, DE

[137] [138] Mission Profile Aware IC Design - A Case Study: Goeran Jerke, Andrew B. Kahng
[139] [140] Mission Profile Aware Robustness Assessment of Automotive Power Devices: Thomas Nirmaier, Andreas Burger, Manuel Harrant, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel, Georg Pelz
[141] [142] Application of Mission Profiles to Enable Cross-Domain Constraint-Driven Design: C. Katzschke, M.-P. Sohn, M. Olbrich, V. Meyer zu Bexten, M. Tristl, E. Barke

4.2 Hot Topic: Multicore Systems in Safety Critical Electronic Control Units for Automotive and Avionics

Organizers and Chairs: Jürgen Becker, KIT, DE; Oliver Sander, KIT, DE

[143] [144] Monitoring and WCET Analysis in COTS Multi-core-SoC-based Mixed-Criticality Systems: Jan Nowotsch, Michael Paulitsch, Arne Henrichsen, Werner Pongratz, Andreas Schacht
[145] [146] Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems: Oliver Sander, Timo Sandmann, Viet Vu Duy, Steffen Bähr, Falco Bapp, Jürgen Becker, Hans Ulrich Michel, Dirk Kaule, Daniel Adam, Enno Lübbers, Jürgen Hairbucher, Andre Richter, Christian Herber, Andreas Herkersdorf

4.3 Secure Device Identification

Chairs: Tim Gueneysu, RUB, DE; Guido Bertoni, TMicroelectronics, IT

[147] [148] ARO-PUF: An Aging-Resistant Ring Oscillator PUF Design: Md. Tauhidur Rahman, Domenic Forte, Jim Fahrny, Mohammad Tehranipoor
[149] [150] An Efficient Reliable PUF-Based Cryptographic Key Generator in 65nm CMOS: Mudit Bhargava, Ken Mai
[151] [152] Increasing the Efficiency of Syndrome Coding for PUFs with Helper Data Compression: Matthias Hiller, Georg Sigl
[153] [154] Key-recovery Attacks on Various RO PUF Constructions via Helper Data Manipulation: Jeroen Delvaux, Ingrid Verbauwhede

4.4 "Almost There" Emerging Technologies

Chairs: Ian O'Connor, University of Lyon, FR; Michael Niemier, University of Notre Dame, US

[155] [156] IIR Filters Using Stochastic Arithmetic: Naman Saraf, Kia Bazargan, David J. Lilja, Marc D. Riedel
[157] [158] Efficient Transient Thermal Simulation of 3D ICs with Liquid-Cooling and Through Silicon Vias: Alain Fourmigue, Giovanni Beltrame, Gabriela Nicolescu
[159] [160] A Logic Integrated Optimal Pin-Count Design for Digital Microfluidic Biochips: Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho
[161] [162] Fast and Accurate Computation Using Stochastic Circuits: Armin Alaghi, John P. Hayes

4.5 Memory System Architectures

Chairs: Muhammad Shafique, Karlsruhe Institute of Technology, DE; Cristina Silvano, Politecnico di Milano, IT

[163] [164] Achieving Efficient Packet-based Memory System by Exploiting Correlation of Memory Requests: Tianyue Lu, Licheng Chen, Mingyu Chen
[165] [166] ALLARM: Optimizing Sparse Directories for Thread-Local Data: Amitabha Roy, Timothy M. Jones
[167] [168] Introducing Thread Criticality Awareness in Prefetcher Aggressiveness Control: Biswabandan Panda, Shankar Balachandran
[169] [170] A Multi Banked - Multi Ported - non Blocking Shared L2 Cache for MPSoC Platforms: Igor Loi, Luca Benini
[171] [172] DRAM-based Coherent Caches and How to Take Advantage of the Coherence Protocol to Reduce the Refresh Energy: Zoran Jaksić, Ramon Canal
[173] [174] Reducing Set-Associative L1 Data Cache Energy by Early Load Data Dependence Detection (ELD³): Alen Bardizbanyan, Magnus Själander, David Whalley, Per Larsson-Edefors
[175] [176] Distributed Cooperative Shared Last-Level Caching in Tiled Multiprocessor System on Chip: Preethi P. Damodaran, Stefan Wallentowitz, Andreas Herkersdorf

4.6 Code Generation and Optimization for Embedded Platforms

Chairs: Heiko Falk, Ulm University, DE; Florence Maraninchi, Grenoble IMP/VERIMAG, FR

[177] [178] EATBit: Effective Automated Test for Binary Translation with High Code Coverage: Hui Guo, Zhenjiang Wang, Chenggang Wu, Ruining He
[179] [180] On-Device Objective-C Application Optimization Framework for High-Performance Mobile Processors: Garo Bournoutian, Alex Orailoglu
[181] [182] Code Generation for Embedded Heterogeneous Architectures on Android: Richard Membarth, Oliver Reiche, Frank Hannig, Jürgen Teich
[183] [184] Design of Safety Critical Systems by Refinement: Alex Iliasov, Arseniy Alekseyev, Danil Sokolov, Andrey Mokhov
[185] [186] Energy Optimization in Android Applications through Wakelock Placement: Faisal Alam, Preeti Ranjan Panda, Nikhil Tripathi, Namita Sharma, Sanjiv Narayan
[187] [188] A Wear-Leveling-Aware Dynamic Stack for PCM Memory in Embedded Systems: Qingan Li, Yanxiang He, Yong Chen, Chun Jason Xue, Nan Jiang, Chao Xu
[189] [190] Lifetime Holes Aware Register Allocation for Clustered VLIW Processors: Xuemeng Zhang, Hui Wu, Haiyan Sun, Jingling Xue

4.7 Dependable System Design

Chairs: Yiorgos Makris, University of Texas at Dallas, US; Michael Nicolaidis, TIMA, FR

[191] [192] Real-Time Trust Evaluation in Integrated Circuits: Yier Jin, Dean Sullivan
[193] [194] Verification-guided Voter Minimization in Triple-Modular Redundant Circuits: Dmitry Burlyaev, Pascal Fradet, Alain Girault
[195] [196] Trade-offs in Execution Signature Compression for Reliable Processor Systems: Jonah Caplan, Maria Isabel Mera, Peter Milder, Brett H. Meyer
[197] [198] An Energy-Aware Fault Tolerant Scheduling Framework for Soft Error Resilient Cloud Computing Systems: Yue Gao, Sandeep K. Gupta, Yanzhi Wang, Massoud Pedram
[199] [200] A Low-Power, High-Performance Approximate Multiplier with Configurable Partial Error Recovery: Cong Liu, Jie Han, Fabrizio Lombardi

5.1 Hot Topic: Predictable Multi-Core Computing

Organizer: Jürgen Teich, Erlangen-Nuremberg U, DE
Chairs: Petru Eles, Linkoping U, SE; Jürgen Teich, Erlangen-Nuremberg U, DE

[201] [202] Impact of Resource Sharing on Performance and Performance Prediction: Jan Reineke, Reinhard Wilhelm
[203] [204] Time-Critical Computing on a Single Chip Massively Parallel Processor: Benoît Dupont de Dinechin, Duco van Amstel, Marc Poulhiès, Guillaume Lager
[205] [206] Mapping Mixed-Criticality Applications on Multi-Core Architectures: Georgia Giannopoulou, Nikolay Stoimenov, Pengcheng Huang, Lothar Thiele

5.2 Hot Topic: Hacking and Protecting Hardware: Threats and Challenges

Organizers: Said Hamdioui, TU Delft, NL; Giorgio Di Natale, LIRMM, FR
Chairs: Said Hamdioui, TU Delft, NL; Giorgio Di Natale, LIRMM, FR

[207] [208] Hacking and Protecting IC Hardware: Said Hamdioui, Giorgio Di Natale, Gerard van Battum, Jean-Luc Danger, Fethulah Smailbegovic, Mark Tehranipoor

5.3 Reliable Systems in the Age of Variability

Chairs: Antonio Miele, Politecnico di Milano, IT; José L. Ayala, Complutense University of Madrid, ES

[209] [210] Temporal Memoization for Energy-Efficient Timing Error Recovery in GPGPUs: Abbas Rahimi, Luca Benini, Rajesh K. Gupta
[211] [212] Reliability-Aware Exceptions: Tolerating Intermittent Faults in Microprocessor Array Structures W: Waleed Dweik, Murali Annavaram, Michel Dubois
[213] [214] Temperature Aware Energy-Reliability Trade-offs for Mapping of Throughput-Constrained Applications on Multimedia MPSoCs: Anup Das, Akash Kumar, Bharadwaj Veeravalli
[215] [216] Recovery-Based Resilient Latency-Insensitive Systems: Yuankai Chen, Xuan Zeng, Hai Zhou
[217] [218] A Linux-Governor Based Dynamic Realiability Manager for Android Mobile Devices: Pietro Mercati, Andrea Bartolini, Francesco Paterna, Tajana Simunic Rosing, Luca Benini
[219] [220] Yield and Timing Constrained Spare TSV Assignment for Three-Dimensional Integrated Circuits: Yu-Guang Chen, Kuan-Yu Lai, Ming-Chao Lee, Yiyu Shi, Wing-Kai Hon, Shih-Chieh Chang
[221] [222] Compiler-Driven Dynamic Reliability Management for On-Chip Systems under Variabilities: Semeen Rehman, Florian Kriebel, Muhammad Shafique, Jörg Henkel

5.4 Prediction and Optimization of Timing Variations

Chairs: Antonio Rubio, UPC Barcelona, ES; Marisa López Vallejo, UPM Madrid,ES

[223] [224] Efficient High-Sigma Yield Analysis for High Dimensional Problems: Moning Zhang, Zuochang Ye, Yan Wang
[225] [226] Sub-threshold Logic Circuit Design Using Feedback Equalization: Mahmoud Zangeneh, Ajay Joshi
[227] [228] Stochastic Analysis of Bubble Razor: Guowei Zhang, Peter Beerel
[229] [230] Minimizing State-of-Health Degradation in Hybrid Electrical Energy Storage Systems with Arbitrary Source and Load Profiles: Yanzhi Wang, Xue Lin, Qing Xie, Naehyuck Chang, Massoud Pedram
[231] [232] Dynamic Flip-Flop Conversion to Tolerate Process Variation in Low Power Circuits: Mehrzad Nejat, Bijan Alizadeh, Ali Afzali Kusha
[233] [234] A Low Power and Robust Carbon Nanotube 6T SRAM Design with Metallic Tolerance: Luo Sun, Jimson Mathew, Rishad A. Shafik, Dhiraj K. Pradhan, Zhen Li

5.5 Boosting the Scalability of Formal Verification Technologies

Chairs: Fahim Rahim, Atrenta, FR; Bernd Becker, University of Freiburg, DE

[235] [236] Scalable Liveness Verification for Communication Fabrics: Sebastiaan J.C. Joosten, Julien Schmaltz
[237] [238] Property Directed Invariant Refinement for Program Verification: Tobias Welp, Andreas Kuehlmann
[239] [240] Simple Interpolants for Linear Arithmetic: Christoph Scholl, Florian Pigorsch, Stefan Disch, Ernst Althaus
[241] [242] Tightening BDD-based Approximate Reachability with SAT-based Clause Generalization: G. Cabodi, P. Pasini, S. Quer, D. Vendraminetto
[243] [244] Make it Real: Effective Floating-Point Reasoning via Exact Arithmetic: Miriam Leeser, Saoni Mukherjee, Jaideep Ramachandran, Thomas Wahl

5.6 Emerging Logic Technologies

Chairs: Mehdi Tahoori, KIT, DE; Marco Ottavi, University of Rome "Tor Vergata", IT

[245] [246] RETLab: A Fast Design-automation Framework for Arbitrary RET Networks: Mohammad D. Mottaghi, Arjun Rallapalli, Chris Dwyer
[247] [248] Design of 3D Nanomagnetic Logic Circuits: A Full-Adder Case Study: Robert Perricone, X. Sharon Hu, Joseph Nahas, Michael Niemier
[249] [250] Highly Accurate SPICE-Compatible Modeling for Single- and Double-Gate GNRFETs with Studies on Technology Scaling: Morteza Gholipour, Ying-Yu Chen, Amit Sangai, Deming Chen
[251] [252] Rewiring for Threshold Logic Circuit Minimization: Chia-Chun Lin, Chun-Yao Wang, Yung-Chih Chen, Ching-Yi Huang
[253] [254] Width Minimization in the Single-Electron Transistor Array Synthesis: Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan
[255] [256] Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints: Yi-Hang Chen, Jian-Yu Chen, Juinn-Dar Huang
[257] [258] Software-based Pauli Tracking in Fault-tolerant Quantum Circuits: Alexandru Paler, Simon Devitt, Kae Nemoto, Ilia Polian

5.7 Test generation and optimization

Chairs: Xiaoqing Wen, Kyushu Institute of Technology, JP; Grzegorz Mrugalski, Mentor Graphics, PL

[259] [260] Efficient SMT-based ATPG for Interconnect Open Defects: Dominik Erb, Karsten Scheibler, Matthias Sauer, Bernd Becker
[261] [262] Interconnect Test for 3D Stacked Memory-on-Logic: Mottaqiallah Taouil, Mahmoud Masadeh, Said Hamdioui, Erik Jan Marinissen
[263] [264] An Effective Approach to Automatic Functional Processor Test Generation for Small-Delay Faults: Andreas Riefert, Lyl Ciganda, Matthias Sauer, Paolo Bernardi, Matteo Sonza Reorda, Bernd Becker
[265] [266] Multi-Site Test Optimization for Multi-V_dd SoCs Using Space- and Time-Division Multiplexing: Fotios Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Rubin Parekhji, Arvind Jain
[267] [268] An Efficient Temperature-Gradient Based Burn-In Technique for 3D Stacked ICs: Nima Aghaee, Zebo Peng, Petru Eles
[269] [270] Test and Non-Test Cubes for Diagnostic Test Generation Based on Merging of Test Cubes: Irith Pomeranz
[271] [272] New Implementions of Predictive Alternate Analog/RF test with Augmented Model Redundancy: H. Ayari, F. Azais, S. Bernard, M. Comte, V. Kerzerho, M. Renovell

5.8 System Integration - The Bridge between More than Moore and More Moore

Organizers: Manfred Dietrich, Fraunhofer IIS/EAS Dresden, DE; Kai Hahn, University Siegen,DE
Chairs: Manfred Dietrich, Fraunhofer IIS/EAS Dresden, DE; Kai Hahn, University Siegen, DE

[273] [274] System Integration - The Bridge between More than Moore and More Moore: Andy Heinig, Manfred Dietrich, Andreas Herkersdorf, Felix Miller, Thomas Wild, Kai Hahn, Armin Grünewald, Rainer Brück, Steffen Kröhnert, Jochen Reisinger

6.1 Hot Topic: The Fight against Dark Silicon

Organizer: Jörg Henkel, Karlsruhe Institute of Technology, DE
Chairs: Jörg Henkel, Karlsruhe Institute of Technology, DE Jürgen Teich, Erlangen-Nuremberg U, DE

[275] [276] A Landscape of the New Dark Silicon Design Regime: Michael B. Taylor
[277] [278] Integrated Microfluidic Power Generation and Cooling for Bright Silicon MPSoCs: Mohamed M. Sabry, Arvind Sridhar, David Atienza, Patrick Ruch, Bruno Michel
[279] [280] Effective Resource Management towards Efficient Computing: Per Stenström

6.2 Embedded Tutorial: Emerging Transistor Technologies: From Devices to Architectures

Organizers: Michael Niemier, University of Notre Dame, US; X. Sharon Hu, University of Notre Dame, US
Chair: Michael Niemier, University of Notre Dame, US

[281] [282] Modeling Steep Slope Devices: From Circuits to Architectures: Karthik Swaminathan, Moon Seok Kim, Nandhini Chandramoorthy, Behnam Sedighi, Robert Perricone, Jack Sampson, Vijaykrishnan Narayanan
[283] [284] Impact of Steep-Slope Transistors on Non-Von Neumann Architectures: CNN Case Study: Indranil Palit, Behnam Sedighi, András Hortváth, X. Sharon Hu, Joseph Nahas, Michael Niemier

6.3 Management of Micro/Macro Renewable Energy Storage Systems

Chairs: Geoff Merrett, University of Southampton,UK Davide Brunelli, University of Trento, IT

[285] [286] Asynchronous Design for New On-Chip Wide Dynamic Range Power Electronics: Delong Shang, Xuefu Zhang, Fei Xia, Alex Yakovlev
[287] [288] Real-time Optimization of the Battery Banks Lifetime in Hybrid Residential Electrical Systems: Maurizio Rossi, Alessandro Toppano, Davide Brunelli
[289] [290] Optimal Dimensioning of Active Cell Balancing Architectures: Swaminathan Narayanaswamy, Sebastian Steinhorst, Martin Lukasiewycz, Matthias Kauer, Samarjit Chakraborty
[291] [292] Optimal Design and Management of a Smart Residential PV and Energy Storage System: Di Zhu, Yanzhi Wang, Naehyuck Chang, Massoud Pedram
[293] [294] Design and Fabrication of a 315 μH Bondwire Micro-Transformer for Ultra-Low Voltage Energy Harvesting: Enrico Macrelli, Ningning Wang, Saibal Roy, Michael Hayes, Rudi Paolo Paganelli, Marco Tartagni, Aldo Romani
[295] [296] Providing Regulation Services and Managing Data Center Peak Power Budgets: Baris Aksanli, Tajana Rosing
[297] [298] The Energy Benefit of Level-crossing Sampling Including the Actuator's Energy Consumption: Burkhard Hensel, Klaus Kabitzsch

6.4 Power Delivery and Distribution

Chairs: Edith Beigné, CEA LETI Grenoble, FR; Domenik Helms, OFFIS Oldenburg, DE

[299] [300] Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors: Masaaki Kondo, Hiroaki Kobyashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda, Hiroshi Nakamura
[301] [302] SuperRange: Wide Operational Range Power Delivery Design for Both STV and NTV Computing: Xin He, Guihai Yan, Yinhe Han, Xiaowei Li
[303] [304] Modeling and Analysis of Digital Linear Dropout Regulators with Adaptive Control for High Efficiency under Wide Dynamic Range Digital Loads: Samantak Gangopadhyay, Youngtak Lee, Saad Bin Nasir, Arijit Raychowdhury

6.5 Beyond EDA: Extending the Application Domain of Formal Methods

Chair: Christoph Scholl, University of Freiburg, DE; Gianpiero Cabodi, Politecnico di Torino, IT

[305] [306] Using MaxBMC for Pareto-Optimal Circuit Initialization: Sven Reimer, Matthias Sauer, Tobias Schubert, Bernd Becker
[307] [308] Partial Witnesses from Preprocessed Quantified Boolean Formulas: Martina Seidl, Robert Könighofer
[309] [310] Equivalence Checking for Function Pipelining in Behavioral Synthesis: Kecheng Hao, Sandip Ray, Fei Xie
[311] [312] Towards the Formal Analysis of Microresonators Based Photonic Systems: Umair Siddique, Sofiène Tahar
[313] [314] SKETCHILOG: Sketching Combinational Circuits: Andrew Becker, David Novo, Paolo Ienne
[315] [316] Towards Verifying Determinism of SystemC Designs: Hoang M. Le, Rolf Drechsler

6.6 Model-Based Design and Hardware/Software Interfaces

Chairs: Wang Wang Yi, Uppsala University, SE; Oliver Bringmann, University of Tübingen, DE

[317] [318] Library-Based Scalable Refinement Checking for Contract-Based Design: Antonio Iannopollo, Pierluigi Nuzzo, Stavros Tripakis, Alberto Sangiovanni-Vincentelli
[319] [320] Isochronous Networks by Construction: Yu Bai, Klaus Schneider
[321] [322] Tightly-Coupled Hardware Support to Dynamic Parallelism Acceleration in Embedded Shared Memory Clusters: Paolo Burgio, Giuseppe Tagliavini, Francesco Conti, Andrea Marongiu, Luca Benini
[323] [324] p-OFTL: An Object-based Semantic-aware Parallel Flash Translation Layer: Wei Wang, Youyou Lu, Jiwu Shu
[325] [326] Using Guided Local Search for Adaptive Resource Reservation in Large-scale Embedded Systems: Timon D. ter Braak
[327] [328] Accelerating Graph Computation with Racetrack Memory and Pointer-Assisted Graph Representation: Eunhyek Park, Sungjoo Yoo, Sunggu Lee, Helen Li

6.7 Hardening Approaches at Different Design Levels

Chairs: Lorena Anghel, TIMA, FR; Jaume Abella, BSC, ES

[329] [330] Nostradamus: Low-Cost Hardware-Only Error Detection for Processor Cores: Ralph Nathan, Daniel J. Sorin
[331] [332] Word-Line Power Supply Selector for Stability Improvement of Embedded SRAMs in High Reliability Applications: B. Alorda, C. Carmona, S. Bota
[333] [334] A High Performance SEU-Tolerant Latch for Nanoscale CMOS Technology: Zhengfeng Huang
[335] [336] A Low-Cost Radiation Hardened Flip-flop: Yang Lin, Mark Zwolinski, Basel Halak
[337] [338] PSP-Cache: A Low-Cost Fault-Tolerant Cache Memory Architecture: Hamed Farbeh, Seyed Ghassem Miremadi
[339] [340] A Hybrid Non-Volatile SRAM Cell with Concurrent SEU Detection and Correction: Pilin Junsangsri, Fabrizio Lombardi, Jie Han

7.0 Special Day Keynote

[341] [342] The Connected Car and Its Implication to the Automotive Chip Roadmap: Michael Bolle, Robert Bosch GmbH, DE

7.2 Embedded Tutorial: Cross Layer Resiliency in Real World

Organizer: Vikas Chandra, ARM, US
Chairs: Yanjing Li, Intel, US; Ulf Schlichtmann, TUM, DE

[343] [344] Cross Layer Resiliency in Real World: Vikas Chandra

7.3 Low Power Methods and Multicore Architectures for Mobile Health Applications

Chairs: Ashoka Sathanur, Philips, NL; Giovanni Ansaloni, EPFL, CH

[345] [346] Hardware/Software Approach for Code Synchronization in Low-Power Multi-Core Sensor Nodes: Rubén Braojos, Ahmed Dogan, Ivan Beretta, Giovanni Ansaloni, David Atienza
[347] [348] Hybrid Memory Architecture for Voltage Scaling in Ultra-Low Power Multi-Core Biomedical Processors: Daniele Bortolotti, Andrea Bartolini, Christian Weis, Davide Rossi, Luca Benini
[349] [350] Context Aware Power Management for Motion-sensing Body Area Network Nodes: Filippo Casamassima, Elisabetta Farella, Luca Benini
[351] [352] A Quality-Scalable and Energy-Efficient Approach for Spectral Analysis of Heart Rate Variability: Georgios Karakonstantis, Aviinaash Sankaranarayanan, Mohamed M. Sabry, David Atienza, Andreas Burg
[353] [354] Battery Aware Stochastic QoS Boosting in Mobile Computing Devices: Hao Shen, Qiuwen Chen, Qinru Qiu

7.4 Runtime Memory Optimization and GPU/Manycore Architectures

Chairs: Alberto Nannarelli, DTU Copenhagen, DK; Alberto Macii, PoliTo Torino, IT

[355] [356] Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization: Karthik Chandrasekar, Sven Goossens, Christian Weis, Martijn Koedam, Benny Akesson, Norbert Wehn, Kees Goossens
[357] [358] Cache Aging Reduction with Improved Performance Using Dynamically Re-sizable Cache: Haroon Mahmood, Massimo Poncino, Enrico Macii
[359] [360] On GPU Bus Power Reduction with 3D IC Technologies: Young-Joon Lee and Sung Kyu Lim
[361] [362] Process Variation-Aware Workload Partitioning Algorithms for GPUs Supporting Spatial-Multitasking: Paula Aguilera, Jungseob Lee, Amin Farmahini-Farahani, Katherine Morrow, Michael Schulte, Nam Sung Kim
[363] [364] A Thermal Resilient Integration of Many-core Microprocessors and Main Memory by 2.5D TSI I/Os: Sih-Sian Wu, Kanwen Wang, Sai Manoj P. D., Tsung-Yi Ho, Mingbin Yu, Hao Yu
[365] [366] Leveraging On-Chip Networks for Efficient Prediction on Multicore Coherence: Libo Huang
[367] [368] An Adaptive Memory Interface Controller for Improving Bandwidth Utilization of Hybrid and Reconfigurable Systems: Vito Giovanni Castellana, Antonino Tumeo, Fabrizio Ferrandi

7.5 Emerging Memory Technologies

Chairs: Aida Todri, CNRS .FR; Lars Bauer, KIT, DE

[369] [370] Asynchronous Asymmetrical Write Termination (AAWT) for a Low Power STT-MRAM: Rajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril, Mehdi B. Tahoori
[371] [372] Write-Once-Memory-Code Phase Change Memory: Jiayin Li, Kartik Mohanram
[373] [374] Improving STT-MRAM Density through Multibit Error Correction: Brandon Del Bel, Jongyeon Kim, Chris H. Kim, Sachin S. Sapatnekar
[375] [376] Energy Efficient In-Memory AES Encryption Based on Nonvolatile Domain-wall Nanowire: Yuhao Wang, Hao Yu, Dennis Sylvester, Pingfan Kong
[377] [378] ICE: Inline Calibration for Memristor Crossbar-based Computing Engine: Boxun Li, Yu Wang, Yiran Chen, Hai (Helen) Li, Huazhong Yang
[379] [380] Complementary Resistive Switch Based Stateful Logic Operations Using Material Implication: Yuanfan Yang, Jimson Mathew, Dhiraj K Pradhan, Marco Ottavi, Salvatore Pontarelli

7.6 Performance and Timing Analysis

Chairs: Wang Wang Yi, Uppsala University, SE Petru Petru Eles, Linköping University, SE

[381] [382] Scalability Bottlenecks Discovery in MPSoC Platforms Using Data Mining on Simulation Traces: Sofiane Lagraa, Alexandre Termier, Frédéric Pétrot
[383] [384] Computing a Language-Based Guarantee for Timing Properties of Cyber-Physical Systems: Neil Dhruva, Pratyush Kumar, Georgia Giannopoulou, Lothar Thiele
[385] [386] Resource Optimization for CSDF-modeled Streaming Applications with Latency Constraints: Di Liu, Jelena Spasic, Jiali Teddy Zhai, Todor Stefanov, Gang Chen
[387] [388] A Layered Approach for Testing Timing in the Model-Based Implementation: BaekGyu Kim, Hyeon I Hwang, Taejoon Park, Sang H. Son, Insup Lee
[389] [390] Model-based Protocol Log Generation for Testing a Telecommunication Test Harness Using CLP: Kenneth Balck, Olga Grinchtein, Justin Pearson
[391] [392] Time-Decoupled Parallel SystemC Simulation: Jan Henrik Weinstock, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Laura Tosoratto
[393] [394] A Unified Methodology for a Fast Benchmarking of Parallel Architecture: Alexandre Guerre, Jean-Thomas Acquaviva, Yves Lhuillier

7.7 Design-for-Test and Test Access

Chairs: Erik Jan Marinissen, IMEC, BE; Hans-Joachim Wunderlich, Univ. of Stuttgart, DE

[395] [396] Bit-Flipping Scan - A Unified Architecture for Fault Tolerance and Offline Test: Michael E. Imhof, Hans-Joachim Wunderlich
[397] [398] Testing PUF-Based Secure Key Storage Circuits: Mafalda Cortez, Gijs Roelofs, Said Hamdioui, Giorgio Di Natale
[399] [400] Making it Harder to Unlock an LSIB: Honeytraps and Misdirection in a P1687 Network: Adam Zygmontowicz, Jennifer Dworak, Al Crouch, John Potter
[401] [402] Co-Optimization of Memory BIST Grouping, Test Scheduling, and Logic Placement: Andrew B. Kahng, Ilgweon Kang

8.1 System Simulation and Virtual Prototyping

Organizer: Johannes Stahl, Synopsys, US; Chair: Johannes Stahl, Synopsys, US

[403] [404] Power Modeling and Analysis in Early Design Phases: Bernhard Fischer, Christian Cech, Hannes Muhr
[405] [406] System-level Design Methodology Enabling Fast Development of Baseband MP-SoC for 4G Small Cell Base Station: Shan Tang, Ziyuan Zhu, Yongtao Su
[407] [408] Virtual Prototype Life Cycle in Automotive Applications: Manfred Thanner

8.2 Hot Topic: Near Threshold Computing (NTC)

Organizer: Michael Huebner, Ruhr-University Bochum, DE
Chair: Michael Huebner, Ruhr-University Bochum, DE

[409] [410] Extreme-Scale Computer Architecture: Energy Efficiency from the Ground up: Josep Torrellas
[411] [412] Voltage Island Management in Near Threshold Manycore Architectures to Mitigate Dark Silicon: Cristina Silvano, Gianluca Palermo, Sotirios Xydis, Ioannis Stamelakos
[413] [414] Resolving the Memory Bottleneck for Single Supply Near-Threshold Computing: Tobias Gemmeke, Mohamed M. Sabry, Jan Stuijt, Praveen Raghavan, Francky Catthoor, David Atienza

8.3 Physical Attacks and Countermeasures

Chairs: Francesco Regazzoni, Alari, CH ;Shivam Bhasin, Telecom Paristech, FR

[415] [416] Efficiency of a Glitch Detector against Electromagnetic Fault Injection: Loic Zussa, Amine Dehbaoui, Karim Tobich, Jean-Max Dutertre, Philippe Maurine, Ludovic Guillaume-Sage, Jessy Clediere, Assia Tria
[417] [418] Analyzing and Eliminating the Causes of Fault Sensitivity Analysis: Nahid Farhady Ghalaty, Aydin Aysu, Patrick Schaumont
[419] [420] A Smaller and Faster Variant of RSM: Noritaka Yamashita, Kazuhiko Minematsu, Toshihiko Okamura, Yukiyasu Tsunoo
[421] [422] A Multiple Fault Injection Methodology Based on Cone Partitioning towards RTL Modeling of Laser Attacks: Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle

8.4 Efficient Designs for Telecom and Financial Applications

Chair: Sergio Saponara, University of Pisa, IT; Amer Baghdadi, Telecom Bretagne, FR

[423] [424] Energy Efficient MIMO Processing: A Case Study of Opportunistic Run-Time Approximations: David Novo, Nazanin Farahpour, Paolo Ienne, Ubaid Ahmad, Francky Catthoor
[425] [426] Energy-Efficient FPGA Implementation for Binomial Option Pricing Using OpenCL: Valentin Mena Morales, Pierre-Henri Horrein, Amer Baghdadi, Erik Hochapfel, Sandrine Vaton
[427] [428] Hardware Implementation of a Reed-Solomon Soft Decoder Based on Information Set Decoding: Stefan Scholl, Norbert Wehn
[429] [430] Ambient Variation-tolerant and Inter Components Aware Thermal Management for Mobile System on Chips: Francesco Paterna, Joe Zanotelli, Tajana Simunic Rosing
[431] [432] Energy Efficient Data Flow Transformation for Givens Rotation Based QR Decomposition: Namita Sharma, Preeti Ranjan Panda, Min Li, Prashant Agrawal, Francky Catthoor
[433] [434] Mode-Controlled Dataflow Based Modeling & Analysis of a 4G-LTE Receiver: Hrishikesh Salunkhe, Orlando Moreira, Kees van Berkel

8.5 Modeling & Specification

Chairs: Wolfgang Mueller, University of Paderborn, DE; Francois PECHEUX, UPMC, FR

[435] [436] An Activity-Sensitive Contention Delay Model for Highly Efficient Deterministic Full-System Simulations: Shu-Yung Chen, Chien-Hao Chen, Ren-Song Tsay
[437] [438] Automatic Specification Granularity Tuning for Design Space Exploration: Jiaxing Zhang, Gunar Schirner
[439] [440] EDT: A Specification Notation for Reactive Systems: R. Venkatesh, Ulka Shrotri, G. Murali Krishna, Supriya Agrawal
[441] [442] Model-Based Actor Multiplexing with Application to Complex Communication Protocols: Christian Zebelein, Christian Haubelt, Joachim Falk, Tobias Schwarzer, Jürgen Teich
[443] [444] A Novel Model for System-Level Decision Making with Combined ASP and SMT Solving: Alexander Biewer, Jens Gladigau, Christian Haubelt
[445] [446] DeSpErate: Speeding-up Design Space Exploration by Using Predictive Simulation Scheduling: Giovanni Mariani, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano

8.6 Mapping and Scheduling for Many-Core Embedded Systems

Chairs: Marc Geilen, Eindhoven University of Technology, NL; Sébastien Le Beux, Ecole Centrale de Lyon, FR

[447] [448] Software Architecture of High Efficiency Video Coding for Many-Core Systems with Power-Efficient Workload Balancing: Muhammad Usman Karim Khan, Muhammad Shafique, Jörg Henkel
[449] [450] GPU-EvR: Run-time Event Based Real-time Scheduling Framework on GPGPU Platform: Haeseung Lee, Mohammad Abdullah Al Faruque
[451] [452] Multi-Objective Distributed Run-time Resource Management for Many-Cores: Stefan Wildermann, Michael Glaβ, Jürgen Teich
[453] [454] CoMik: A Predictable and Cycle-Accurately Composable Real-Time Microkernel: Andrew Nelson, Ashkan Beyranvand Nejad, Anca Molnos, Martijn Koedam, Kees Goossens
[455] [456] Utilization-aware Load Balancing for the Energy Efficient Operation on the big.LITTLE Processor: Myungsun Kim, Kibeom Kim, James R. Geraci, Seongsoo Hong
[457] [458] hevcDTM: Application-Driven Dynamic Thermal Management for High Efficiency Video Coding: Daniel Palomino, Muhammad Shafique, Hussam Amrouch, Altamiro Susin, Jörg Henkel
[459] [460] Improving Efficiency of Extensible Processors by Using Approximate Custom Instructions: Mehdi Kamal, Amin Ghasemazar, Ali Afzali-Kusha, Massoud Pedram

8.7 Performance Modeling and Delay Test

Chairs: Robert Aitken, ARM, US Mehdi Tahoori, KIT, DE

[461] [462] Efficient Performance Estimation with Very Small Sample Size via Physical Subspace Projection and Maximum A Posteriori Estimation: Li Yu, Sharad Saxena, Christopher Hess, Ibrahim (Abe) M. Elfadel, Dimitri Antoniadis, Duane Boning
[463] [464] Joint Virtual Probe: Joint Exploration of Multiple Test Items' Spatial Patterns for Efficient Silicon Characterization and Test Prediction: Shuangyue Zhang, Fan Lin, Chun-Kai Hsu, Kwang-Ting Cheng, Hong Wang
[465] [466] Substituting Transition Faults with Path Delay Faults as a Basic Delay Fault Model: Irith Pomeranz
[467] [468] Standard Cell Library Tuning for Variability Tolerant Designs: Sebastien Fabrie, Juan Diego Echeverri, Maarten Vertregt, José Pineda de Gyvez
[469] [470] Probabilistic Standard Cell Modeling Considering Non-Gaussian Parameters and Correlations: André Lange, Christoph Sohrmann, Roland Jancke, Joachim Haase, Ingolf Lorenz, Ulf Schlichtmann

8.8 Hot Topic: Beyond CMOS Ultra-low-power Computing

Organizer: Saibal Mukhopadhyay, Georgia Institute of Technology, US
Chairs: Arijit Raychowdhury, Georgia Institute of Technology, US; Saibal Mukhopadhyay, Georgia Institute of Technology, US

[471] [472] Ultra-low Power Electronics with Si/Ge Tunnel FET: Amit Ranjan Trivedi, Mohammad Faisal Amir, Saibal Mukhopadhyay
[473] [474] Brain-Inspired Computing with Spin Torque Devices: Kaushik Roy, Mrigank Sharad, Deliang Fan, Karthik Yogendra
[475] [476] Toward Ultralow-Power Computing at Exteme with Silicon Carbide (SiC) Nanoelectromechanical Logic: Swarup Bhunia, Vaishnavi Ranganathan, Tina He, Srihari Rajgopal, Rui Yang, Mehran Mehregany, Philip X.-L. Feng

9.1 Hot Topic: CMOS Scaling - from Evolutionary to Revolutionary Computing

Organizers: Thomas Mikolajick, NamLab gGmbH, DE; Ian O'Connor, Lyon Institute of Nanotechnology, FR
Chairs: Thomas Mikolajick, NamLab gGmbH, DE; Ian O'Connor, Lyon Institute of Nanotechnology, FR

[477] [478] III-V Semiconductor Nanowires for Future Devices: H. Schmid, B.M. Borg, K. Moselund, P. Das Kunungo, G. Signorello, S. Karg, P. Mensch, V. Schmidt, H. Riel
[479] [480] Advanced System on a Chip Design Based on Controllable-Polarity FETs: Pierre-Emmanuel Gaillardon, Luca Amaru, Jian Zhang, Giovanni De Micheli
[481] [482] Reconfigurable Silicon Nanowire Devices and Circuits: Opportunities and Challenges: Walter M. Weber, Jens Trommer, Matthias Grube, André Heinzig, Markus König, Thomas Mikolajick
[483] [484] Advancing CMOS with Carbon Electronics: Franz Kreupl

9.2 Low-Cost, High-Performance NoCs

Chairs: Kees Goossens, Eindhoven University, NL; Luca Ramini, University of Ferrara, IT

[485] [486] Application Mapping for Express Channel-Based Networks-on-Chip: Di Zhu, Lizhong Chen, Siyu Yue, Massoud Pedram
[487] [488] Parallel Probe Based Dynamic Connection Setup in TDM NoCs: Shaoteng Liu, Axel Jantsch, Zhonghai Lu
[489] [490] ElastiStore: An Elastic Buffer Architecture for Network-on-Chip Routers: I. Seitanidis, A. Psarras, G. Dimitrakopoulos, C. Nicopoulos
[491] [492] Dynamic Construction of Circuits for Reactive Traffic in Homogeneous CMPs: Marta Ortín, Darío Suárez, María Villarroya, Cruz Izu, Víctor Viñals
[493] [494] Improving Hamiltonian-based Routing Methods for On-chip Networks: A Turn Model Approach: Poona Bahrebar, Dirk Stroobandt

9.3 Hardware Implementations for Data Security

Chairs: Viktor Fischer, St Etienne, FR; Filippo Melzani, STMicroelectronics, IT

[495] [496] Embedded Reconfigurable Logic for ASIC Design Obfuscation against Supply Chain Attacks: Bao Liu, Brandon Wang
[497] [498] A Minimalist Approach to Remote Attestation: Aurélien Francillon, Quan Nguyen, Kasper B. Rasmussen, Gene Tsudik
[499] [500] Multi Resolution Touch Panel with Built-in Fingerprint Sensing Support: Pranav Koundinya, Sandhya Theril, Tao Feng, Varun Prakash, Jiming Bao, Weidong Shi
[501] [502] HEROIC: Homomorphically EncRypted One Instruction Computer: Nektarios Georgios Tsoutsos, Michail Maniatakos
[503] [504] EDA Tools Trust Evaluation through Security Property Proofs: Yier Jin

9.4 Timing challenges in validation

Chairs: Elena Ioana Vatajelu, Politecnico di Torino, IT; Mark Zwolinski, University of Southampton, UK

[505] [506] Fast STA Prediction-based Gate-level Timing Simulation: Tariq B. Ahmad, Maciej J. Ciesielski
[507] [508] A Cross-Level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors: V. Guarnieri, M. Petricca, A. Sassone, S. Vinco, N. Bombieri, F. Fummi, E. Macii, M. Poncino
[509] [510] Empowering Study of Delay Bound Tightness with Simulated Annealing: Xueqian Zhao, Zhonghai Lu
[511] [512] Analysis and Evaluation of Per-Flow Delay Bound for Multiplexing Models: Yanchen Long, Zhonghai Lu, Xiaolang Yan

9.5 Hot Topic: Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test

Organizers: Ulf Schlichtmann, Technische Universität München, DE; Andreas Herkersdorf, Technische Universität München, DE
Chairs: Nikil Dutt, University of California, Irvine, US; Mehdi Tahoori, Karlsruhe Institute of Technology, DE

[513] [514] Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test: Ulf Schlichtmann, Veit B. Kleeberger, Jacob A. Abraham, Adrian Evans, Christina Gimmler-Dumont, Michael Glaβ, Andreas Herkersdorf, Sani R. Nassif, Norbert Wehn

9.6 Schedulability Analysis

Chair: Rob Davis, University of York, UK; Giuseppe Lipari, ENS - Cachan, FR

[515] [516] Rate-Adaptive Tasks: Model, Analysis, and Design Issues: Giorgio C. Buttazzo, Enrico Bini, Darren Buttle
[517] [518] Acceptance and Random Generation of Event Sequences under Real Time Calculus Constraints: Kajori Banerjee, Pallab Dasgupta
[519] [520] General and Efficient Response Time Analysis for EDF Scheduling: Nan Guan, Wang Yi
[521] [522] The Schedulability Region of Two-Level Mixed-Criticality Systems Based on EDF-VD: Dirk Müller, Alejandro Masrur

9.7 Timing Analysis and Cell Design

Chairs: Jose Monteiro, INESC-ID / Tecnico, ULisboa, PT; Elena Dubrova, Royal Institute of Technology, SE

[523] [524] Facilitating Timing Debug by Logic Path Correspondence: Oshri Adler, Eli Arbel, Ilia Averbouch, Ilan Beer, Inna Grijnevitch
[525] [526] Statistical Static Timing Analysis Using a Skew-Normal Canonical Delay Model: Vijaykumar M, V Vasudevan
[527] [528] Leakage-Power-Aware Clock Period Minimization: Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh
[529] [530] A Deep Learning Methodology to Proliferate Golden Signoff Timing: Seung-Soo Han, Andrew B. Kahng, Siddhartha Nath, Ashok S. Vydyanathan
[531] [532] Aging-aware Standard Cell Library Design: Saman Kiamehr, Farshad Firouzi, Mojtaba Ebrahimi, Mehdi B. Tahoori
[533] [534] Pass-XNOR Logic: A New Logic Style for P-N Junction Based Graphene Circuits: Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
[535] [536] Mixed Allocation of Adjustable Delay Buffers Combined with Buffer Sizing in Clock Tree Synthesis of Multiple Power Mode Designs: Kitae Park, Geunho Kim, Taewhan Kim

9.8 Embedded Tutorial: Memcomputing: The Cape of Good Hope

Organizers: Yiyu Shi, Missouri University of Science & Technology, US; Hung-Ming Chen, National Chiao Tung University,Taiwan
Chairs: Yiyu Shi, Missouri University of Science & Technology, US; Hung-Ming Chen, National Chiao Tung University,Taiwan, Taiwan

[537] [538] Memcomputing: The Cape of Good Hope: Yiyu Shi, Hung-Ming Chen
[539] [540] MSim: A General Cycle Accurate Simulation Platform for Memcomputing Studies: Chun Zhang, Peng Deng, Hui Geng, Jianming Liu, Qi Zhu, Jinjun Xiong, Yiyu Shi
[541] [542] Energy-Efficient Hardware Acceleration through Computing in the Memory: Somnath Paul, Robert Karam, Swarup Bhunia, Ruchir Puri

10.1 Hot Topic: Memories Today and Tomorrow

Organizers: Thomas Mikolajick, NamLab gGmbH, DE; Ian O'Connor, Lyon Institute of Nanotechnology, FR
Chairs: Ian O'Connor, Lyon Institute of Nanotechnology, FR; Thomas Mikolajick, NamLab gGmbH, DE

[543] [544] Exploring the Limits of Phase Change Memories: Matthias Wuttig
[545] [546] Magnetic Memories: From DRAM Replacement to Ultra Low Power Logic Chips: G. Prenat, G. Di Pendina, C. Layer, O. Goncalves, K. Jaber, B. Dieny, R. Sousa, I.L. Prejbeanu, J.P. Nozieres
[547] [548] Resistive Memories: Which Applications?: Fabien Clermidy, Natalija Jovanovic, Santhosh Onkaraiah, Houcine Oucheikh, Olivier Thomas, Ogun Turkyilmaz, Elisa Vianello, Jean-Michel Portal, Marc Bocquet
[549] [550] Thinfilm Printed Ferro-Electric Memories and Integrated Products: Christer Karlsson, Peter Fischer

10.2 Wireless NoCs

Chairs: Giorgos Dimitrakopoulos, Democritus University of Thrace, GR; Valeria Bertacco, University of Michigan, US

[551] [552] An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs: Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania
[553] [554] Performance Evaluation of Wireless NoCs in Presence of Irregular Network Routing Strategies: Paul Wettin, Jacob Murray, Ryan Kim, Xinmin Yu, Partha Pratim Pande, Deukhyoun Heo
[555] [556] Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips: Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano
[557] [558] Hybrid Wire-Surface Wave Architecture for One-to-Many Communication in Network-on-Chip: Ammar Karkar, Nizar Dahir, Ra'ed Al-Dujaily, Kenneth Tong, Terrence Mak, Alex Yakovlev
[559] [560] Failure Analysis of a Network-on-Chip for Real-Time Mixed-Critical Systems: Eberle A Rambo, Alexander Tschiene, Jonas Diemer, Leonie Ahrendts, Rolf Ernst

10.3 Green Computing Systems

Chairs: Ayse Coskun, Boston University, US; Martino Ruggiero, University of Bologna, IT

[561] [562] Global Fan Speed Control Considering Non-Ideal Temperature Measurements in Enterprise Servers: Jungsoo Kim, Mohamed M. Sabry, David Atienza, Kalyan Vaidyanathan, Kenny Gross
[563] [564] Unveiling Eurora - Thermal and Power Characterization of the Most Energy-Efficient Supercomputer in the World: Andrea Bartolini, Matteo Cacciari, Carlo Cavazzoni, Giampietro Tecchiolli, Luca Benini
[565] [566] Contention Aware Frequency Scaling on CMPs with Guaranteed Quality of Service: Hao Shen, Qinru Qiu
[567] [568] Concurrent Placement, Capacity Provisioning, and Request Flow Control for a Distributed Cloud Infrastructure: Shuang Chen, Yanzhi Wang, Massoud Pedram
[569] [570] COOLIP: Simple yet Effective Job Allocation for Distributed Thermally-Throttled Processors: Pratyush Kumar, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele
[571] [572] Energy Optimization in 3D MPSoCs with Wide-I/O DRAM Using Temperature Variation Aware Bank-wise Refresh: Mohammadsadegh Sadri, Matthias Jung, Christian Weis, Norbert Wehn, Luca Benini

10.4 System-level Evaluation

Chairs: Pablo Sanchez, University of Cantabria, ES Florian Letombe, Synopsys, FR

[573] [574] Automatic Detection of Concurrency Bugs through Event Ordering Constraints: Luis Gabriel Murillo, Simon Wawroschek, Jeronimo Castrillon, Rainer Leupers, Gerd Ascheid
[575] [576] Hardware-Based Fast Exploration of Cache Hierarchies in Application Specific MPSoCs: Isuru Nawinne, Josef Schneider, Haris Javaid, Sri Parameswaran
[577] [578] SSDExplorer: A Virtual Platform for Fine-Grained Design Space Exploration of Solid State Drives: Lorenzo Zuolo, Cristian Zambelli, Rino Micheloni, Salvatore Galfano, Marco Indaco, Stefano Di Carlo, Paolo Prinetto, Pirero Olivo, Davide Bertozzi
[579] [580] Efficient Simulation and Modelling of Non-rectangular NoC Topologies: Ji Qi, Mark Zwolinski
[581] [582] Moving from Co-Simulation to Simulation for Effective Smart Systems Design: Franco Fummi, Michele Lora, Francesco Stefanni, Dimitrios Trachanis, Jan Vanhese, Sara Vinco

10.5 Analysis of Components and Systems

Chairs: Frank Oppenheimer, OFFIS, DE; Todor Stefanov, Leiden University, NL

[583] [584] May-Happen-in-Parallel Analysis Based on Segment Graphs for Safe ESL Models: Weiwei Chen, Xu Han, Rainer Dömer
[585] [586] Timing Analysis of First-Come First-Served Scheduled Interval-Timed Directed Acyclic Graphs: R.M.W.Frijns, S.Adyanthaya, S.Stuijk, J.P.M.Voeten, M.C.W.Geilen, R.R.H.Schiffelers, H.Corporaal
[587] [588] A Dynamic Computation Method for Fast and Accurate Performance Evaluation of Multi-core Architectures: Sébastien Le Nours, Adam Postula, Neil W. Bergmann
[589] [590] Cross-correlation of Specification and RTL for Soft IP Analysis: Bhanu Singh, Arunprasath Shankar, Francis Wolff, Christos Papachristou, Daniel Weyer, Steve Clay

10.6 Multi-processor and Distributed Systems

Chairs: Orlando Moreira, Ericsson, NL; Benny Akesson, CTU, CZ

[591] [592] Thermal-Aware Frequency Scaling for Adaptive Workloads on Heterogeneous MPSoCs: Heng Yu, Rizwan Syed, Yajun Ha
[593] [594] Partitioned Mixed-Criticality Scheduling on Multiprocessor Platforms: Chuancai Gu, Nan Guan, Qingxu Deng, Wang Yi
[595] [596] Generation of Communication Schedules for Multi-Mode Distributed Real-Time Applications: Akramul Azim, Gonzalo Carvajal, Rodolfo Pellizzoni, Sebastian Fischmeister

10.7 Advances in Synthesis

Chairs: John Hayes, University of Michigan, US; Kim Taemin, Intel Labs, US

[597] [598] Provably Minimal Energy Using Coordinated DVS and Power Gating: Nathaniel A. Conos, Saro Meguerdichian, Foad Dabiri, Miodrag Potkonjak
[599] [600] A Tree Arbiter Cell for High Speed Resource Sharing in Asynchronous Environments: Syed Rameez Naqvi, Andreas Steininger
[601] [602] An Efficient Manipulation Package for Biconditional Binary Decision Diagrams: Luca Amarú, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
[603] [604] Synthesis Algorithm of Parallel Index Generation Units: Yusuke Matsunaga
[605] [606] Automating Data Reuse in High-Level Synthesis: Wim Meeus, Dirk Stroobandt
[607] [608] A Universal Symmetry Detection Algorithm: Peter M. Maurer
[609] [610] Optimization of Design Complexity in Time-Multiplexed Constant Multiplications: Levent Aksoy, Paulo Flores, José Monteiro
[611] [612] Hardware Primitives for the Synthesis of Multithreaded Elastic Systems: G. Dimitrakopoulos, I. Seitanidis, A. Psarras, K. Tsiouris, P. Mattheakis, J. Cortadella

11.0 Special Day Keynote: Organic Electronics - From Lab to Markets

[613] [614] Karl Leo - Technische Universität Dresden, DE

11.1 Embedded Tutorial: Alternatives to CMOS

Organizers: Ian O'Connor, Lyon Institute of Nanotechnology, FR; Thomas Mikolajick, NamLab gGmbH, DE
Chairs: Ian O'Connor, Lyon Institute of Nanotechnology, FR; Thomas Mikolajick, NamLab gGmbH, DE

[615] [616] Spintronics for Low-Power Computing: Yue Zhang, Weisheng Zhao, Jacques-Olivier Klein, Wang Kang, Damien Querlioz, Youguang Zhang, Dafiné Ravelosona, Claude Chappert
[617] [618] CHAMELEON: CHANNEL Efficient Optical Network-on-Chip: Sébastien Le Beux, Hui Li, Ian O'Connor, Kazem Cheshmi, Xuchen Liu, Jelena Trajkovic, Gabriela Nicolescu
[619] [620] Low-Voltage Organic Transistors for Flexible Electronics: Ute Zschieschang, Reinhold Rödel, Ulrike Kraft, Kazuo Takimiya, Tarek Zaki, Florian Letzkus, Jörg Butschke, Harald Richter, Joachim N. Burghartz, Wei Xiong, Boris Murmann, Hagen Klauk

11.2 Transitioning NoC Design Techniques to Future Challenges

Chairs: Masoud Daneshtalab, University of Turku, FI; Hiroki Matsutani, Keio University, JP

[621] [622] Brisk and Limited-Impact NoC Routing Reconfiguration: Doowon Lee, Ritesh Parikh, Valeria Bertacco
[623] [624] Thermal Management of Manycore Systems with Silicon-Photonic Networks: Tiansheng Zhang, José L. Abellán, Ajay Joshi, Ayse K. Coskun
[625] [626] Assessing the Energy Break-Even Point between an Optical NoC Architecture and an Aggressive Electronic Baseline: Luca Ramini, Paolo Grani, Hervé Tatenguem Fankem, Alberto Ghiribaldi, Sandro Bartolini, Davide Bertozzi
[627] [628] DCM: An IP for the Autonomous Control of Optical and Electrical Reconfigurable NoCs.: Wolfgang Büter, Christof Osewold, Daniel Gregorek, Alberto García-Ortiz
[629] [630] Minimally Buffered Single-Cycle Deflection Router: Gnaneswara Rao Jonna, John Jose, Rachana Radhakrishnan, Madhu Mutyam

11.3 Industry Relevant Research and Practice for System Design

Chairs: Emil Matus, Technische Universität Dresden, DE; Norbert Wehn, TU Kaiserslautern. DE

[631] [632] The Metamodeling Approach to System Level Synthesis: Wolfgang Ecker, Michael Velten, Leily Zafari, Ajay Goyal
[633] [634] Logic Synthesis of Low-power ICs with Ultra-wide Voltage and Frequency Scaling: Yu Pu, Juan Echeverri, Maurice Meijer, Jose Pineda de Gyvez
[635] [636] Formal Verification of Taint-propagation Security Properties in a Commercial SoC Design: Pramod Subramanyan, Divya Arora
[637] [638] Early Design Stage Thermal Evaluation and Mitigation: The Locomotiv Architectural Case: Tanguy Sassolas, Chiara Sandionigi, Alexandre Guerre, Alexandre Aminot, Pascal Vivet, Hela Boussetta, Luca Ferro, Nicolas Peltier
[639] [640] Multi-Disciplinary Integrated Design Automation Tool for Automotive Cyber-Physical Systems: Arquimedes Canedo, Mohammad Abdullah Al Faruque, Jan H. Richter
[641] [642] Predictive Parallel Event-driven HDL Simulation with A New Powerful Prediction Strategy: Seiyang Yang, Jaehoon Han, Doowhan Kwak, Namdo Kim, Daeseo Cha, Junhyuck Park, Jay Kim

11.4 Enabling validation on fast platforms

Chairs: Ronny Morad, IBM, IL; Franco Fummi, Universita' di Verona, IT

[643] [644] ArChiVED: Architectural Checking via Event Digests for High Performance Validation: Chang-Hong Hsu, Debapriya Chatterjee, Ronny Morad, Raviv Gal, Valeria Bertacco
[645] [646] Coverage Evaluation of Post-silicon Validation Tests with Virtual Prototypes: Kai Cong, Li Lei, Zhenkun Yang, Fei Xie
[647] [648] Effective Post-Silicon Failure Localization Using Dynamic Program Slicing: Ophir Friedler, Wisam Kadry, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin
[649] [650] Design-for-Debug Routing for FIB Probing: Chia-Yi Lee, Tai-Hung Li, Tai-Chen Chen
[651] [652] Functional Test Generation Guided by Steady-State Probabilities of Abstract Design: Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li
[653] [654] Automated System Testing Using Dynamic and Resource Restricted Clients: Mirko Caspar, Mirko Lippmann, Wolfram Hardt

11.5 Memory Resource Allocation and Scheduling in MPSoC

Chairs: Andreas Herkersdorf, Technische Universität Munchen, DE; Donatella Sciuto, Politecnico di Milano,IT

[655] [656] Scenario-aware Data Placement and Memory Area Allocation for Multi-Processor System-on-Chips with Reconfigurable 3D-stacked SRAMs: Meng-Ling Tsai, Yi-Jung Chen, Yi-Ting Chen, Ru-Hua Chang
[657] [658] Optimized Buffer Allocation in Multicore Platforms: Maximilian Odendahl, Andrés Goens, Rainer Leupers, Gerd Ascheid, Benjamin Ries, Berthold Vöcking, Tomas Henriksson
[659] [660] Memory-Constrained Static Rate-Optimal Scheduling of Synchronous Dataflow Graphs via Retiming: Xue-Yang Zhu, Marc Geilen, Twan Basten, Sander Stuijk
[661] [662] A Constraint-Based Design Space Exploration Framework for Real-Time Applications on MPSoCs: Kathrin Rosvall, Ingo Sander
[663] [664] Reliability-Aware Mapping Optimization of Multi-Core Systems with Mixed-Criticality: Shin-Haeng Kang, Hoeseok Yang, Sungchan Kim, Iuliana Bacivarov, Soonhoi Ha, Lothar Thiele
[665] [666] From Simulink to NoC-based MPSoC on FPGA: Francesco Robino, Johnny Öberg

11.6 System-Level Thermal Estimation and Management

Chairs: Coskun Ayse, Boston University, US; Wolfgang Nebel, OFFIS, DE

[667] [668] Minimal Sparse Observability of Complex Networks: Application to MPSoC Sensor Placement and Run-time Thermal Estimation & Tracking: Santanu Sarma, Nikil Dutt
[669] [670] mDTM: Multi-Objective Dynamic Thermal Management for On-Chip Systems: Heba Khdr, Thomas Ebi, Muhammad Shafique, Hussam Amrouch, Jörg Henkel
[671] [672] Thermal Management of Batteries Using a Hybrid Supercapacitor Architecture: Donghwa Shin, Massimo Poncino, Enrico Macii
[673] [674] Thermal Analysis and Model Identification Techniques for a Logic + WIDEIO Stacked DRAM Test Chip: Francesco Beneventi, Andrea Bartolini, Pascal Vivet, Denis Dutoit, Luca Benini
[675] [676] Adaptive Power Allocation for Many-core Systems Inspired from Multiagent Auction Model: Xiaohang Wang, Baoxin Zhao, Terrence Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Maurizio Palesi
[677] [678] Unified, Ultra Compact, Quadratic Power Proxies for Multi-Core Processors: Muhammad Yasin, Anas Shahrour, Ibrahim (Abe) M. Elfadel

11.7 Power and Emerging Technologies in Reconfigurable Computing

Chairs: Diana Goehringer, Ruhr-University Bochum (RUB), DE; Fabrizio Ferrandi, Politecnico di Milano, IT

[679] [680] Exploiting STT-NV Technology for Reconfigurable, High Performance, Low Power, and Low Temperature Functional Unit Design: Adarsh Reddy Ashammagari, Hamid Mahmoodi, Houman Homayoun
[681] [682] A Power-Efficient Reconfigurable Architecture Using PCM Configuration Technology: Ali Ahari, Hossein Asadi, Behnam Khaleghi, Mehdi B. Tahoori
[683] [684] Extending Lifetime of Battery-Powered Coarse-Grained Reconfigurable Computing Platforms: Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei
[685] [686] 3D FPGA Using High-density Interconnect Monolithic Integration: Ogun Turkyilmaz, Gérald Cibrario, Olivier Rozeau, Perrine Batude, Fabien Clermidy
[687] [688] Joint Communication Scheduling and Interconnect Synthesis for FPGA-based Many-Core Systems: Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo
[689] [690] A Novel Embedded System for Vision Tracking: Antonis Nikitakis, Theofilos Paganos, Ioannis Papaefstathiou

11.8 Embedded Tutorial: GPGPUs: How to Combine High Computational Power with High Reliability

Organizesr: Matteo Sonza Reorda, Politecnico di Torino, IT
Chairs: Dimitris Gizopoulos, University of Athens, GR; Rob Aitken, ARM, US

[691] [692] GPGPUs: How to Combine High Computational Power with High Reliability: L. Bautista Gomez, F. Cappello, L. Carro, N. DeBardeleben, B. Fang, S. Gurumurthi, K. Pattabiraman, P. Rech, M. Sonza Reorda

12.1 Hot Topic: The Future of Interfacing to the Natural World

Organizers: Ian O'Connor, Lyon Institute of Nanotechnology, FR; Thomas Mikolajick, NamLab gGmbH, DE
Chairs: Thomas Mikolajick, NamLab gGmbH, DE; Ian O'Connor, Lyon Institute of Nanotechnology, FR

[693] [694] Integrated Circuits Processing Chemical Information: Prospects and Challenges: A. Richter, A. Voigt, R. Schüffny, S. Henker, M. Völp
[695] [696] Interfacing to Living Cells: Rudy Lauwereins
[697] [698] Video Analytics Using Beyond CMOS Devices: Vijaykrishnan Narayanan, Suman Datta, Gert Cauwenberghs, Don Chiarulli, Steve Levitan, Philip Wong
[699] [700] Energy Efficient Neural Networks for Big Data Analytics: Yu Wang, Boxun Li, Rong Luo, Yiran Chen, Ningyi Xu, Huazhong Yang

12.2 Hot topic: How Secure are PUFs Really? On the Reach and Limits of Recent PUF Attacks

Organizer: Ulrich Rührmair, TU München, DE
Chair: Ulf Schlichtmann, TU München, DE

[701] [702] Special Session: How Secure are PUFs Really? On the Reach and Limits of Recent PUF Attacks: Ulrich Rührmair, Ulf Schlichtmann, Wayne Burleson
[703] [704] PUFs at a Glance: Ulrich Rührmair, Daniel E. Holcomb
[705] [706] PUF Modeling Attacks: An Introduction and Overview: Ulrich Rührmair, Jan Sölter
[707] [708] Hybrid Side-Channel / Machine-Learning Attacks on PUFs: A New Threat?: Xiaolin Xu, Wayne Burleson
[709] [710] Physical Vulnerabilities of Physically Unclonable Functions: Clemens Helfmeier, Christian Boit, Dmitry Nedospasov, Shahin Tajik, Jean-Pierre Seifert
[711] [712] Protocol Attacks on Advanced PUF Protocols and Countermeasures: Marten van Dijk, Ulrich Rührmair
[713] [714] Quo Vadis, PUF? Trends and Challenges of Emerging Physical-Disorder Based Security: Masoud Rostami, James B. Wendt, Miodrag Potkonjak, Farinaz Koushanfar

12.3 Multimedia Systems

Chairs: Theocharides Theocharis, University of Cyprus, CY; Cristiana Bolchini, Politecnico di Milano, IT

[715] [716] Flexible and Scalable Implementation of H.264/AVC Encoder for Multiple Resolutions Using ASIPs: Hong Chinh Doan, Haris Javaid, Sri Parameswaran
[717] [718] A Flexible ASIP Architecture for Connected Components Labeling in Embedded Vision Applications: Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid, Patrick Sudowe, Bastian Leibe, Tamon Sadasue
[719] [720] Image Progressive Acquisition for Hardware Systems: Jianxiong Liu, Christos Bouganis, Peter Y.K. Cheung
[721] [722] High-Quality Real-Time Hardware Stereo Matching Based on Guided Image Filtering: Christos Ttofis, Theocharis Theocharides

12.4 Physical Aspects

Chair: Carl Sechen, University of Texas at Dallas, US; Jens Lienig, TU Dresden, DE

[723] [724] Optimization of Standard Cell Based Detailed Placement for 16 nm FinFET Process: Yuelin Du, Martin D. F. Wong
[725] [726] Signature Indexing of Design Layouts for Hotspot Detection: Cristian Andrades, M. Andrea Rodríguez, Charles C. Chiang
[727] [728] Metal Layer Planning for Silicon Interposers with Consideration of Routability and Manufacturing Cost: Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang

12.5 System-level Design Space Exploration

Chairs: Frederic Petrot, TIMA, FR; Luciano Lavagno, Politecnico di Torino, IT

[729] [730] Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures: Ulrich Abelein, Alejandro Cook, Piet Engelke, Michael Glaβ, Felix Reimann, Laura Rodríguez Gómez, Thomas Russ, Jürgen Teich, Dominik Ull, Hans-Joachim Wunderlich
[731] [732] ABACUS: A Technique for Automated Behavioral Synthesis of Approximate Computing Circuits: Kumud Nepal, Yueting Li, R. Iris Bahar, Sherief Reda
[733] [734] Automatic Generation of Custom SIMD Instructions for Superword Level Parallelism: Taemin Kim, Yatin Hoskote
[735] [736] System-level Scheduling of Real-time Streaming Applications Using a Semi-partitioned Approach: Emanuele Cannella, Mohamed A. Bamakhrama, Todor Stefanov

12.6 Error Resilience and Power Management

Chairs: William Fornaciari, Politecnico di Milano - DEIB, IT; Kim Gruettner, OFFIS, DE

[737] [738] ASLAN: Synthesis of Approximate Sequential Circuits: Ashish Ranjan, Arnab Raha, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan
[739] [740] VRCon: Dynamic Reconfiguration of Voltage Regulators in a Multicore Platform: Woojoo Lee, Yanzhi Wang, Massoud Pedram
[741] [742] Coarse-grained Bubble Razor to Exploit the Potential of Two-Phase Transparent Latch Designs: Hayoung Kim, Dongyoung Kim, Jae-Joon Kim, Sungjoo Yoo, Sunggu Lee
[743] [744] FEPMA: Fine-Grained Event-Driven Power Meter for Android Smartphones Based on Device Driver Layer Event Monitoring: Kitae Kim, Donghwa Shin, Qing Xie, Yanzhi Wang, Massoud Pedram, Naehyuck Chang

12.7 Built-in Self-test Solutions for Mixed-signal and RF ICs

Chairs: Jacob A. Abraham, University of Texas at Austin, US; Marian Verhelst, KU Leuven, BE

[745] [746] An Analog Non-Volatile Neural Network Platform for Prototyping RF BIST Solutions: Dzmitry Maliuk, Yiorgos Makris
[747] [748] Built-In Self-Test and Characterization of Polar Transmitter Parameters in the Loop-Back Mode: Jae Woong Jeong, Sule Ozev, Shreyas Sen, Vishwanath Natarajan, Mustapha Slamani
[749] [750] A Flexible BIST Strategy for SDR Transmitters: Emanuel Dogaru, Filipe Vinci dos Santos, William Rebernak
[751] [752] Sigma-Delta Testability for Pipeline A/D Converters: Antonio Gines, Gildas Leger

12.8 Panel: Future SoC Verification Methodology: UVM Evolution or Revolution?

Organizer: Alex Goryachev, IBM Research - Haifa, IL
Chair: Rolf Drechsler, University of Bremen/DFKI,DE

[753] [754] Future SoC Verification Methodology: UVM Evolution or Revolution?: Rolf Drechsler, Christophe Chevallaz, Franco Fummi, Alan J. Hu, Ronny Morad, Frank Schirrmeister, Alex Goryachev