DATE 2004 TABLE OF CONTENTS
Sessions:
[Plenary]
[1A]
[1B]
[1C]
[1D]
[1E]
[1F]
[2A]
[2B]
[2C]
[2E]
[2F]
[3A]
[3B]
[3C]
[3E]
[3F]
[4A]
[4B]
[4C]
[4E]
[4F]
[4G]
[5A]
[5B]
[5C]
[5E]
[5F]
[5G]
[IP1]
[IP2]
[IP3]
[6A]
[6B]
[6C]
[6E]
[6F]
[6G]
[7A]
[7B]
[7C]
[7E]
[7F]
[7G]
[8A]
[8B]
[8C]
[8E]
[8G]
[9A]
[9B]
[9C]
[9E]
[9G]
[10A]
[10B]
[10C]
[10E]
[10F]
[10G]
[IP4]
[IP5]
[IP6]
DATE Executive Committee
Technical Program Chairs
Vendors Committee
DATE Sponsors Committee
Technical Program Committee
Reviewers
Foreword
Best Paper Awards
Tutorials
Master Courses
Call for Papers DATE 2005
Volume I
Moderator: J. Figueras, UP Catalunya, ES

Opportunities and Challenges in Building Silicon Products in 65nm and Beyond [p. 2]

G. Spirakis
Moderators: J. Henkel, NEC, US; A. Macii, Politecnico di Torino, IT

FineGrained Dynamic Voltage and Frequency Scaling for Precise Energy and
Performance TradeOff Based on the Ratio of OffChip Access to OnChip Computation Times [p. 4]

K. Choi, R. Soma, and M. Pedram

Hybrid Architectural Dynamic Thermal Management [p. 10]

K. Skadron

ValueConscious Cache: Simple Technique for Reducing Cache Access Power [p. 16]

Y. Chang, C. Yang, and F. Lai

StatePreserving vs. NonStatePreserving Leakage Control in Caches [p. 22]

D. Parikh, K. Sankaranarayanan, Y. Li, K. Skadron, Y. Zhang, and M. Stan
Moderators: A. Veneris, Toronto U, CA; K. Winkelmann, Infineon Technologies, DE

Arithmetic Reasoning in DPLLBased SAT Solving [p. 30]

M. Wedler, D. Stoffel, and W. Kunz

Enhanced Diameter Bounding via Structural Transformation [p. 36]

J. Baumgartner and A. Kuehlmann

Improved Symbolic Simulation by Dynamic Functional Space Partitioning [p. 42]

T. Feng, L. Wang, K. Cheng, and A. Lin
Moderators: S. Kundu, Intel, US; B. Straube, FhG IIS/EAS Dresden, DE

Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults [p. 50]

S. Padmanaban and S. Tragoudas

Level of Similarity: A Metric for Fault Collapsing [p. 56]

I. Pomeranz and S. Reddy

Design of RoutingConstrained Low Power Scan Chains [p. 62]

Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, and A. Virazel

ZSets and ZDetections: Circuit Characteristics that Simplify Fault Diagnosis [p. 68]

I. Pomeranz, S. Venkataraman, S. Reddy, and B. Seshadri
Moderators: A. RodriguezVazquez, IMSECNM, ES; P. Wambacq, IMEC, BE

A 2.7V 350µW 11b Algorithmic AnalogtoDigital Converter with SingleEnded Multiplexed Inputs [p. 76]

A. Nagari and G. Nicollini

Digital Background Gain Error Correction in Pipeline ADCs [p. 82]

A. Ginés, E. Peralías, and A. Rueda

Digital Ground Bounce Reduction by Phase Modulation of the Clock [p. 88]

M. Badaroglu, G. Gielen, H. De Man, P. Wambacq, G. Van Der Plas, and S. Donnay

PseudoRandom Sequence Based Tuning System for ContinuousTime Filters [p. 94]

A. Baschirotto, S. D'Amico, F. Corsi, C. Marzocca, and G. Matarrese
Moderators: J. Teich, ErlangenNuremberg U, DE; P. Cheung, Imperial College London, UK

A Crosstalk Aware Interconnect with Variable Cycle Transmission [p. 102]

L. Li, N. Vijaykrishnan, M. Kandemir, and M. Irwin

Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip [p. 108]

N. Thepayasuwan and A. Doboli

Loop Shifting and Compaction for the HighLevel Synthesis of Designs with Complex Control Flow [p. 114]

S. Gupta, N. Dutt, A. Nicolau, and R. Gupta
Organiser/Moderator: G. Martin, Cadence Berkeley Labs, US; D. Sciuto, Politecnico di Milano
Panellists:
S. Swan, Cadence, US
F. Ghenassia, STMicroelectronics, FR
P. Flake, Synopsys, US
J. Srouji, Intel, Israel
W. Rosenstiel, Tübingen U, DE

SystemC and System Verilog: Where do They Fit? Where are they going? [p. 122]

Moderators: E. Schmidt, Chip Vision Design Systems, DE; C. Guardiani, PDF Solutions, IT

ReConfigurable Bus Encoding Scheme for Reducing Power Consumption of the
Cross Coupling Capacitance for Deep SubMicron Instruction Bus [p. 130]

S. Wong and C. Tsui

Hierarchical Adaptive Dynamic Power Management [p. 136]

Z. Ren, B. Krogh, and R. Marculescu

A SelfTuning Cache Architecture for Embedded Systems [p. 142]

C. Zhang, F. Vahid, and R. Lysecky

Scheduling Reusable Instructions for Power Reduction [p. 148]

J. Hu, N. Vijaykrishnan, S. Kim, M. Kandemir, and M. Irwin
Moderators: R. Drechsler, Bremen U, DE; H. Eveking, TU Darmstadt, DE

Using Counter Example Guided Abstraction Refinement to Find Complex Bugs [p. 156]

P. Bjesse and J. Kukula

CostEfficient Block Verification for a UMTS UpLink ChipRate Coprocessor [p. 162]

G. Fey, D. Stoffel, H. Trylus, and K. Winkelmann

Automatic Verification of Safety and Liveness for XScaleLike Processor Models
Using WEB Refinements [p. 168]

P. Manolios and S. Srinivasan
Moderators: H. Obermeir, Infineon Technologies, DE; M. Hsiao, Virginia Tech., US

A Probabilistic Method for the Computation of Testability of RTL Constructs [p. 176]

J. Fernandes, M. Santos, A. Oliveira, and J. Teixeira

GraphBased Functional Test Program Generation for Pipelined Processors [p. 182]

P. Mishra and N. Dutt

Automatic Generation of Validation Stimuli for ApplicationSpecific Processors [p. 188]

O. Goloubeva, M. Sonza Reorda, and M. Violante

Efficient Static Compaction of Test Sequence Sets through the Application of Set Covering Techniques [p. 194]

M. Dimopoulos and P. Linardis
Moderators: R. Bergamaschi, IBM TJ Watson Res. Center, US; R. Hermida, Madrid Complutense U, ES

Data Reuse Analysis Technique for SoftwareControlled Memory Hierarchies [p. 202]

I. Issenin, N. Dutt, E. Brockmeyer, and M. Miranda

Automatic Tuning of TwoLevel Caches to Embedded Applications [p. 208]

A. GordonRoss, F. Vahid, and N. Dutt

Low StaticPower FrequentValue Data Caches [p. 214]

C. Zhang, J. Yang, and F. Vahid

Using a Victim Buffer in an ApplicationSpecific Memory Hierarchy [p. 220]

C. Zhang and F. Vahid
Organiser/Moderator: M. Renaudin, TIMA Laboratory, FR; F. Bouesse, TIMA Laboratory, FR
Speakers:
P. Proust, Gemplus Corporate R&D Security Technologies, FR
J. Tual, Axalto  Schlumberger, FR
L. Sourgen, STMicroelectronics, FR
F. Germain, DCSSI  French Government Service on the Security of Information Systems, FR

High Security Smartcards [p. 228]

Moderators: M. Miranda, IMEC, BE; W. Nebel, OFFIS, DE

EnergyAware Communication and Task Scheduling for NetworkonChip Architectures
Under RealTime Constraints [p. 234]

J. Hu and R. Marculescu

A Low Cost IndividualWell Adaptive Body Bias (IWABB) Scheme for Leakage Power
Reduction and Performance Enhancement in the Presence of IntraDie Variations [p. 240]

T. Chen and J. Gregg

A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation [p. 246]

K. Tiri and I. Verbauwhede

Power Minimization in a Backlit TFTLCD Display by Concurrent Brightness and Contrast Scaling [p. 252]

W. Cheng, Y. Hou, and M. Pedram
Moderators: P. Bjesse, Synopsys, US; G. Cabodi, Politecnico di Torino, IT

Managing Don't Cares in Boolean Satisfiability [p. 260]

S. Safarpour, A. Veneris, R. Drechsler, and J. Lee

Exploiting Signal Unobservability for Efficient Translation to CNF in Formal
Verification of Microprocessors [p. 266]

M. Velev

A Novel SAT AllSolutions Solver for Efficient Preimage Computation [p. 272]

B. Li, M. Hsiao, and S. Sheng
Moderators: A. Richardson, Lancaster U, UK; F Azais, LIRMM, FR

Efficient Test Strategy for TDMA Power Amplifiers Using Transient Current Measurements:
Uses and Benefits [p. 280]

G. Srinivasan, S. Bhattacharya, A. Chatterjee, and S. Cherubal

Random Jitter Extraction Technique in a MultiGigahertz Signal [p. 286]

C. Ong, D. Hong, K. Cheng, and L. Wang

Low Cost Analog Testing of RF Signal Paths [p. 292]

M. Negreiros, L. Carro, and A. Susin

A Method for Parameter Extraction of Analog SineWave Signals for MixedSignal
BuiltInSelfTest Applications [p. 298]

D. Vázquez, G. Huertas, G. Leger, A. Rueda, and J. Huertas
Moderators: E. de Kock, Philips Research, NL; G. Constantinides, Imperial College, UK

A Novel Implementation of TileBased Address Mapping [p. 306]

S. Hettiaratchi and P. Cheung

Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks [p. 312]

Z. Wang and X. Hu

TimeEnergy Design Space Exploration for MultiLayer Memory Architectures [p. 318]

R. Szymanek, K. Kuchcinski, and F. Catthoor

Breaking InstanceIndependent Symmetries in Exact Graph Coloring [p. 324]

A. Ramani, F. Aloul, I. Markov, and K. Sakallah
Organiser: R. Lauwereins, IMEC, BE
Moderator: R. Wilson, CMP Media, US
Panellists:
K. Maex, IMEC, BE
P. Groeneveld, Magma Design Automation, US
G. Martin, Cadence, US
A. Cuomo, STMicroelectronics, IT
F. Catthoor, IMEC, BE
P. van de Steeg, Philips Semiconductors, NL

How Can System Level Design Solve the
Interconnect Technology Scaling Problem? [p. 332]
Moderators: Y. Mathys, Motorola, FR; H. Hsieh, UC Riverside, US

System Design Using Kahn Process Networks: The Compaan/Laura Approach [p. 340]

E. Deprettere, B. Kienhuis, T. Stefanov, A. Turjan, and C. Zissulescu

Microarchitecture Development via Metropolis Successive Platform Refinement [p. 346]

D. Densmore, A. SangiovanniVincentelli, and S. Rekhi

Fast Exploration of Parameterized Bus Architecture for CommunicationCentric SoC Design [p. 352]

C. Shin, Y. Kim, E. Chung, K. Choi, J. Kong, and S. Eo

SoftContract: An AssertionBased Software Development Process that Enables DesignbyContract [p. 358]

J. Brunel, P. Giusto, M. di Natale, A. Ferrari, and L. Lavagno

A System Level Exploration Platform and Methodology for Network Applications Based on
Configurable Processors [p. 364]

D. Quinn, B. Lavigueur, G. Bois, and M. Aboulhamid
Moderators: S. Singh, Xilinx, US; A. Jantsch, Royal Inst. of Tech., SE

Refinement of MixedSignal Systems with Affine Arithmetic [p. 372]

C. Grimm, W. Heupke, and K. Waldschmidt

SystemLevel Performance Analysis in SystemC [p. 378]

H. Posadas, F. Herrera, P. Sánchez, E. Villar, and F. Blasco

Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks [p. 384]

M. Mousavi, P. Le Guernic, J. Talpin, S. Shukla, and T. Basten

Synchronous Protocol Automata: A Framework for Modelling and Verification of
SoC Communication Architectures [p. 390]

V. D'Silva, S. Ramesh, and A. Sowmya

Aspects of Formal and Graphical Design of a Bus System [p. 396]

T. Seceleanu and T. Westerlund
Moderators: R. Dorsch, IBM Deutschland Entwicklung, DE; E. Larsson, Linköping U, SE

Scan Power Minimization through Stimulus and Response Transformations [p. 404]

O. Sinanoglu and A. Orailoglu

SynchroTokens: Eliminating Nondeterminism to Enable ChipLevel Test of Globally Asynchronous
LocallySynchronous SoC's [p. 410]

M. Heath, W. Burleson, and I. Harris

Wrapper Design for Testing IP Cores with Multiple Clock Domains [p. 416]

Q. Xu and N. Nicolici

Efficient Modular Testing of SOCs Using DualSpeed TAM Architectures [p. 422]

A. Sehgal and K. Chakrabarty

An Arithmetic Structure for Test Data Horizontal Compression [p. 428]

M. Flottes, R. Poirier, and B. Rouzeyre
Moderators: F. Fernandez, IMSECNM, ES; R. Schwencker, Infineon Technologies, DE

A PhaseFrequency Transfer Description of Analog and MixedSignal FrontEnd Architectures for
SystemLevel Design [p. 436]

E. Martens and G. Gielen

Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on
Nonlinear Symbolic Techniques [p. 442]

L. Näthke, V. Burkhay, L. Hedrich, and E. Barke

Performance Modeling of Analog Integrated Circuits Using LeastSquares Support Vector Machines [p. 448]

T. Kiely and G. Gielen

Extended Subspace Identification of Improper Linear Systems [p. 454]

G. Vandersteen, D. Linten, R. Pintelon, and S. Donnay

Identification and Modeling of Nonlinear Dynamic Behavior in Analog Circuits [p. 460]

X. Huang and H. Mantooth
Moderators: G. Koch, Micronas GmbH, DE; C. Passerone, Politecnico di Torino, IT

Exploring Logic Block Granularity for Regular Fabrics [p. 468]

A. Koorapaty, V. Kheterpal, P. Gopalakrishnan, M. Fu, and L. Pileggi

Network Topology Exploration of MeshBased CoarseGrain Reconfigurable Architectures [p. 474]

N. Bansal, S. Gupta, N. Dutt, A. Nicolau, and R. Gupta

A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning [p. 480]

R. Lysecky and F. Vahid

ConfigurationSensitive Process Scheduling for FPGABased Computing Platforms [p. 486]

G. Chen, M. Kandemir, and U. Sezer
Moderators: R. Zafalon, STMicroelectronics, IT; K. Roy, Purdue U, US

Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization [p. 494]

D. Lee, H. Deogun, D. Blaauw, and D. Sylvester

A Scalable ODCBased Algorithm for RTL Insertion of Gated Clocks [p. 500]

P. Babighian, E. Macii, and L. Benini

Impact of Data Transformations on Memory Bank Locality [p. 506]

M. Kandemir

Why Transition Coding for Power Minimization of OnChip Buses Does Not Work [p. 512]

C. Kretzschmar, D. Müller, and A. Nieuwland

OverheadConscious Voltage Selection for Dynamic and Leakage Energy
Reduction of TimeConstrained Systems [p. 518]

A. Andrei, M. Schmitz, P. Eles, Z. Peng, and B. AlHashimi
Moderators: B. Kienhuis, LIACS, Leiden U, NL; F. Petrot, Pierre et Marie Curie U, FR

Dynamic Power Management Using Date Buffers [p. 526]

Y. Lu and L. Cai

Dynamic Memory Management Design Methodology for Reduced Memory.
Footprint in Multimedia and Wireless Network Applications [p. 532]

D. Atienza, J. Mendias, S. Mamagkakis, D. Soudris, and F. Catthoor

HighLevel System Modeling and Architecture Exploration with SystemC on a
Network SoC: S3C2510 Case Study [p. 538]

H. Jang, M. Kang, K. Shim, M. Lee, K. Chae, and K. Lee

A SystemCBased Verification Methodology for Complex Wireless Software IP [p. 544]

G. Post, P. Venkataraghavan, T. Ray, and D. Seetharaman
Moderators: M. Zwolinski, Southampton U, UK; M. Lajolo, NEC Laboratories, US

A New Optimized Implementation of the SystemC Engine Using Acyclic Scheduling [p. 552]

D. Pérez, O. Temam, and G. Mouchard

Stimuli Generation with Late Binding of Values [p. 558]

A. Ziv

Native ISSSystemC Integration for the CoSimulation of MultiProcessor SoC [p. 564]

F. Fummi, S. Martini, G. Perbellini, and M. Poncino

Extraction of Schematic Array Models for Memory Circuits [p. 570]

S. Bose and A. Nandi
Moderators: T. Mak, Intel Corp., US; Y. Tsiatouhas, Ioannina U, GR

Effective SoftwareBased SelfTest Strategies for OnLine Periodic Testing of Embedded Processors [p. 578]

A. Paschalis and D. Gizopoulos

Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAMBased FPGA [p. 584]

M. Bellato, P. Bernardi, A. Candelori, M. Rebaudengo, M. Sonza Reorda, M. Violante,
M. Ceschia, D. Bortolato, A. Paccagnella, and P. Zambolin

Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow [p. 590]

R. Leveugle and A. Ammari

On Concurrent Error Detection with Bounded Latency in FSMs [p. 596]

S. Almukhaizim, Y. Makris, and P. Drineas
Moderators: H. Graeb, TU Munich, DE; G. Vandersteen, IMEC, BE

Fast, LayoutInclusive Analog Circuit Synthesis Using PreCompiled ParasiticAware
Symbolic Performance Models [p. 604]

M. Ranjan, A. Agarwal, H. Sampath, R. Vemuri, W. Verhaegen, and G. Gielen

SensitivityBased Modeling and Methodology for FullChip Substrate Noise Analysis [p. 610]

R. Murgai, S. Reddy, T. Miyoshi, T Horie, and M. Tahoori

SubCALM: A Program for Hierarchical Substrate Coupling Simulation on Floorplan Level [p. 616]

T. Brandtner and R. Weigel

Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming [p. 622]

Y. Zhan and S. Sapatnekar
Moderators: B. Juurlink, TU Delft, NL; R. Leupers, RWTH Aachen, DE

System Design for DSP Applications Using the MASIC Methodology [p. 630]

A. K. Deb, A. Jantsch, and J. Öberg

Flexible Software Protection Using Hardware/Software Codesign Techniques [p. 636]

J. Zambreno, A. Choudhary, R. Simha, and B. Narahari

Interactive Cosimulation with Partial Evaluation [p. 642]

P. Schaumont and I. Verbauwhede

Communication Analysis for System on Chip Design [p. 648]

A. Siebenborn, O. Bringmann, and W. Rosenstiel
Organizer/Moderator: C. Piguet, CSEM, CH
Presenters:
J. Gautier, CEALETI, FR
C. Heer, Infineon Technologies, DE
I. O'Connor, Ecole centrale de Lyon, FR
U. Schlichtmann, Technical University of Munich, DE

Extremely LowPower Logic [p. 656]


Decomposition of Instruction Decoder for Low Power Design [p. 664]

W. Kuo, T. Hwang, and A. Wu

Functional Level Power Analysis: An Efficient Approach for Modeling the
Power Consumption of Complex Processors [p. 666]

J. Laurent, N. Julien, E. Senn, and E. Martin

Formal Verification Coverage: Are the RTLProperties Covering the Design's Architectural Intent? [p. 668]

P. Basu, S. Das, P. Dasgupta, P. Chakrabarti, C. Mohan, and L. Fix

Functional Coverage Metric Generation from Temporal Event Relation Graph [p. 670]

Y. Kwon and C. Kyung

Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits [p. 672]

A. Efthymiou, D. Edwards, and C. Sotiriou

Automatic Synthesis and Simulation of ContinuousTime ΣΔ Modulators [p. 674]

H. Aboushady, L. de Lamarre, N. Beilleau, and M. Louërat

A Methodology for SystemLevel Analog Design Space Exploration [p. 676]

F. De Bernardinis and A. SangiovanniVincentelli

Systematic Design for Optimization of HighResolution Pipelined ADCs [p. 678]

R. Lotfi, M. TaherzadehSani, and O. Shoaei

A Direct Bootstrapped CMOS Large CapacitiveLoad Driver Circuit [p. 680]

J. García, J. MontielNelson, J. Sosa, and H. Navarro

CoProcessor Synthesis: A New Methodology for Embedded Software Acceleration [p. 682]

B. Hounsell and R. Taylor

Behavioural Bitwise Scheduling Based on Computational Effort Balancing [p. 684]

M. Molina, R. RuizSautua, J. Mendías, and R. Hermida

A Tool for Automatic Generation of RTLLevel VHDL Description of RNS FIR Filters [p. 686]

A. Nannarelli, A. Del Re, and M. Re

On Transfer Function and Power Consumption Transient Response [p. 688]

L. Cao

Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits [p. 690]

T. Raudvere, A. Singh, I. Sander, and A. Jantsch

Regression Simulation: Applying PathBased Learning in Delay Test and PostSilicon Validation [p. 692]

L. Wang

A Game Theoretic Approach to Low Energy Wireless Video Streaming [p. 696]

A. Iranli, K. Choi, and M. Pedram

BlockEnabled Memory Macros: Design Space Exploration and ApplicationSpecific Tuning [p. 698]

A. Ivaldi, A. Macii, E. Macii, and L. Benini

Synthesis of Partitioned Shared Memory Architectures for EnergyEfficient MultiProcessor SoC [p. 700]

E. Macii, K. Patel, and M. Poncino

A Low Power Strategy for Future Mobile Terminals [p. 702]

M. Nikitovic and M. Brorsson

A 0.18 µm CMOS Implementation of OnChip Analogue Test Signal Generation from Digital Test Patterns [p. 704]

L. Rolíndez, S. Mir, G. Prenat, and A. Bounceur

A Digital Test for FirstOrder ΣΔModulators [p. 706]

G. Leger and A. Rueda

Trim Bit Setting of Analog Filters Using WaveletBased Supply Current Analysis [p. 708]

S. Bhunia, A. Raychowdhury, and K. Roy

SoC Test Scheduling with PowerTime Tradeoff and Hot Spot Avoidance [p. 710]

J. Chin and M. Nourani

STEPS: Experimenting a New SoftwareBased Strategy for Testing SoCs Containing
P1500Compliant IP Cores [p. 712]

M. Benabdenbi, F. Pêcheux, A. Greiner, M. Tuna and E. Viaud

Are Our Designs for Testability Features Fault Secure? [p. 714]

C. Metra, M. Omaña, and T. Mak

Test Compression and Hardware Decompression for ScanBased SoCs [p. 716]

F. Wolff, C. Papachristou, and D. McIntyre

Concurrent Sizing, Vdd and V_{th} Assignment for LowPower Design [p. 718]

A. Srivastava, D. Sylvester, and D. Blaauw

Sizing and Characterization of LeakageControl Cells for LayoutAware Distributed PowerGating [p. 720]

P. Babighian, E. Macii, and L. Benini

An Asynchronous Synthesis Toolset Using Verilog [p. 724]

F. Burns, D. Shang, A. Koelmans, and A. Yakovlev

Organizing Libraries of DFG Patterns [p. 726]

G. Dittmann

Compositional Memory Systems for Data Intensive Applications [p. 728]

A. Molnos, M. Heijligers, J. Van Eijndhoven, and S. Cotofana

Scalar Metric for Temporal Locality and Estimation of Cache Performance [p. 730]

J. Alakarhu and J. Niittylahti

.NET Framework  A Solution for the Next Generation Tools for SystemLevel Modeling and Simulation [p. 732]

J. Lapalme, E. Aboulhamid, G. Nicolescu, L. Charest, J. David, F. Boyer, and G. Bois

Modeling and Simulating Memory Hierarchies in a PlatformBased Design Methodology [p. 734]

P. Viana, E. Barros, S. Rigo, R. Azevedo, and G. Araújo

Integrating the Synchronous Dataflow Model with UML [p. 736]

P. Green and S. Essa

Design and Behavioral Modeling Tools for Optical NetworkOnChip [p. 738]

M. Brière, L. Carrel, T. Michalke, F. Mieyeville, I. O'Connor, and F. Gaffiot

Hierarchical Modeling and Simulation of Large Analog Circuits [p. 740]

S. Tan, Z. Qi, and H. Li

Efficient MixedDomain Behavioural Modeling of Ferromagnetic Hysteresis Implemented in VHDLAMS [p. 742]

P. Wilson, J. Ross, A. Brown, T. Kazmierski, and J. Baranowski

A Fast Algorithm for Finding Maximal Empty Rectangles for Dynamic FPGA Placement [p. 744]

M. Handa and R. Vemuri

Enhancing Reliability of Operational Interconnections in FPGAs [p. 746]

A. FitFlorea, M. Halas, and F. Kocan

Operating System Support for Interface Virtualization of Reconfigurable Coprocessors [p. 748]

M. Vuletic, L. Righetti, L. Pozzi, and P. Ienne
Volume II
Moderators: R. Ernst, TU Braunschweig, DE; A. Jantsch, Royal Inst. of Tech., SE

Analyzing OnChip Communication in a MPSoC Environment [p. 752]

F. Angiolini, D. Bertozzi, L. Benini, M. Loghi, and R. Zafalon

A Mapping Strategy for ResourceEfficient Network Processing on Multiprocessor SoCs [p. 758]

M. Grünewald, J. Niemann, M. Porrmann, and U. Rückert

CostPerformance TradeOffs in Networks on Chip: A SimulationBased Approach [p. 764]

S. Pestana, E. Rijpkema, A. Radulescu, K. Goossens, and O. Gangwal

A Case Study in NetworksonChip Design for Embedded Video [p. 770]

J. Xu, W. Wolf, T. Lv, J. Henkel, and S. Chakradhar
Moderators: T. Villa, Udine U, IT; T. Shiple, Synopsys, FR

Exploiting Crosstalk to Speed up OnChip Buses [p. 778]

C. Duan and S. Khatri

FalseNoise Analysis for Domino Circuits [p. 784]

A. Glebov, S. Gavrilov, V. Zolotov, M. Becer, C. Oh, and R. Panda

Crosstalk Minimization in Logic Synthesis for PLA [p. 790]

Y. Liu, T. Hwang, and K. Wang

Synthesis for Manufacturability: A Sanity Check [p. 796]

A. Nardi and A. SangiovanniVincentelli
Moderators: G: Carlsson, Ericsson Telecom, SE; K. Chakrabarty, Duke U, US

Design of Sub10Picoseconds OnChip Time Measurement Circuit [p. 804]

M. Abas, D. Kinniment, and G. Russell

Impact of Test Point Insertion on Silicon Area and Timing during Layout [p. 810]

H. Vranken, H. Wunderlich, and F. Sapei

Designing Self Test Programs for Embedded DSP Cores [p. 816]

H. Rizk, C. Papachristou, and F. Wolff
Moderators: P. Feldmann, IBM T.J. Watson Res. Center, US; L. Silveira, INESC ID/IST  TU Lisbon, PT

Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction [p. 824]

Z. Wang, J. Roychowdhury, and R. Murgai

Thermal and Power Integrity Based Power/Ground Networks Optimization [p. 830]

T. Wang, J. Tsai, and C. Chen

Synthesized Compact Models (SCM) of Substrate Noise Coupling Analysis and
Synthesis in MixedSignal ICs [p. 836]

H. Lan and R. Dutton
Organizer/Moderator: P. Paulin, STMicroelectronics, FR
Panellists:
R. Bramley, STMicroelectronics
A. Silburt, Cisco, CAN
J. Balzano, Alcatel, FR
K. van Berkel, Philips Research, NL
N. Wehn, Kaiserslautern U, DE

Chips of the Future: Soft, Crunchy or Hard? [p. 844]

Moderators: M. Pedram, Southern California U, US; A. Amara, ISEP, FR

Tuning InSensor Data Filtering to Reduce Energy Consumption in Wireless Sensor Networks [p. 852]

I. Kadayif and M. Kandemir

PowerAware Network Swapping for Wireless Palmtop PCs [p. 858]

A. Acquaviva, E. Lattanzi, and A. Bogliolo

Power Aware Interface Synthesis for BusBased SoC Design [p. 864]

N. Liveris and P. Banerjee

Asynchronous Design by Conversion: Converting Synchronous Circuits into Asynchronous Ones [p. 870]

A. Branover, R. Kol, and R. Ginosar
Moderators: G. Nicolescu, Ecole Polytechnique de Montreal, CA; M. Coppola, STMicroelectronics, FR

An Efficient OnChip Network Interface Offering Guaranteed Services, SharedMemory Abstraction, and
Flexible Network Configuration [p. 878]

A. Radulescu, J. Dielissen, K. Goossens, E. Rijpkema, and P. Wielage

×pipesCompiler: A Tool for Instantiating Application Specific NetworksonChip [p. 884]

S. Murali, G. De Micheli, A. Jalabert, and L. Benini

Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the
Nostrum Network on Chip [p. 890]

M. Millberg, E. Nilsson, R. Thid, and A. Jantsch

BandwidthConstrained Mapping of Cores onto NoC Architectures [p. 896]

S. Murali and G. De Micheli
Moderators: T. Kutzschebauch, Magma Design Automation, US; L. Stok, IBM, US

Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies [p. 904]

R. Zhang, P. Gupta, L. Zhong, and N. Jha

Fast Comparisons of Circuit Implementations [p. 910]

S. Karandikar and S. Sapatnekar

Saving Power by Mapping FiniteState Machines into Embedded Memory Blocks in FPGAs [p. 916]

A. Tiwari and K. Tomko

MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with
Embedded Memory Arrays Using Reconvergence Analysis [p. 922]

M. Kumar, J. Bobba, and V. Kamakoti
Organizer: K. Thapar, Mentor Graphics Europe, UK
Moderator: J. Rajski, Mentor Graphics, US
Panellists:
M. Vergniault, STMicroelectronics, FR
P. Muhmenthaler, Infineon Technologies, DE
E. Haioun, Motorola, FR
E. Marinissen, Philips Research, NL
R. Illman, Cadence Design Foundry, UK
B. Bennetts, Bennetts Associates, UK
S. Dowd, Jennic, UK

Nanometer Design: What are the Requirements for Manufacturing Test? [p. 930]
Moderators: I. Elfadel, IBM T.J. Watson Res. Center, US; U. Feldmann, Infineon Technologies, DE

Poor Man's TBR: A Simple Model Reduction Scheme [p. 938]

J. Phillips and L. Silveira

Model Order Reduction Techniques for Linear Systems with Large Numbers of Terminals [p. 944]

P. Feldmann

SCORE: Spice COmpatible Reluctance Extraction [p. 948]

R. Jiang and C. Chen

A Compact Propagation Delay Model for DeepSubmicron CMOS Technologies including Crosstalk [p. 954]

J. Rosselló and J. Segura
Moderators: T. Basten, TU Eindhoven, NL; L. Claesen, National Chiao Tung U, Taiwan, ROC

A Framework for BatteryAware Sensor Management [p. 962]

S. Dasika, S. Vrudhula, S. Chopra, and R. Srinivasan

Local Decisions and Triggering Mechanisms for Dynamic Fault Tolerance [p. 968]

P. StanleyMarbell and D. Marculescu

An Algorithm for NanoPipelining of Circuits and Architectures for a Nanotechnology [p. 974]

P. Gupta and N. Jha

Smaller TwoQubit Circuits for Quantum Communication and Computation [p. 980]

V. Shende, I. Markov, and S. Bullock
Organizer: E. Macii, Politecnico di Torino, IT
Moderator: N. Chang, Seoul National U, KR
Speakers:
I. Verbauwhede, UCLA, US
C. Piguet, CSEM, CH
P. Schaumont, UCLA, US
B. Kienhuis, Leiden U, NL

Architectures and Design Techniques for Energy Efficient
Embedded DSP and Multimedia Processing [p. 988]

Moderators: R. Seepold, Carlos III de Madrid U, ES; T. Riesgo, UP Madrid, ES

Measurement of IP Qualification Costs and Benefits [p. 996]

A. Vörg, W. Rosenstiel, and M. Radetzki

ArchitectureLevel Performance Estimation for IPBased Embedded Systems [p. 1002]

K. Ueda, K. Sakanushi, Y. Takeuchi, and M. Imai

Generalized LatencyInsensitive Systems for SingleClock and MultiClock Architectures [p. 1008]

M. Singh and M. Theobald

Platform Based on OpenSource Cores for Industrial Applications [p. 1014]

M. Bolado, J. Castillo, P. Huerta, H. Posadas, P. Sánchez, C. Sánchez, F. Blasco, and H. Fouren

MINCE: Matching INstructions with Combinational Equivalence for Extensible Processor [p. 1020]

N. Cheung, S. Parameswaran, J. Henkel, and J. Chan
Moderators: S. Hu, Notre Dame U, US; F. Wolf, Volkswagen, DE

Design Optimization of MultiCluster Embedded Systems for RealTime Applications [p. 1028]

P. Pop, P. Eles, Z. Peng, V. Izosimov, M. Hellring, and O. Bridal

Timing Analysis for Preemptive MultiTasking RealTime Systems with Caches [p. 1034]

Y. Tan and V. Mooney

Workload Characterization Model for Tasks with Variable Execution Demand [p. 1040]

A. Maxiaguine, S. Künzli, and L. Thiele

ContextAware Performance Analysis for Efficient Embedded System Design [p. 1046]

M. Jersak, R. Henia, and R. Ernst

Compact Binaries with Code Compression in a Software Dynamic Translator [p. 1052]

S. Shogan and B. Childers
Moderators: R. Aitken, Artisan, US; H. Manhaeve, Qstar Test, BE

Pattern Selection for Testing of Deep SubMicron Timing Defects [p. 1060]

M. C. Chao, L. Wang, and K. Cheng

Balanced Excitation and its Effect on the Fortuitous Detection of Dynamic Defects [p. 1066]

J. Dworak, B. Cobb, J. Wingfield, and M. Mercer

Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis [p. 1072]

Y. Huang, W. Cheng, C. Hsieh, H. Tseng, A. Huang, and Y. Hung

A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuits [p. 1078]

C. Tirumurti, S. Kundu, S. SurKolay, and Y. Chang

Soft Faults and the Importance of Stresses in Memory Testing [p. 1084]

Z. AlArs and A. van De Goor
Moderators: J. Lienig, TU Dresden, DE; R. Otten, TU Eindhoven, NL

Wire Retiming for SystemOnChip by Fixpoint Computation [p. 1092]

C. Lin and H. Zhou

Boosting: MinCut Placement with Improved Signal Delay [p. 1098]

A. Kahng, S. Reda, and I. Markov

Optimal Algorithm for Minimizing the Number of Twists in an OnChip Bus [p. 1104]

L. Deng and M. Wong

A Fast WordLevel Statistical Estimator of IntraBus Crosstalk [p. 1110]

S. Gupta and S. Katkoori

FullChip Multilevel Routing for Power and Signal Integrity [p. 1116]

J. Xiong and L. He
Organizer/Moderator: E. Pol, Philips Research, NL
Speakers:
H. Van Antwerpen, Philips Research, NL
R. von Vignau, Philips Research, NL
R. Gupta, UC San Diego, US
N. Dutt, UC Irvine, US
N. Venkatasubramanian, UC Irvine, US
S. Mohapatra, UC California Irvine, US
C. Pereira, UC California San Diego, US

EnergyAware System Design for Wireless Multimedia [p. 1124]

Moderators: K. Goossens, Philips Research, NL; L. Benini, Bologna U, IT

Unified Component Integration Flow for MultiProcessor SoC Design and Validation [p. 1132]

M. Dziri, W. Cesário, A. Jerraya, and F. Wagner

An Interconnect Channel Design Methodology for High Performance Integrated Circuits [p. 1138]

V. Chandra, A. Xu, H. Schmit, and L. Pileggi

Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach [p. 1144]

A. Bobrek, J. Pieper, J. Nelson, J. Paul, and D. Thomas

Supporting Cache Coherence in Heterogeneous Multiprocessor Systems [p. 1150]

T. Suh, D. Blough, and H. Lee
Moderators: R. Ernst, TU Braunschweig; P. Kajfasz, Thales Communications, FR

Exploiting Processor Workload Heterogeneity for Reducing Energy Consumption in Chip Multiprocessors [p. 1158]

I. Kadayif, M. Kandemir, and I. Kolcu

FaultTolerant Deployment of Embedded Software for CostSensitive
RealTime FeedbackControl Applications [p. 1164]

C. Pinello, L. Carloni, and A. SangiovanniVincentelli

Task Feasibility Analysis and Dynamic Voltage Scaling in FaultTolerant RealTime Embedded Systems [p. 1170]

Y. Zhang and K. Chakrabarty

QuasiStatic Scheduling for RealTime Systems with Hard and Soft Tasks [p. 1176]

L. Cortés, P. Eles, and Z. Peng
Organizer/Moderator: B. Bennetts, Bennetts Associates, UK

Status of IEEE Testability Standards 1149.4, 1532 and 1149.6 [p. 1184]

S. Sunter, A. Osseiran, A. Cron, N. Jacobson, D. Bonnett, B. Eklow, C. Barnhart, and B. Bennetts
Moderators: I. Markov, Michigan U, US; J. Lienig, TU Dresden, DE

Eliminating False Positives in Crosstalk Noise Analysis [p. 1192]

Y. Ran, M. MarekSadowska, A. Kondratyev, and Y. Watanabe

A New Approach to Timing Analysis Using Event Propagation and Temporal Logic [p. 1198]

A. Mondal, P. Chakrabarti, and C. Mandal

A New Effective Congestion Model in Floorplan Design [p. 1204]

Y. Hsieh and T. Hsieh

ULSI Interconnect Length Distribution Model Considering Core Utilization [p. 1210]

H. Nakashima, J. Inoue, K. Okada, and K. Masu
Moderators: Y. Tanurhan, Actel, US; W. Rosenstiel, Tuebingen U and FZI Karlsruhe, DE

Implementation of a UMTS Turbodecoder on a Dynamically Reconfigurable Platform [p. 1218]

A. La Rosa, C. Passerone, F. Gregoretti, and L. Lavagno

Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study [p. 1224]

B. Mei, R. Lauwereins, S. Vernalde, and D. Verkest

Efficient Implementations of Mobile Video Computations on DomainSpecific Reconfigurable Arrays [p. 1230]

I. Ahmed, S. Baloch, A. Pai, T. Arslan, N. Aydin, S. Khawam, and F. Westall

Mapping MultiMillion Gate SoCs on FPGAs: Industrial Methodology and Experience [p. 1236]

H. Krupnova
Moderators: B. Candaele, Thales, FR; A. Jerraya, TIMA Laboratory, FR

Using a Communication Architecture Specification in an ApplicationDriven Retargetable
Prototyping Platform for Multiprocessing [p. 1244]

X. Zhu and S. Malik

A Power and Performance Model for NetworkonChip Architectures [p. 1250]

N. Banerjee, P. Vellanki, and K. Chatha

A System Level Processor/Communication CoExploration Methodology for
MultiProcessor SystemonChip Platforms [p. 1256]

A. Wieferink, T. Kogel, R. Leupers, G. Ascheid, H. Meyr, G. Braun, and A. Nohl
Moderators: F. Rousseau, TIMA Laboratory, FR; J. Madsen, TU Denmark, DK

CacheAware Scratchpad Allocation Algorithm [p. 1264]

M. Verma, L. Wehmeyer, and P. Marwedel

Phase Coupled Code Generation for DSPs Using a Genetic Algorithm [p. 1270]

M. Lorenz and P. Marwedel

A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models [p. 1276]

M. Hohenauer, H. Scharwaechter, K. Karuri, O. Wahlen, T. Kogel,
R. Leupers, G. Ascheid, H. Meyr, G. Braun, and H. van Someren
Moderators: H. Vranken, Philips Research, NL; C. Papachristou, Case Western Reserve U, US

NineCoded Compression Technique with Application to Reduced PinCount Testing and
Flexible OnChip Decompression [p. 1284]

M. Tehranipour, M. Nourani, and K. Chakrabarty

CircularScan: A Scan Architecture for Test Cost Reduction [p. 1290]

B. Arslan and A. Orailoglu

Hybrid Delay Scan: A Low Hardware Overhead ScanBased Delay Test Technique for
High Fault Coverage and Compact Test Sets [p. 1296]

S. Wang, S. Chakradhar, and X. Liu

Diagnosis of ScanChains by Use of a Configurable Signature Register and ErrorCorrecting Codes [p. 1302]

A. Leininger, P. Muhmenthaler, and M. Goessel
Moderators: T. Kazmierski, Southampton U, UK; S. Yoo, TIMA Laboratory, FR

Hierarchical MultiDimensional Table Lookup for Model Compiler Based Circuit Simulation [p. 1310]

B. Wan and C. Shi

Direct Nonlinear Order Reduction with Variational Analysis [p. 1316]

L. Feng, X. Zeng, C. Chiang, D. Zhou, and Q. Fang

SteadyState Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method [p. 1322]

X. Zhou, D. Zhou, J. Liu, R. Li, X. Zeng, and C. Chiang

Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits [p. 1327]

T. Mine, H. Kubota, A. Kamo, T. Watanabe, and H. Asai
Organizer/Moderator: H. Schlebusch, Synopsys, DE
Speaker: T. Fitzpatrick, Synopsys, US

System Verilog for VHDL Users [p. 1334]

Organizer/Moderator: P. Eles, Linkoping U, SE
Speakers:
R. Marculescu, Carnegie Mellon U, US
J. Henkel, NEC, US
M. Pedram, Southern California U, US

Distributed Multimedia System Design: A Holistic Perspective [p. 1342]


Adaptive Prefetching for Multimedia Applications in Embedded Systems [p. 1350]

H. Sbeyti, S. Niar, and L. Eeckhout

Data Windows: A DataCentric Approach for Query Execution in MemoryResident Databases [p. 1352]

J. Pisharath, A. Choudhary, and M. Kandemir

HighPerformance QuIDDBased Simulation of Quantum Circuits [p. 1354]

G. Viamontes, I. Markov, and J. Hayes

An Application of Parallel Discrete Event Simulation Algorithms to Mixed Domain System Simulation [p. 1356]

D. Reed, S. Levitan, J. Boles, J. Martinez, and D. Chiarulli

Fault Tolerance of Programmable Switch Blocks [p. 1358]

J. Huang, M. Tahoori, and F. Lombardi

A New SelfChecking SumBit Duplicated CarrySelect Adder [p. 1360]

E. Sogomonyan, D. Marienfeld, V. Ocheretnij, and M. Gössel

A Macromodelling Methodology for Efficient HighLevel Simulation of Substrate Noise Generation [p. 1362]

L. Elvira, F. Martorell, X. Aragonés, and J. González

Accurate Estimation of Parasitic Capacitances in Analog Circuits [p. 1364]

A. Agarwal, H. Sampath, V. Yelamanchili, and R. Vemuri

GRAAL  A Development Framework for Embedded Graphics Accelerators [p. 1366]

D. Crisu, S. Cotofana, S. Vassiliadis, and P. Liuha

From Synchronous to Asynchronous: An Automatic Approach [p. 1368]

J. Cortadella, A. Kondratyev, L. Lavagno, K. Lwin, and C. Sotiriou

Enhancing Testability of System on Chips Using Network Management Protocols [p. 1370]

O. Laouamri and C. Aktouf

Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique [p. 1372]

M. Lampropoulos, B. AlHashimi, and P. Rosinger

EnergyEfficient Design for Highly Associative Instruction Caches in NextGeneration Embedded Processors [p. 1374]

J. Aragon, D. Nicolaescu, A. Veidenbaum, and A. Badulescu

Dynamic Voltage and Cache Reconfiguration for Low Power [p. 1376]

A. Nacul and A. Givargis

Overheadfree Polymorphism in NetworkonChip Implementation of ObjectOriented Models [p. 1380]

M. Goudarzi, S. Hessabi, and A. Mycroft

MultiProcessor SoC Design Methodology Using a Concept of TwoLayer HardwareDependent Software [p. 1382]

S. Yoo, M. Youssef, A. Bouchhima, A. Jerraya, and M. DiazNava

Synthesis of Reversible Logic [p. 1384]

A. Agrawal and N. Jha

A Unified Design Space for Regular Parallel Prefix Adders [p. 1386]

M. Ziegler and M. Stan

MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions [p. 1388]

A. Jabir and D. Pradhan

Issues in Implementing Latency Insensitive Protocols [p. 1390]

M. Casu and L. Macchiarulo

ModelBased Specification and Execution of Embedded RealTime Systems [p. 1392]

T. Schattkowsky and W. Mueller

A Demonstration of CoDesign and CoVerification in a Synchronous Language [p. 1394]

S. Singh

Profile Guided Management of Code Partitions for Embedded Systems [p. 1396]

S. Zhou, B. Childers, and N. Kumar

Realizable Reduction for Electromagnetically Coupled RLMC Interconnects [p. 1400]

R. Jiang and C. Chen

Statistically Aware Buffer Planning [p. 1402]

G. Garcea, N. van der Meijs, and R. Otten

A Tunneling Model for Gate Oxide Failure in Deep SubMicron Technology [p. 1404]

S. Bernadini, J. Portal, and P. Masson

Power Supply Noise Monitor for Signal Integrity Faults [p. 1406]

J. Vázquez and J. de Gyvez

Testing of Quantum Dot Cellular Automata Based Designs [p. 1408]

M. Tahoori and F. Lombardi

Net and Pin Distribution for 3D Package Global Routing [p. 1410]

J. Minz, M. Pathak, and S. Lim

Placement Using a Localization Probability Model (LPM) [p. 1412]

M. Olbrich and E. Barke

CMOS Structures Suitable for Secured Hardware [p. 1414]

S. Guilley, P. Hoogvorst, Y. Mathieu, R. Pacalet, and J. Provost

Timing Correction and Optimization with Adaptive Delay Sequential Elements [p. 1416]

K. Rahimi, S. Bridges, and C. Diorio