SIGDA, DATE 2004, Author Index

DATE 2004 AUTHOR INDEX

[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] [X] [Y] [Z]

Abas, M.: Design of Sub-10-Picoseconds On-Chip Time Measurement Circuit [p. 804]
Aboulhamid, E.: .NET Framework -- A Solution for the Next Generation Tools for System-Level Modeling and Simulation [p. 732]
Aboulhamid, M.: A System Level Exploration Platform and Methodology for Network Applications Based on Configurable Processors [p. 364]
Aboushady, H.: Automatic Synthesis and Simulation of Continuous-Time ΣΔ Modulators [p. 674]
Acquaviva, A.: Power-Aware Network Swapping for Wireless Palmtop PCs [p. 858]
Agarwal, A.: Fast, Layout-Inclusive Analog Circuit Synthesis Using Pre-Compiled Parasitic-Aware Symbolic Performance Models [p. 604]; Accurate Estimation of Parasitic Capacitances in Analog Circuits [p. 1364]
Agrawal, A.: Synthesis of Reversible Logic [p. 1384]
Ahmed, I.: Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays [p. 1230]
Aktouf, C.: Enhancing Testability of System on Chips Using Network Management Protocols [p. 1370]
Alakarhu, J.: Scalar Metric for Temporal Locality and Estimation of Cache Performance [p. 730]
Al-Ars, Z.: Soft Faults and the Importance of Stresses in Memory Testing [p. 1084]
Al-Hashimi, B.: Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems [p. 518]; Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique [p. 1372]
Almukhaizim, S.: On Concurrent Error Detection with Bounded Latency in FSMs [p. 596]
Aloul, F.: Breaking Instance-Independent Symmetries in Exact Graph Coloring [p. 324]
Ammari, A.: Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow [p. 590]
Andrei, A.: Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems [p. 518]
Angiolini, F.: Analyzing On-Chip Communication in a MPSoC Environment [p. 752]
Aragon, J.: Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors [p. 1374]
Aragonés, X.: A Macromodelling Methodology for Efficient High-Level Simulation of Substrate Noise Generation [p. 1362]
Araújo, G.: Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology [p. 734]
Arslan, B.: CircularScan: A Scan Architecture for Test Cost Reduction [p. 1290]
Arslan, T.: Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays [p. 1230]
Asai, H.: Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits [p. 1327]
Ascheid, G.: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms [p. 1256]; A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models [p. 1276]
Atienza, D.: Dynamic Memory Management Design Methodology for Reduced Memory. Footprint in Multimedia and Wireless Network Applications [p. 532]
Aydin, N.: Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays [p. 1230]
Azevedo, R.: Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology [p. 734]

Babighian, P.: A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks [p. 500]; Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating [p. 720]
Badaroglu, M.: Digital Ground Bounce Reduction by Phase Modulation of the Clock [p. 88]
Badulescu, A.: Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors [p. 1374]
Baloch, S.: Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays [p. 1230]
Balzano, J.: Chips of the Future: Soft, Crunchy or Hard? [p. 844]
Banerjee, N.: A Power and Performance Model for Network-on-Chip Architectures [p. 1250]
Banerjee, P.: Power Aware Interface Synthesis for Bus-Based SoC Design [p. 864]
Bansal, N.: Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures [p. 474]
Baranowski, J.: Efficient Mixed-Domain Behavioural Modeling of Ferromagnetic Hysteresis Implemented in VHDL-AMS [p. 742]
Barke, E.: Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques [p. 442]; Placement Using a Localization Probability Model (LPM) [p. 1412]
Barnhart, C.: Status of IEEE Testability Standards 1149.4, 1532 and 1149.6 [p. 1184]
Barros, E.: Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology [p. 734]
Baschirotto, A.: Pseudo-Random Sequence Based Tuning System for Continuous-Time Filters [p. 94]
Basten, T.: Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks [p. 384]
Basu, P.: Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent? [p. 668]
Baumgartner, J.: Enhanced Diameter Bounding via Structural Transformation [p. 36]
Becer, M.: False-Noise Analysis for Domino Circuits [p. 784]
Beilleau, N.: Automatic Synthesis and Simulation of Continuous-Time ΣΔ Modulators [p. 674]
Bellato, M.: Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA [p. 584]
Benabdenbi, M.: STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores [p. 712]
Benini, L.: A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks [p. 500]; Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning [p. 698]; Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating [p. 720]; Analyzing On-Chip Communication in a MPSoC Environment [p. 752]; ×pipesCompiler: A Tool for Instantiating Application Specific Networks-on-Chip [p. 884]
Bennetts, B.: Nanometer Design: What are the Requirements for Manufacturing Test? [p. 930]; Status of IEEE Testability Standards 1149.4, 1532 and 1149.6 [p. 1184]
Bernadini, S.: A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology [p. 1404]
Bernardi, P.: Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA [p. 584]
Bernardinis, F. De: A Methodology for System-Level Analog Design Space Exploration [p. 676]
Bertozzi, D.: Analyzing On-Chip Communication in a MPSoC Environment [p. 752]
Bhattacharya, S.: Efficient Test Strategy for TDMA Power Amplifiers Using Transient Current Measurements: Uses and Benefits [p. 280]
Bhunia, S.: Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis [p. 708]
Bjesse, P.: Using Counter Example Guided Abstraction Refinement to Find Complex Bugs [p. 156]
Blaauw, D.: Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization [p. 494]; Concurrent Sizing, Vdd and V_th Assignment for Low-Power Design [p. 718]
Blasco, F.: System-Level Performance Analysis in SystemC [p. 378]; Platform Based on Open-Source Cores for Industrial Applications [p. 1014]
Blough, D.: Supporting Cache Coherence in Heterogeneous Multiprocessor Systems [p. 1150]
Bobba, J.: MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis [p. 922]
Bobrek, A.: Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach [p. 1144]
Bogliolo, A.: Power-Aware Network Swapping for Wireless Palmtop PCs [p. 858]
Bois, G.: A System Level Exploration Platform and Methodology for Network Applications Based on Configurable Processors [p. 364]; .NET Framework -- A Solution for the Next Generation Tools for System-Level Modeling and Simulation [p. 732]
Bolado, M.: Platform Based on Open-Source Cores for Industrial Applications [p. 1014]
Boles, J.: An Application of Parallel Discrete Event Simulation Algorithms to Mixed Domain System Simulation [p. 1356]
Bonhomme, Y.: Design of Routing-Constrained Low Power Scan Chains [p. 62]
Bonnett, D.: Status of IEEE Testability Standards 1149.4, 1532 and 1149.6 [p. 1184]
Bortolato, D.: Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA [p. 584]
Bose, S.: Extraction of Schematic Array Models for Memory Circuits [p. 570]
Bouchhima, A.: Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent Software [p. 1382]
Bouesse, F.: High Security Smartcards [p. 228]
Bounceur, A.: A 0.18 µm CMOS Implementation of On-Chip Analogue Test Signal Generation from Digital Test Patterns [p. 704]
Boyer, F.: .NET Framework -- A Solution for the Next Generation Tools for System-Level Modeling and Simulation [p. 732]
Bramley, R.: Chips of the Future: Soft, Crunchy or Hard? [p. 844]
Brandtner, T.: SubCALM: A Program for Hierarchical Substrate Coupling Simulation on Floorplan Level [p. 616]
Branover, A.: Asynchronous Design by Conversion: Converting Synchronous Circuits into Asynchronous Ones [p. 870]
Braun, G.: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms [p. 1256]; A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models [p. 1276]
Bridal, O.: Design Optimization of Multi-Cluster Embedded Systems for Real-Time Applications [p. 1028]
Bridges, S.: Timing Correction and Optimization with Adaptive Delay Sequential Elements [p. 1416]
Brière, M.: Design and Behavioral Modeling Tools for Optical Network-On-Chip [p. 738]
Bringmann, O.: Communication Analysis for System on Chip Design [p. 648]
Brockmeyer, E.: Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies [p. 202]
Brorsson, M.: A Low Power Strategy for Future Mobile Terminals [p. 702]
Brown, A.: Efficient Mixed-Domain Behavioural Modeling of Ferromagnetic Hysteresis Implemented in VHDL-AMS [p. 742]
Brunel, J.: SoftContract: An Assertion-Based Software Development Process that Enables Design-by-Contract [p. 358]
Bullock, S.: Smaller Two-Qubit Circuits for Quantum Communication and Computation [p. 980]
Burkhay, V.: Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques [p. 442]
Burleson, W.: Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally Asynchronous Locally-Synchronous SoC's [p. 410]
Burns, F.: An Asynchronous Synthesis Toolset Using Verilog [p. 724]

Cai, L.: Dynamic Power Management Using Date Buffers [p. 526]
Candelori, A.: Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA [p. 584]
Cao, L.: On Transfer Function and Power Consumption Transient Response [p. 688]
Carloni, L.: Fault-Tolerant Deployment of Embedded Software for Cost-Sensitive Real-Time Feedback-Control Applications [p. 1164]
Carrel, L.: Design and Behavioral Modeling Tools for Optical Network-On-Chip [p. 738]
Carro, L.: Low Cost Analog Testing of RF Signal Paths [p. 292]
Castillo, J.: Platform Based on Open-Source Cores for Industrial Applications [p. 1014]
Casu, M.: Issues in Implementing Latency Insensitive Protocols [p. 1390]
Catthoor, F.: Time-Energy Design Space Exploration for Multi-Layer Memory Architectures [p. 318]; How Can System Level Design Solve the Interconnect Technology Scaling Problem? [p. 332]; Dynamic Memory Management Design Methodology for Reduced Memory. Footprint in Multimedia and Wireless Network Applications [p. 532]
Cesário, W.: Unified Component Integration Flow for Multi-Processor SoC Design and Validation [p. 1132]
Ceschia, M.: Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA [p. 584]
Chae, K.: High-Level System Modeling and Architecture Exploration with SystemC on a Network SoC: S3C2510 Case Study [p. 538]
Chakrabarti, P.: Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent? [p. 668]; A New Approach to Timing Analysis Using Event Propagation and Temporal Logic [p. 1198]
Chakrabarty, K.: Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures [p. 422]; Task Feasibility Analysis and Dynamic Voltage Scaling in Fault-Tolerant Real-Time Embedded Systems [p. 1170]; Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression [p. 1284]
Chakradhar, S.: A Case Study in Networks-on-Chip Design for Embedded Video [p. 770]; Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets [p. 1296]
Chan, J.: MINCE: Matching INstructions with Combinational Equivalence for Extensible Processor [p. 1020]
Chandra, V.: An Interconnect Channel Design Methodology for High Performance Integrated Circuits [p. 1138]
Chang, N.: Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing [p. 988]
Chang, Y.: Value-Conscious Cache: Simple Technique for Reducing Cache Access Power [p. 16]; A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuits [p. 1078]
Chao, M. C.: Pattern Selection for Testing of Deep Sub-Micron Timing Defects [p. 1060]
Charest, L.: .NET Framework -- A Solution for the Next Generation Tools for System-Level Modeling and Simulation [p. 732]
Chatha, K.: A Power and Performance Model for Network-on-Chip Architectures [p. 1250]
Chatterjee, A.: Efficient Test Strategy for TDMA Power Amplifiers Using Transient Current Measurements: Uses and Benefits [p. 280]
Chen, C.: Thermal and Power Integrity Based Power/Ground Networks Optimization [p. 830]; SCORE: Spice COmpatible Reluctance Extraction [p. 948]; Realizable Reduction for Electromagnetically Coupled RLMC Interconnects [p. 1400]
Chen, G.: Configuration-Sensitive Process Scheduling for FPGA-Based Computing Platforms [p. 486]
Chen, T.: A Low Cost Individual-Well Adaptive Body Bias (IWABB) Scheme for Leakage Power Reduction and Performance Enhancement in the Presence of Intra-Die Variations [p. 240]
Cheng, K.: Improved Symbolic Simulation by Dynamic Functional Space Partitioning [p. 42]; Random Jitter Extraction Technique in a Multi-Gigahertz Signal [p. 286]; Pattern Selection for Testing of Deep Sub-Micron Timing Defects [p. 1060]
Cheng, W.: Power Minimization in a Backlit TFT-LCD Display by Concurrent Brightness and Contrast Scaling [p. 252]; Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis [p. 1072]
Cherubal, S.: Efficient Test Strategy for TDMA Power Amplifiers Using Transient Current Measurements: Uses and Benefits [p. 280]
Cheung, N.: MINCE: Matching INstructions with Combinational Equivalence for Extensible Processor [p. 1020]
Cheung, P.: A Novel Implementation of Tile-Based Address Mapping [p. 306]
Chiang, C.: Direct Nonlinear Order Reduction with Variational Analysis [p. 1316]; Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method [p. 1322]
Chiarulli, D.: An Application of Parallel Discrete Event Simulation Algorithms to Mixed Domain System Simulation [p. 1356]
Childers, B.: Compact Binaries with Code Compression in a Software Dynamic Translator [p. 1052]; Profile Guided Management of Code Partitions for Embedded Systems [p. 1396]
Chin, J.: SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance [p. 710]
Choi, K.: Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Trade-Off Based on the Ratio of Off-Chip Access to On-Chip Computation Times [p. 4]; Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design [p. 352]; A Game Theoretic Approach to Low Energy Wireless Video Streaming [p. 696]
Chopra, S.: A Framework for Battery-Aware Sensor Management [p. 962]
Choudhary, A.: Flexible Software Protection Using Hardware/Software Codesign Techniques [p. 636]; Data Windows: A Data-Centric Approach for Query Execution in Memory-Resident Databases [p. 1352]
Chung, E.: Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design [p. 352]
Cobb, B.: Balanced Excitation and its Effect on the Fortuitous Detection of Dynamic Defects [p. 1066]
Corsi, F.: Pseudo-Random Sequence Based Tuning System for Continuous-Time Filters [p. 94]
Cortadella, J.: From Synchronous to Asynchronous: An Automatic Approach [p. 1368]
Cortés, L.: Quasi-Static Scheduling for Real-Time Systems with Hard and Soft Tasks [p. 1176]
Cotofana, S.: Compositional Memory Systems for Data Intensive Applications [p. 728]; GRAAL -- A Development Framework for Embedded Graphics Accelerators [p. 1366]
Crisu, D.: GRAAL -- A Development Framework for Embedded Graphics Accelerators [p. 1366]
Cron, A.: Status of IEEE Testability Standards 1149.4, 1532 and 1149.6 [p. 1184]
Cuomo, A.: How Can System Level Design Solve the Interconnect Technology Scaling Problem? [p. 332]

D'Amico, S.: Pseudo-Random Sequence Based Tuning System for Continuous-Time Filters [p. 94]
D'Silva, V.: Synchronous Protocol Automata: A Framework for Modelling and Verification of SoC Communication Architectures [p. 390]
Das, S.: Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent? [p. 668]
Dasgupta, P.: Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent? [p. 668]
Dasika, S.: A Framework for Battery-Aware Sensor Management [p. 962]
David, J.: .NET Framework -- A Solution for the Next Generation Tools for System-Level Modeling and Simulation [p. 732]
Deb, A. K.: System Design for DSP Applications Using the MASIC Methodology [p. 630]
Deng, L.: Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus [p. 1104]
Densmore, D.: Microarchitecture Development via Metropolis Successive Platform Refinement [p. 346]
Deogun, H.: Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization [p. 494]
Deprettere, E.: System Design Using Kahn Process Networks: The Compaan/Laura Approach [p. 340]
Diaz-Nava, M.: Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent Software [p. 1382]
Dielissen, J.: An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration [p. 878]
Dimopoulos, M.: Efficient Static Compaction of Test Sequence Sets through the Application of Set Covering Techniques [p. 194]
Diorio, C.: Timing Correction and Optimization with Adaptive Delay Sequential Elements [p. 1416]
Dittmann, G.: Organizing Libraries of DFG Patterns [p. 726]
Doboli, A.: Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip [p. 108]
Donnay, S.: Digital Ground Bounce Reduction by Phase Modulation of the Clock [p. 88]; Extended Subspace Identification of Improper Linear Systems [p. 454]
Dowd, S.: Nanometer Design: What are the Requirements for Manufacturing Test? [p. 930]
Drechsler, R.: Managing Don't Cares in Boolean Satisfiability [p. 260]
Drineas, P.: On Concurrent Error Detection with Bounded Latency in FSMs [p. 596]
Duan, C.: Exploiting Crosstalk to Speed up On-Chip Buses [p. 778]
Dutt, N.: Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow [p. 114]; Graph-Based Functional Test Program Generation for Pipelined Processors [p. 182]; Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies [p. 202]; Automatic Tuning of Two-Level Caches to Embedded Applications [p. 208]; Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures [p. 474]; Energy-Aware System Design for Wireless Multimedia [p. 1124]
Dutton, R.: Synthesized Compact Models (SCM) of Substrate Noise Coupling Analysis and Synthesis in Mixed-Signal ICs [p. 836]
Dworak, J.: Balanced Excitation and its Effect on the Fortuitous Detection of Dynamic Defects [p. 1066]
Dziri, M.: Unified Component Integration Flow for Multi-Processor SoC Design and Validation [p. 1132]

Edwards, D.: Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits [p. 672]
Eeckhout, L.: Adaptive Prefetching for Multimedia Applications in Embedded Systems [p. 1350]
Efthymiou, A.: Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits [p. 672]
Eijndhoven, J. van: Compositional Memory Systems for Data Intensive Applications [p. 728]
Eklow, B.: Status of IEEE Testability Standards 1149.4, 1532 and 1149.6 [p. 1184]
Eles, P.: Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems [p. 518]; Design Optimization of Multi-Cluster Embedded Systems for Real-Time Applications [p. 1028]; Quasi-Static Scheduling for Real-Time Systems with Hard and Soft Tasks [p. 1176]; Distributed Multimedia System Design: A Holistic Perspective [p. 1342]
Elvira, L.: A Macromodelling Methodology for Efficient High-Level Simulation of Substrate Noise Generation [p. 1362]
Eo, S.: Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design [p. 352]
Ernst, R.: Context-Aware Performance Analysis for Efficient Embedded System Design [p. 1046]
Essa, S.: Integrating the Synchronous Dataflow Model with UML [p. 736]

Fang, Q.: Direct Nonlinear Order Reduction with Variational Analysis [p. 1316]
Feldmann, P.: Model Order Reduction Techniques for Linear Systems with Large Numbers of Terminals [p. 944]
Feng, L.: Direct Nonlinear Order Reduction with Variational Analysis [p. 1316]
Feng, T.: Improved Symbolic Simulation by Dynamic Functional Space Partitioning [p. 42]
Fernandes, J.: A Probabilistic Method for the Computation of Testability of RTL Constructs [p. 176]
Ferrari, A.: SoftContract: An Assertion-Based Software Development Process that Enables Design-by-Contract [p. 358]
Fey, G.: Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor [p. 162]
Fit-Florea, A.: Enhancing Reliability of Operational Interconnections in FPGAs [p. 746]
Fitzpatrick, T.: System Verilog for VHDL Users [p. 1334]
Fix, L.: Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent? [p. 668]
Flake, P.: SystemC and System Verilog: Where do They Fit? Where are they going? [p. 122]
Flottes, M.: An Arithmetic Structure for Test Data Horizontal Compression [p. 428]
Fouren, H.: Platform Based on Open-Source Cores for Industrial Applications [p. 1014]
Fu, M.: Exploring Logic Block Granularity for Regular Fabrics [p. 468]
Fummi, F.: Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC [p. 564]

Gaffiot, F.: Design and Behavioral Modeling Tools for Optical Network-On-Chip [p. 738]
Gangwal, O.: Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach [p. 764]
Garcea, G.: Statistically Aware Buffer Planning [p. 1402]
García, J.: A Direct Bootstrapped CMOS Large Capacitive-Load Driver Circuit [p. 680]
Gautier, J.: Extremely Low-Power Logic [p. 656]
Gavrilov, S.: False-Noise Analysis for Domino Circuits [p. 784]
Germain, F.: High Security Smartcards [p. 228]
Ghenassia, F.: SystemC and System Verilog: Where do They Fit? Where are they going? [p. 122]
Gielen, G.: Digital Ground Bounce Reduction by Phase Modulation of the Clock [p. 88]; A Phase-Frequency Transfer Description of Analog and Mixed-Signal Front-End Architectures for System-Level Design [p. 436]; Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines [p. 448]; Fast, Layout-Inclusive Analog Circuit Synthesis Using Pre-Compiled Parasitic-Aware Symbolic Performance Models [p. 604]
Ginés, A.: Digital Background Gain Error Correction in Pipeline ADCs [p. 82]
Ginosar, R.: Asynchronous Design by Conversion: Converting Synchronous Circuits into Asynchronous Ones [p. 870]
Girard, P.: Design of Routing-Constrained Low Power Scan Chains [p. 62]
Giusto, P.: SoftContract: An Assertion-Based Software Development Process that Enables Design-by-Contract [p. 358]
Givargis, A.: Dynamic Voltage and Cache Reconfiguration for Low Power [p. 1376]
Gizopoulos, D.: Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors [p. 578]
Glebov, A.: False-Noise Analysis for Domino Circuits [p. 784]
Goessel, M.: Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Codes [p. 1302]
Goloubeva, O.: Automatic Generation of Validation Stimuli for Application-Specific Processors [p. 188]
González, J.: A Macromodelling Methodology for Efficient High-Level Simulation of Substrate Noise Generation [p. 1362]
Goor, A. van De: Soft Faults and the Importance of Stresses in Memory Testing [p. 1084]
Goossens, K.: Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach [p. 764]; An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration [p. 878]
Gopalakrishnan, P.: Exploring Logic Block Granularity for Regular Fabrics [p. 468]
Gordon-Ross, A.: Automatic Tuning of Two-Level Caches to Embedded Applications [p. 208]
Gössel, M.: A New Self-Checking Sum-Bit Duplicated Carry-Select Adder [p. 1360]
Goudarzi, M.: Overhead-free Polymorphism in Network-on-Chip Implementation of Object-Oriented Models [p. 1380]
Green, P.: Integrating the Synchronous Dataflow Model with UML [p. 736]
Gregg, J.: A Low Cost Individual-Well Adaptive Body Bias (IWABB) Scheme for Leakage Power Reduction and Performance Enhancement in the Presence of Intra-Die Variations [p. 240]
Gregoretti, F.: Implementation of a UMTS Turbo-decoder on a Dynamically Reconfigurable Platform [p. 1218]
Greiner, A.: STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores [p. 712]
Grimm, C.: Refinement of Mixed-Signal Systems with Affine Arithmetic [p. 372]
Groeneveld, P.: How Can System Level Design Solve the Interconnect Technology Scaling Problem? [p. 332]
Grünewald, M.: A Mapping Strategy for Resource-Efficient Network Processing on Multiprocessor SoCs [p. 758]
Guernic, P. Le: Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks [p. 384]
Guiller, L.: Design of Routing-Constrained Low Power Scan Chains [p. 62]
Guilley, S.: CMOS Structures Suitable for Secured Hardware [p. 1414]
Gupta, P.: Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies [p. 904]; An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology [p. 974]
Gupta, R.: Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow [p. 114]; Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures [p. 474]; Energy-Aware System Design for Wireless Multimedia [p. 1124]
Gupta, S.: Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow [p. 114]; Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures [p. 474]; A Fast Word-Level Statistical Estimator of Intra-Bus Crosstalk [p. 1110]
Gyvez, J. de: Power Supply Noise Monitor for Signal Integrity Faults [p. 1406]

Haioun, E.: Nanometer Design: What are the Requirements for Manufacturing Test? [p. 930]
Halas, M.: Enhancing Reliability of Operational Interconnections in FPGAs [p. 746]
Handa, M.: A Fast Algorithm for Finding Maximal Empty Rectangles for Dynamic FPGA Placement [p. 744]
Harris, I.: Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally Asynchronous Locally-Synchronous SoC's [p. 410]
Hayes, J.: High-Performance QuIDD-Based Simulation of Quantum Circuits [p. 1354]
He, L.: Full-Chip Multilevel Routing for Power and Signal Integrity [p. 1116]
Heath, M.: Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally Asynchronous Locally-Synchronous SoC's [p. 410]
Hedrich, L.: Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques [p. 442]
Heer, C.: Extremely Low-Power Logic [p. 656]
Heijligers, M.: Compositional Memory Systems for Data Intensive Applications [p. 728]
Hellring, M.: Design Optimization of Multi-Cluster Embedded Systems for Real-Time Applications [p. 1028]
Henia, R.: Context-Aware Performance Analysis for Efficient Embedded System Design [p. 1046]
Henkel, J.: A Case Study in Networks-on-Chip Design for Embedded Video [p. 770]; MINCE: Matching INstructions with Combinational Equivalence for Extensible Processor [p. 1020]; Distributed Multimedia System Design: A Holistic Perspective [p. 1342]
Hermida, R.: Behavioural Bitwise Scheduling Based on Computational Effort Balancing [p. 684]
Herrera, F.: System-Level Performance Analysis in SystemC [p. 378]
Hessabi, S.: Overhead-free Polymorphism in Network-on-Chip Implementation of Object-Oriented Models [p. 1380]
Hettiaratchi, S.: A Novel Implementation of Tile-Based Address Mapping [p. 306]
Heupke, W.: Refinement of Mixed-Signal Systems with Affine Arithmetic [p. 372]
Hohenauer, M.: A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models [p. 1276]
Hong, D.: Random Jitter Extraction Technique in a Multi-Gigahertz Signal [p. 286]
Hoogvorst, P.: CMOS Structures Suitable for Secured Hardware [p. 1414]
Horie, T.: Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis [p. 610]
Hou, Y.: Power Minimization in a Backlit TFT-LCD Display by Concurrent Brightness and Contrast Scaling [p. 252]
Hounsell, B.: Co-Processor Synthesis: A New Methodology for Embedded Software Acceleration [p. 682]
Hsiao, M.: A Novel SAT All-Solutions Solver for Efficient Preimage Computation [p. 272]
Hsieh, C.: Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis [p. 1072]
Hsieh, T.: A New Effective Congestion Model in Floorplan Design [p. 1204]
Hsieh, Y.: A New Effective Congestion Model in Floorplan Design [p. 1204]
Hu, J.: Scheduling Reusable Instructions for Power Reduction [p. 148]; Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures Under Real-Time Constraints [p. 234]
Hu, X.: Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks [p. 312]
Huang, A.: Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis [p. 1072]
Huang, J.: Fault Tolerance of Programmable Switch Blocks [p. 1358]
Huang, Y.: Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis [p. 1072]
Huang, X.: Identification and Modeling of Nonlinear Dynamic Behavior in Analog Circuits [p. 460]
Huerta, P.: Platform Based on Open-Source Cores for Industrial Applications [p. 1014]
Huertas, G.: A Method for Parameter Extraction of Analog Sine-Wave Signals for Mixed-Signal Built-In-Self-Test Applications [p. 298]
Huertas, J.: A Method for Parameter Extraction of Analog Sine-Wave Signals for Mixed-Signal Built-In-Self-Test Applications [p. 298]
Hung, Y.: Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis [p. 1072]
Hwang, T.: Decomposition of Instruction Decoder for Low Power Design [p. 664]; Crosstalk Minimization in Logic Synthesis for PLA [p. 790]

Ienne, P.: Operating System Support for Interface Virtualization of Reconfigurable Coprocessors [p. 748]
Illman, R.: Nanometer Design: What are the Requirements for Manufacturing Test? [p. 930]
Imai, M.: Architecture-Level Performance Estimation for IP-Based Embedded Systems [p. 1002]
Inoue J.: ULSI Interconnect Length Distribution Model Considering Core Utilization [p. 1210]
Iranli, A.: A Game Theoretic Approach to Low Energy Wireless Video Streaming [p. 696]
Irwin, M.: A Crosstalk Aware Interconnect with Variable Cycle Transmission [p. 102]; Scheduling Reusable Instructions for Power Reduction [p. 148]
Issenin, I.: Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies [p. 202]
Ivaldi, A.: Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning [p. 698]
Izosimov, V.: Design Optimization of Multi-Cluster Embedded Systems for Real-Time Applications [p. 1028]

Jabir, A.: MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions [p. 1388]
Jacobson, N.: Status of IEEE Testability Standards 1149.4, 1532 and 1149.6 [p. 1184]
Jalabert, A.: ×pipesCompiler: A Tool for Instantiating Application Specific Networks-on-Chip [p. 884]
Jang, H.: High-Level System Modeling and Architecture Exploration with SystemC on a Network SoC: S3C2510 Case Study [p. 538]
Jantsch, A.: System Design for DSP Applications Using the MASIC Methodology [p. 630]; Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits [p. 690]; Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip [p. 890]
Jerraya, A.: Unified Component Integration Flow for Multi-Processor SoC Design and Validation [p. 1132]; Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent Software [p. 1382]
Jersak, M.: Context-Aware Performance Analysis for Efficient Embedded System Design [p. 1046]
Jha, N.: Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies [p. 904]; An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology [p. 974]; Synthesis of Reversible Logic [p. 1384]
Jiang, R.: SCORE: Spice COmpatible Reluctance Extraction [p. 948]; Realizable Reduction for Electromagnetically Coupled RLMC Interconnects [p. 1400]
Julien, N.: Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors [p. 666]

Kadayif, I.: Tuning In-Sensor Data Filtering to Reduce Energy Consumption in Wireless Sensor Networks [p. 852]; Exploiting Processor Workload Heterogeneity for Reducing Energy Consumption in Chip Multiprocessors [p. 1158]
Kahng, A.: Boosting: Min-Cut Placement with Improved Signal Delay [p. 1098]
Kamakoti, V.: MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis [p. 922]
Kamo, A.: Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits [p. 1327]
Kandemir, M.: A Crosstalk Aware Interconnect with Variable Cycle Transmission [p. 102]; Scheduling Reusable Instructions for Power Reduction [p. 148]; Configuration-Sensitive Process Scheduling for FPGA-Based Computing Platforms [p. 486]; Impact of Data Transformations on Memory Bank Locality [p. 506]; Tuning In-Sensor Data Filtering to Reduce Energy Consumption in Wireless Sensor Networks [p. 852]; Exploiting Processor Workload Heterogeneity for Reducing Energy Consumption in Chip Multiprocessors [p. 1158]; Data Windows: A Data-Centric Approach for Query Execution in Memory-Resident Databases [p. 1352]
Kang, M.: High-Level System Modeling and Architecture Exploration with SystemC on a Network SoC: S3C2510 Case Study [p. 538]
Karandikar, S.: Fast Comparisons of Circuit Implementations [p. 910]
Karuri, K.: A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models [p. 1276]
Katkoori, S.: A Fast Word-Level Statistical Estimator of Intra-Bus Crosstalk [p. 1110]
Kazmierski, T.: Efficient Mixed-Domain Behavioural Modeling of Ferromagnetic Hysteresis Implemented in VHDL-AMS [p. 742]
Khatri, S.: Exploiting Crosstalk to Speed up On-Chip Buses [p. 778]
Khawam, S.: Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays [p. 1230]
Kheterpal, V.: Exploring Logic Block Granularity for Regular Fabrics [p. 468]
Kiely, T.: Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines [p. 448]
Kienhuis, B.: System Design Using Kahn Process Networks: The Compaan/Laura Approach [p. 340]; Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing [p. 988]
Kim, S.: Scheduling Reusable Instructions for Power Reduction [p. 148]
Kim, Y.: Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design [p. 352]
Kinniment, D.: Design of Sub-10-Picoseconds On-Chip Time Measurement Circuit [p. 804]
Kocan, F.: Enhancing Reliability of Operational Interconnections in FPGAs [p. 746]
Koelmans, A.: An Asynchronous Synthesis Toolset Using Verilog [p. 724]
Kogel, T.: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms [p. 1256]; A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models [p. 1276]
Kol, R.: Asynchronous Design by Conversion: Converting Synchronous Circuits into Asynchronous Ones [p. 870]
Kolcu, I.: Exploiting Processor Workload Heterogeneity for Reducing Energy Consumption in Chip Multiprocessors [p. 1158]
Kondratyev, A.: Eliminating False Positives in Crosstalk Noise Analysis [p. 1192]; From Synchronous to Asynchronous: An Automatic Approach [p. 1368]
Kong, J.: Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design [p. 352]
Koorapaty, A.: Exploring Logic Block Granularity for Regular Fabrics [p. 468]
Kretzschmar, C.: Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work [p. 512]
Krogh, B.: Hierarchical Adaptive Dynamic Power Management [p. 136]
Krupnova, H.: Mapping Multi-Million Gate SoCs on FPGAs: Industrial Methodology and Experience [p. 1236]
Kubota, H.: Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits [p. 1327]
Kuchcinski, K.: Time-Energy Design Space Exploration for Multi-Layer Memory Architectures [p. 318]
Kuehlmann, A.: Enhanced Diameter Bounding via Structural Transformation [p. 36]
Kukula, J.: Using Counter Example Guided Abstraction Refinement to Find Complex Bugs [p. 156]
Kumar, M.: MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis [p. 922]
Kumar, N.: Profile Guided Management of Code Partitions for Embedded Systems [p. 1396]
Kundu, S.: A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuits [p. 1078]
Kunz, W.: Arithmetic Reasoning in DPLL-Based SAT Solving [p. 30]
Künzli, S.: Workload Characterization Model for Tasks with Variable Execution Demand [p. 1040]
Kuo, W.: Decomposition of Instruction Decoder for Low Power Design [p. 664]
Kwon, Y.: Functional Coverage Metric Generation from Temporal Event Relation Graph [p. 670]
Kyung, C.: Functional Coverage Metric Generation from Temporal Event Relation Graph [p. 670]

Lai, F.: Value-Conscious Cache: Simple Technique for Reducing Cache Access Power [p. 16]
Lamarre, L. de: Automatic Synthesis and Simulation of Continuous-Time ΣΔ Modulators [p. 674]
Lampropoulos, M.: Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique [p. 1372]
Lan, H.: Synthesized Compact Models (SCM) of Substrate Noise Coupling Analysis and Synthesis in Mixed-Signal ICs [p. 836]
Landrault, C.: Design of Routing-Constrained Low Power Scan Chains [p. 62]
Laouamri, O.: Enhancing Testability of System on Chips Using Network Management Protocols [p. 1370]
Lapalme, J.: .NET Framework -- A Solution for the Next Generation Tools for System-Level Modeling and Simulation [p. 732]
Lattanzi, E.: Power-Aware Network Swapping for Wireless Palmtop PCs [p. 858]
Laurent, J.: Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors [p. 666]
Lauwereins, R.: How Can System Level Design Solve the Interconnect Technology Scaling Problem? [p. 332]; Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study [p. 1224]
Lavagno, L.: SoftContract: An Assertion-Based Software Development Process that Enables Design-by-Contract [p. 358]; Implementation of a UMTS Turbo-decoder on a Dynamically Reconfigurable Platform [p. 1218]; From Synchronous to Asynchronous: An Automatic Approach [p. 1368]
Lavigueur, B.: A System Level Exploration Platform and Methodology for Network Applications Based on Configurable Processors [p. 364]
Lee, D.: Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization [p. 494]
Lee, H.: Supporting Cache Coherence in Heterogeneous Multiprocessor Systems [p. 1150]
Lee, J.: Managing Don't Cares in Boolean Satisfiability [p. 260]
Lee, K.: High-Level System Modeling and Architecture Exploration with SystemC on a Network SoC: S3C2510 Case Study [p. 538]
Lee, M.: High-Level System Modeling and Architecture Exploration with SystemC on a Network SoC: S3C2510 Case Study [p. 538]
Leger, G.: A Method for Parameter Extraction of Analog Sine-Wave Signals for Mixed-Signal Built-In-Self-Test Applications [p. 298]; A Digital Test for First-Order ΣΔModulators [p. 706]
Leininger, A.: Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Codes [p. 1302]
Leupers, R.: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms [p. 1256]; A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models [p. 1276]
Leveugle, R.: Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow [p. 590]
Levitan, S.: An Application of Parallel Discrete Event Simulation Algorithms to Mixed Domain System Simulation [p. 1356]
Li, B.: A Novel SAT All-Solutions Solver for Efficient Preimage Computation [p. 272]
Li, H.: Hierarchical Modeling and Simulation of Large Analog Circuits [p. 740]
Li, L.: A Crosstalk Aware Interconnect with Variable Cycle Transmission [p. 102]
Li, R.: Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method [p. 1322]
Li, Y.: State-Preserving vs. Non-State-Preserving Leakage Control in Caches [p. 22]
Lim, S.: Net and Pin Distribution for 3D Package Global Routing [p. 1410]
Lin, A.: Improved Symbolic Simulation by Dynamic Functional Space Partitioning [p. 42]
Lin, C.: Wire Retiming for System-On-Chip by Fixpoint Computation [p. 1092]
Linardis, P.: Efficient Static Compaction of Test Sequence Sets through the Application of Set Covering Techniques [p. 194]
Linten, D.: Extended Subspace Identification of Improper Linear Systems [p. 454]
Liu, J.: Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method [p. 1322]
Liu, X.: Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets [p. 1296]
Liu, Y.: Crosstalk Minimization in Logic Synthesis for PLA [p. 790]
Liuha, P.: GRAAL -- A Development Framework for Embedded Graphics Accelerators [p. 1366]
Liveris, N.: Power Aware Interface Synthesis for Bus-Based SoC Design [p. 864]
Loghi, M.: Analyzing On-Chip Communication in a MPSoC Environment [p. 752]
Lombardi, F.: Fault Tolerance of Programmable Switch Blocks [p. 1358]; Testing of Quantum Dot Cellular Automata Based Designs [p. 1408]
Lorenz, M.: Phase Coupled Code Generation for DSPs Using a Genetic Algorithm [p. 1270]
Lotfi, R.: Systematic Design for Optimization of High-Resolution Pipelined ADCs [p. 678]
Louërat, M.: Automatic Synthesis and Simulation of Continuous-Time ΣΔ Modulators [p. 674]
Lu, Y.: Dynamic Power Management Using Date Buffers [p. 526]
Lv, T.: A Case Study in Networks-on-Chip Design for Embedded Video [p. 770]
Lwin, K.: From Synchronous to Asynchronous: An Automatic Approach [p. 1368]
Lysecky, R.: A Self-Tuning Cache Architecture for Embedded Systems [p. 142]; A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning [p. 480]

Macchiarulo, L.: Issues in Implementing Latency Insensitive Protocols [p. 1390]
Macii, A.: Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning [p. 698]
Macii, E.: A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks [p. 500]; Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning [p. 698]; Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC [p. 700]; Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating [p. 720]; Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing [p. 988]
Maex, K.: How Can System Level Design Solve the Interconnect Technology Scaling Problem? [p. 332]
Mak, T.: Are Our Designs for Testability Features Fault Secure? [p. 714]
Makris, Y.: On Concurrent Error Detection with Bounded Latency in FSMs [p. 596]
Malik, S.: Using a Communication Architecture Specification in an Application-Driven Retargetable Prototyping Platform for Multiprocessing [p. 1244]
Mamagkakis, S.: Dynamic Memory Management Design Methodology for Reduced Memory. Footprint in Multimedia and Wireless Network Applications [p. 532]
Man, H. De: Digital Ground Bounce Reduction by Phase Modulation of the Clock [p. 88]
Mandal, C.: A New Approach to Timing Analysis Using Event Propagation and Temporal Logic [p. 1198]
Manolios, P.: Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements [p. 168]
Mantooth, H.: Identification and Modeling of Nonlinear Dynamic Behavior in Analog Circuits [p. 460]
Marculescu, D.: Local Decisions and Triggering Mechanisms for Dynamic Fault Tolerance [p. 968]
Marculescu, R.: Hierarchical Adaptive Dynamic Power Management [p. 136]; Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures Under Real-Time Constraints [p. 234]; Distributed Multimedia System Design: A Holistic Perspective [p. 1342]
Marek-Sadowska, M.: Eliminating False Positives in Crosstalk Noise Analysis [p. 1192]
Marienfeld, D.: A New Self-Checking Sum-Bit Duplicated Carry-Select Adder [p. 1360]
Marinissen, E.: Nanometer Design: What are the Requirements for Manufacturing Test? [p. 930]
Markov, I.: Breaking Instance-Independent Symmetries in Exact Graph Coloring [p. 324]; Smaller Two-Qubit Circuits for Quantum Communication and Computation [p. 980]; Boosting: Min-Cut Placement with Improved Signal Delay [p. 1098]; High-Performance QuIDD-Based Simulation of Quantum Circuits [p. 1354]
Martens, E.: A Phase-Frequency Transfer Description of Analog and Mixed-Signal Front-End Architectures for System-Level Design [p. 436]
Martin, E.: Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors [p. 666]
Martin, G.: How Can System Level Design Solve the Interconnect Technology Scaling Problem? [p. 332]
Martinez, J.: An Application of Parallel Discrete Event Simulation Algorithms to Mixed Domain System Simulation [p. 1356]
Martini, S.: Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC [p. 564]
Martorell, F.: A Macromodelling Methodology for Efficient High-Level Simulation of Substrate Noise Generation [p. 1362]
Marwedel, P.: Cache-Aware Scratchpad Allocation Algorithm [p. 1264]; Phase Coupled Code Generation for DSPs Using a Genetic Algorithm [p. 1270]
Marzocca, C.: Pseudo-Random Sequence Based Tuning System for Continuous-Time Filters [p. 94]
Masson. P.: A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology [p. 1404]
Masu, K.: ULSI Interconnect Length Distribution Model Considering Core Utilization [p. 1210]
Matarrese, G.: Pseudo-Random Sequence Based Tuning System for Continuous-Time Filters [p. 94]
Mathieu, Y.: CMOS Structures Suitable for Secured Hardware [p. 1414]
Maxiaguine, A.: Workload Characterization Model for Tasks with Variable Execution Demand [p. 1040]
McIntyre, D.: Test Compression and Hardware Decompression for Scan-Based SoCs [p. 716]
Mei, B.: Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study [p. 1224]
Meijs, N. van der: Statistically Aware Buffer Planning [p. 1402]
Mendias, J.: Dynamic Memory Management Design Methodology for Reduced Memory. Footprint in Multimedia and Wireless Network Applications [p. 532]
Mendías, J.: Behavioural Bitwise Scheduling Based on Computational Effort Balancing [p. 684]
Mercer, M.: Balanced Excitation and its Effect on the Fortuitous Detection of Dynamic Defects [p. 1066]
Metra, C.: Are Our Designs for Testability Features Fault Secure? [p. 714]
Meyr, H.: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms [p. 1256]; A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models [p. 1276]
Michalke, T.: Design and Behavioral Modeling Tools for Optical Network-On-Chip [p. 738]
Micheli, G. De: ×pipesCompiler: A Tool for Instantiating Application Specific Networks-on-Chip [p. 884]; Bandwidth-Constrained Mapping of Cores onto NoC Architectures [p. 896]
Mieyeville, F.: Design and Behavioral Modeling Tools for Optical Network-On-Chip [p. 738]
Millberg, M.: Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip [p. 890]
Mine, T.: Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits [p. 1327]
Minz, J.: Net and Pin Distribution for 3D Package Global Routing [p. 1410]
Mir, S.: A 0.18 µm CMOS Implementation of On-Chip Analogue Test Signal Generation from Digital Test Patterns [p. 704]
Miranda, M.: Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies [p. 202]
Mishra, P.: Graph-Based Functional Test Program Generation for Pipelined Processors [p. 182]
Miyoshi, T.: Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis [p. 610]
Mohan, C.: Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent? [p. 668]
Mohapatra, S.: Energy-Aware System Design for Wireless Multimedia [p. 1124]
Molina, M.: Behavioural Bitwise Scheduling Based on Computational Effort Balancing [p. 684]
Molnos, A.: Compositional Memory Systems for Data Intensive Applications [p. 728]
Mondal, A.: A New Approach to Timing Analysis Using Event Propagation and Temporal Logic [p. 1198]
Montiel-Nelson, J.: A Direct Bootstrapped CMOS Large Capacitive-Load Driver Circuit [p. 680]
Mooney, V.: Timing Analysis for Preemptive Multi-Tasking Real-Time Systems with Caches [p. 1034]
Mouchard, G.: A New Optimized Implementation of the SystemC Engine Using Acyclic Scheduling [p. 552]
Mousavi, M.: Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks [p. 384]
Mueller, W.: Model-Based Specification and Execution of Embedded Real-Time Systems [p. 1392]
Muhmenthaler, P.: Nanometer Design: What are the Requirements for Manufacturing Test? [p. 930]; Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Codes [p. 1302]
Müller, D.: Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work [p. 512]
Murali, S.: ×pipesCompiler: A Tool for Instantiating Application Specific Networks-on-Chip [p. 884]; Bandwidth-Constrained Mapping of Cores onto NoC Architectures [p. 896]
Murgai, R.: Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis [p. 610]; Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction [p. 824]
Mycroft, A.: Overhead-free Polymorphism in Network-on-Chip Implementation of Object-Oriented Models [p. 1380]

Nacul, A.: Dynamic Voltage and Cache Reconfiguration for Low Power [p. 1376]
Nagari, A.: A 2.7V 350µW 11-b Algorithmic Analog-to-Digital Converter with Single-Ended Multiplexed Inputs [p. 76]
Nakashima, H.: ULSI Interconnect Length Distribution Model Considering Core Utilization [p. 1210]
Nandi, A.: Extraction of Schematic Array Models for Memory Circuits [p. 570]
Nannarelli, A.: A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters [p. 686]
Narahari, B.: Flexible Software Protection Using Hardware/Software Codesign Techniques [p. 636]
Nardi, A.: Synthesis for Manufacturability: A Sanity Check [p. 796]
Natale, M. de: SoftContract: An Assertion-Based Software Development Process that Enables Design-by-Contract [p. 358]
Näthke, L.: Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques [p. 442]
Navarro, H.: A Direct Bootstrapped CMOS Large Capacitive-Load Driver Circuit [p. 680]
Negreiros, M.: Low Cost Analog Testing of RF Signal Paths [p. 292]
Nelson, J.: Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach [p. 1144]
Niar, S.: Adaptive Prefetching for Multimedia Applications in Embedded Systems [p. 1350]
Nicolaescu, D.: Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors [p. 1374]
Nicolau, A.: Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow [p. 114]; Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures [p. 474]
Nicolescu, G.: .NET Framework -- A Solution for the Next Generation Tools for System-Level Modeling and Simulation [p. 732]
Nicolici, N.: Wrapper Design for Testing IP Cores with Multiple Clock Domains [p. 416]
Nicollini, G.: A 2.7V 350µW 11-b Algorithmic Analog-to-Digital Converter with Single-Ended Multiplexed Inputs [p. 76]
Niemann, J.: A Mapping Strategy for Resource-Efficient Network Processing on Multiprocessor SoCs [p. 758]
Nieuwland, A.: Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work [p. 512]
Niittylahti, J.: Scalar Metric for Temporal Locality and Estimation of Cache Performance [p. 730]
Nikitovic, M.: A Low Power Strategy for Future Mobile Terminals [p. 702]
Nilsson, E.: Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip [p. 890]
Nohl, A.: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms [p. 1256]
Nourani, M.: SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance [p. 710]; Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression [p. 1284]

O'Connor, I.: Extremely Low-Power Logic [p. 656]; Design and Behavioral Modeling Tools for Optical Network-On-Chip [p. 738]
Öberg, J.: System Design for DSP Applications Using the MASIC Methodology [p. 630]
Ocheretnij, V.: A New Self-Checking Sum-Bit Duplicated Carry-Select Adder [p. 1360]
Oh, C.: False-Noise Analysis for Domino Circuits [p. 784]
Okada, K.: ULSI Interconnect Length Distribution Model Considering Core Utilization [p. 1210]
Olbrich, M.: Placement Using a Localization Probability Model (LPM) [p. 1412]
Oliveira, A.: A Probabilistic Method for the Computation of Testability of RTL Constructs [p. 176]
Omaña, M.: Are Our Designs for Testability Features Fault Secure? [p. 714]
Ong, C.: Random Jitter Extraction Technique in a Multi-Gigahertz Signal [p. 286]
Orailoglu, A.: Scan Power Minimization through Stimulus and Response Transformations [p. 404]; CircularScan: A Scan Architecture for Test Cost Reduction [p. 1290]
Osseiran, A.: Status of IEEE Testability Standards 1149.4, 1532 and 1149.6 [p. 1184]
Otten, R.: Statistically Aware Buffer Planning [p. 1402]

Pacalet, R.: CMOS Structures Suitable for Secured Hardware [p. 1414]
Paccagnella, A.: Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA [p. 584]
Padmanaban, S.: Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults [p. 50]
Pai, A.: Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays [p. 1230]
Panda, R.: False-Noise Analysis for Domino Circuits [p. 784]
Papachristou C.: Test Compression and Hardware Decompression for Scan-Based SoCs [p. 716]; Designing Self Test Programs for Embedded DSP Cores [p. 816]
Parameswaran, S.: MINCE: Matching INstructions with Combinational Equivalence for Extensible Processor [p. 1020]
Parikh, D.: State-Preserving vs. Non-State-Preserving Leakage Control in Caches [p. 22]
Paschalis, A.: Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors [p. 578]
Passerone, C.: Implementation of a UMTS Turbo-decoder on a Dynamically Reconfigurable Platform [p. 1218]
Patel, K.: Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC [p. 700]
Pathak, M.: Net and Pin Distribution for 3D Package Global Routing [p. 1410]
Paul, J.: Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach [p. 1144]
Paulin, P.: Chips of the Future: Soft, Crunchy or Hard? [p. 844]
Pêcheux, F.: STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores [p. 712]
Pedram, M.: Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Trade-Off Based on the Ratio of Off-Chip Access to On-Chip Computation Times [p. 4]; Power Minimization in a Backlit TFT-LCD Display by Concurrent Brightness and Contrast Scaling [p. 252]; A Game Theoretic Approach to Low Energy Wireless Video Streaming [p. 696]; Distributed Multimedia System Design: A Holistic Perspective [p. 1342]
Peng, Z.: Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems [p. 518]; Design Optimization of Multi-Cluster Embedded Systems for Real-Time Applications [p. 1028]; Quasi-Static Scheduling for Real-Time Systems with Hard and Soft Tasks [p. 1176]
Peralías, E.: Digital Background Gain Error Correction in Pipeline ADCs [p. 82]
Perbellini, G.: Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC [p. 564]
Pereira, C.: Energy-Aware System Design for Wireless Multimedia [p. 1124]
Pérez, D.: A New Optimized Implementation of the SystemC Engine Using Acyclic Scheduling [p. 552]
Pestana, S.: Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach [p. 764]
Phillips, J.: Poor Man's TBR: A Simple Model Reduction Scheme [p. 938]
Pieper, J.: Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach [p. 1144]
Piguet, C.: Extremely Low-Power Logic [p. 656]; Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing [p. 988]
Pileggi, L.: Exploring Logic Block Granularity for Regular Fabrics [p. 468]; An Interconnect Channel Design Methodology for High Performance Integrated Circuits [p. 1138]
Pinello, C.: Fault-Tolerant Deployment of Embedded Software for Cost-Sensitive Real-Time Feedback-Control Applications [p. 1164]
Pintelon, R.: Extended Subspace Identification of Improper Linear Systems [p. 454]
Pisharath, J.: Data Windows: A Data-Centric Approach for Query Execution in Memory-Resident Databases [p. 1352]
Plas, G. Van Der: Digital Ground Bounce Reduction by Phase Modulation of the Clock [p. 88]
Poirier, R.: An Arithmetic Structure for Test Data Horizontal Compression [p. 428]
Pol, E.: Energy-Aware System Design for Wireless Multimedia [p. 1124]
Pomeranz, I.: Level of Similarity: A Metric for Fault Collapsing [p. 56]; Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis [p. 68]
Poncino, M.: Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC [p. 564]; Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC [p. 700]
Pop, P.: Design Optimization of Multi-Cluster Embedded Systems for Real-Time Applications [p. 1028]
Porrmann, M.: A Mapping Strategy for Resource-Efficient Network Processing on Multiprocessor SoCs [p. 758]
Portal, J.: A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology [p. 1404]
Posadas, H.: System-Level Performance Analysis in SystemC [p. 378]; Platform Based on Open-Source Cores for Industrial Applications [p. 1014]
Post, G.: A SystemC-Based Verification Methodology for Complex Wireless Software IP [p. 544]
Pozzi, L.: Operating System Support for Interface Virtualization of Reconfigurable Coprocessors [p. 748]
Pradhan, D.: MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions [p. 1388]
Pravossoudovitch, S.: Design of Routing-Constrained Low Power Scan Chains [p. 62]
Prenat, G.: A 0.18 µm CMOS Implementation of On-Chip Analogue Test Signal Generation from Digital Test Patterns [p. 704]
Proust, P.: High Security Smartcards [p. 228]
Provost, J.: CMOS Structures Suitable for Secured Hardware [p. 1414]

Qi, Z.: Hierarchical Modeling and Simulation of Large Analog Circuits [p. 740]
Quinn, D.: A System Level Exploration Platform and Methodology for Network Applications Based on Configurable Processors [p. 364]

Radetzki, M.: Measurement of IP Qualification Costs and Benefits [p. 996]
Radulescu, A.: Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach [p. 764]; An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration [p. 878]
Rahimi, K.: Timing Correction and Optimization with Adaptive Delay Sequential Elements [p. 1416]
Rajski, J.: Nanometer Design: What are the Requirements for Manufacturing Test? [p. 930]
Ramani, A.: Breaking Instance-Independent Symmetries in Exact Graph Coloring [p. 324]
Ramesh, S.: Synchronous Protocol Automata: A Framework for Modelling and Verification of SoC Communication Architectures [p. 390]
Ran, Y.: Eliminating False Positives in Crosstalk Noise Analysis [p. 1192]
Ranjan, M.: Fast, Layout-Inclusive Analog Circuit Synthesis Using Pre-Compiled Parasitic-Aware Symbolic Performance Models [p. 604]
Raudvere, T.: Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits [p. 690]
Ray, T.: A SystemC-Based Verification Methodology for Complex Wireless Software IP [p. 544]
Raychowdhury, A.: Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis [p. 708]
Re, A. Del: A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters [p. 686]
Re, M.: A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters [p. 686]
Rebaudengo, M.: Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA [p. 584]
Reda, S.: Boosting: Min-Cut Placement with Improved Signal Delay [p. 1098]
Reddy, S.: Level of Similarity: A Metric for Fault Collapsing [p. 56]; Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis [p. 68]; Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis [p. 610]
Reed, D.: An Application of Parallel Discrete Event Simulation Algorithms to Mixed Domain System Simulation [p. 1356]
Rekhi, S.: Microarchitecture Development via Metropolis Successive Platform Refinement [p. 346]
Ren, Z.: Hierarchical Adaptive Dynamic Power Management [p. 136]
Renaudin, M.: High Security Smartcards [p. 228]
Reorda, M. Sonza: Automatic Generation of Validation Stimuli for Application-Specific Processors [p. 188]; Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA [p. 584]
Righetti, L.: Operating System Support for Interface Virtualization of Reconfigurable Coprocessors [p. 748]
Rigo, S.: Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology [p. 734]
Rijpkema, E.: Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach [p. 764]; An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration [p. 878]
Rizk, H.: Designing Self Test Programs for Embedded DSP Cores [p. 816]
Rolíndez, L.: A 0.18 µm CMOS Implementation of On-Chip Analogue Test Signal Generation from Digital Test Patterns [p. 704]
Rosa, A. La: Implementation of a UMTS Turbo-decoder on a Dynamically Reconfigurable Platform [p. 1218]
Rosenstiel, W.: SystemC and System Verilog: Where do They Fit? Where are they going? [p. 122]; Communication Analysis for System on Chip Design [p. 648]; Measurement of IP Qualification Costs and Benefits [p. 996]
Rosinger, P.: Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique [p. 1372]
Ross, J.: Efficient Mixed-Domain Behavioural Modeling of Ferromagnetic Hysteresis Implemented in VHDL-AMS [p. 742]
Rosselló, J.: A Compact Propagation Delay Model for Deep-Submicron CMOS Technologies including Crosstalk [p. 954]
Rouzeyre, B.: An Arithmetic Structure for Test Data Horizontal Compression [p. 428]
Roy, K.: Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis [p. 708]
Roychowdhury, J.: Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction [p. 824]
Rückert, U.: A Mapping Strategy for Resource-Efficient Network Processing on Multiprocessor SoCs [p. 758]
Rueda, A.: Digital Background Gain Error Correction in Pipeline ADCs [p. 82]; A Method for Parameter Extraction of Analog Sine-Wave Signals for Mixed-Signal Built-In-Self-Test Applications [p. 298]; A Digital Test for First-Order ΣΔModulators [p. 706]
Ruiz-Sautua, R.: Behavioural Bitwise Scheduling Based on Computational Effort Balancing [p. 684]
Russell, G.: Design of Sub-10-Picoseconds On-Chip Time Measurement Circuit [p. 804]

Safarpour, S.: Managing Don't Cares in Boolean Satisfiability [p. 260]
Sakallah, K.: Breaking Instance-Independent Symmetries in Exact Graph Coloring [p. 324]
Sakanushi, K.: Architecture-Level Performance Estimation for IP-Based Embedded Systems [p. 1002]
Sampath, H.: Fast, Layout-Inclusive Analog Circuit Synthesis Using Pre-Compiled Parasitic-Aware Symbolic Performance Models [p. 604]; Accurate Estimation of Parasitic Capacitances in Analog Circuits [p. 1364]
Sánchez, C.: Platform Based on Open-Source Cores for Industrial Applications [p. 1014]
Sánchez, P.: System-Level Performance Analysis in SystemC [p. 378]; Platform Based on Open-Source Cores for Industrial Applications [p. 1014]
Sander, I.: Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits [p. 690]
Sangiovanni-Vincentelli, A.: Microarchitecture Development via Metropolis Successive Platform Refinement [p. 346]; A Methodology for System-Level Analog Design Space Exploration [p. 676]; Synthesis for Manufacturability: A Sanity Check [p. 796]; Fault-Tolerant Deployment of Embedded Software for Cost-Sensitive Real-Time Feedback-Control Applications [p. 1164]
Sankaranarayanan, K.: State-Preserving vs. Non-State-Preserving Leakage Control in Caches [p. 22]
Santos, M.: A Probabilistic Method for the Computation of Testability of RTL Constructs [p. 176]
Sapatnekar, S.: Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming [p. 622]; Fast Comparisons of Circuit Implementations [p. 910]
Sapei, F.: Impact of Test Point Insertion on Silicon Area and Timing during Layout [p. 810]
Sbeyti, H.: Adaptive Prefetching for Multimedia Applications in Embedded Systems [p. 1350]
Scharwaechter, H.: A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models [p. 1276]
Schattkowsky, T.: Model-Based Specification and Execution of Embedded Real-Time Systems [p. 1392]
Schaumont, P.: Interactive Cosimulation with Partial Evaluation [p. 642]; Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing [p. 988]
Schlebusch, H.: System Verilog for VHDL Users [p. 1334]
Schlichtmann, U.: Extremely Low-Power Logic [p. 656]
Schmit, H.: An Interconnect Channel Design Methodology for High Performance Integrated Circuits [p. 1138]
Schmitz, M.: Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems [p. 518]
Sciuto, D.: SystemC and System Verilog: Where do They Fit? Where are they going? [p. 122]
Seceleanu, T.: Aspects of Formal and Graphical Design of a Bus System [p. 396]
Seetharaman, D.: A SystemC-Based Verification Methodology for Complex Wireless Software IP [p. 544]
Segura, J.: A Compact Propagation Delay Model for Deep-Submicron CMOS Technologies including Crosstalk [p. 954]
Sehgal, A.: Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures [p. 422]
Senn, E.: Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors [p. 666]
Seshadri, B.: Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis [p. 68]
Sezer, U.: Configuration-Sensitive Process Scheduling for FPGA-Based Computing Platforms [p. 486]
Shang, D.: An Asynchronous Synthesis Toolset Using Verilog [p. 724]
Shende, V.: Smaller Two-Qubit Circuits for Quantum Communication and Computation [p. 980]
Sheng, S.: A Novel SAT All-Solutions Solver for Efficient Preimage Computation [p. 272]
Shi, C.: Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation [p. 1310]
Shim, K.: High-Level System Modeling and Architecture Exploration with SystemC on a Network SoC: S3C2510 Case Study [p. 538]
Shin, C.: Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design [p. 352]
Shoaei, O.: Systematic Design for Optimization of High-Resolution Pipelined ADCs [p. 678]
Shogan, S.: Compact Binaries with Code Compression in a Software Dynamic Translator [p. 1052]
Shukla, S.: Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks [p. 384]
Siebenborn, A.: Communication Analysis for System on Chip Design [p. 648]
Silburt, A.: Chips of the Future: Soft, Crunchy or Hard? [p. 844]
Silveira, L.: Poor Man's TBR: A Simple Model Reduction Scheme [p. 938]
Simha, R.: Flexible Software Protection Using Hardware/Software Codesign Techniques [p. 636]
Sinanoglu, O.: Scan Power Minimization through Stimulus and Response Transformations [p. 404]
Singh, A.: Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits [p. 690]
Singh, M.: Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures [p. 1008]
Singh, S.: A Demonstration of Co-Design and Co-Verification in a Synchronous Language [p. 1394]
Skadron, K.: Hybrid Architectural Dynamic Thermal Management [p. 10]; State-Preserving vs. Non-State-Preserving Leakage Control in Caches [p. 22]
Sogomonyan, E.: A New Self-Checking Sum-Bit Duplicated Carry-Select Adder [p. 1360]
Soma, R.: Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Trade-Off Based on the Ratio of Off-Chip Access to On-Chip Computation Times [p. 4]
Someren, H. van: A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models [p. 1276]
Sosa, J.: A Direct Bootstrapped CMOS Large Capacitive-Load Driver Circuit [p. 680]
Sotiriou, C.: Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits [p. 672]; From Synchronous to Asynchronous: An Automatic Approach [p. 1368]
Soudris, D.: Dynamic Memory Management Design Methodology for Reduced Memory. Footprint in Multimedia and Wireless Network Applications [p. 532]
Sourgen, L.: High Security Smartcards [p. 228]
Sowmya, A.: Synchronous Protocol Automata: A Framework for Modelling and Verification of SoC Communication Architectures [p. 390]
Spirakis, G.: Opportunities and Challenges in Building Silicon Products in 65nm and Beyond [p. 2]
Srinivasan, G.: Efficient Test Strategy for TDMA Power Amplifiers Using Transient Current Measurements: Uses and Benefits [p. 280]
Srinivasan, R.: A Framework for Battery-Aware Sensor Management [p. 962]
Srinivasan, S.: Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements [p. 168]
Srivastava, A.: Concurrent Sizing, Vdd and V_th Assignment for Low-Power Design [p. 718]
Srouji, J.: SystemC and System Verilog: Where do They Fit? Where are they going? [p. 122]
Stan, M.: State-Preserving vs. Non-State-Preserving Leakage Control in Caches [p. 22]; A Unified Design Space for Regular Parallel Prefix Adders [p. 1386]
Stanley-Marbell, P.: Local Decisions and Triggering Mechanisms for Dynamic Fault Tolerance [p. 968]
Stefanov, T.: System Design Using Kahn Process Networks: The Compaan/Laura Approach [p. 340]
Stoffel, D.: Arithmetic Reasoning in DPLL-Based SAT Solving [p. 30]; Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor [p. 162]
Suh, T.: Supporting Cache Coherence in Heterogeneous Multiprocessor Systems [p. 1150]
Sunter, S.: Status of IEEE Testability Standards 1149.4, 1532 and 1149.6 [p. 1184]
Sur-Kolay, S.: A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuits [p. 1078]
Susin, A.: Low Cost Analog Testing of RF Signal Paths [p. 292]
Swan, S.: SystemC and System Verilog: Where do They Fit? Where are they going? [p. 122]
Sylvester, D.: Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization [p. 494]; Concurrent Sizing, Vdd and V_th Assignment for Low-Power Design [p. 718]
Szymanek, R.: Time-Energy Design Space Exploration for Multi-Layer Memory Architectures [p. 318]

Taherzadeh-Sani, M.: Systematic Design for Optimization of High-Resolution Pipelined ADCs [p. 678]
Tahoori, M.: Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis [p. 610]; Fault Tolerance of Programmable Switch Blocks [p. 1358]; Testing of Quantum Dot Cellular Automata Based Designs [p. 1408]
Takeuchi, Y.: Architecture-Level Performance Estimation for IP-Based Embedded Systems [p. 1002]
Talpin, J.: Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks [p. 384]
Tan, S.: Hierarchical Modeling and Simulation of Large Analog Circuits [p. 740]
Tan, Y.: Timing Analysis for Preemptive Multi-Tasking Real-Time Systems with Caches [p. 1034]
Taylor, R.: Co-Processor Synthesis: A New Methodology for Embedded Software Acceleration [p. 682]
Tehranipour, M.: Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression [p. 1284]
Teixeira, J.: A Probabilistic Method for the Computation of Testability of RTL Constructs [p. 176]
Temam, O.: A New Optimized Implementation of the SystemC Engine Using Acyclic Scheduling [p. 552]
Thapar, K.: Nanometer Design: What are the Requirements for Manufacturing Test? [p. 930]
Theobald, M.: Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures [p. 1008]
Thepayasuwan, N.: Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip [p. 108]
Thid, R.: Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip [p. 890]
Thiele, L.: Workload Characterization Model for Tasks with Variable Execution Demand [p. 1040]
Thomas, D.: Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach [p. 1144]
Tiri, K.: A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation [p. 246]
Tirumurti, C.: A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuits [p. 1078]
Tiwari, A.: Saving Power by Mapping Finite-State Machines into Embedded Memory Blocks in FPGAs [p. 916]
Tomko, K.: Saving Power by Mapping Finite-State Machines into Embedded Memory Blocks in FPGAs [p. 916]
Tragoudas, S.: Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults [p. 50]
Trylus, H.: Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor [p. 162]
Tsai, J.: Thermal and Power Integrity Based Power/Ground Networks Optimization [p. 830]
Tseng, H.: Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis [p. 1072]
Tsui, C.: Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus [p. 130]
Tual, J.: High Security Smartcards [p. 228]
Tuna, M.: STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores [p. 712]
Turjan, A.: System Design Using Kahn Process Networks: The Compaan/Laura Approach [p. 340]

Ueda, K.: Architecture-Level Performance Estimation for IP-Based Embedded Systems [p. 1002]

Vahid, F.: A Self-Tuning Cache Architecture for Embedded Systems [p. 142]; Automatic Tuning of Two-Level Caches to Embedded Applications [p. 208]; Low Static-Power Frequent-Value Data Caches [p. 214]; Using a Victim Buffer in an Application-Specific Memory Hierarchy [p. 220]; A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning [p. 480]
Vandersteen, G.: Extended Subspace Identification of Improper Linear Systems [p. 454]
Van Antwerpen, H.: Energy-Aware System Design for Wireless Multimedia [p. 1124]
van Berkel, K.: Chips of the Future: Soft, Crunchy or Hard? [p. 844]
van de Steeg, P.: How Can System Level Design Solve the Interconnect Technology Scaling Problem? [p. 332]
Vassiliadis, S.: GRAAL -- A Development Framework for Embedded Graphics Accelerators [p. 1366]
Vázquez, D.: A Method for Parameter Extraction of Analog Sine-Wave Signals for Mixed-Signal Built-In-Self-Test Applications [p. 298]
Vázquez, J.: Power Supply Noise Monitor for Signal Integrity Faults [p. 1406]
Veidenbaum, A.: Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors [p. 1374]
Velev, M.: Exploiting Signal Unobservability for Efficient Translation to CNF in Formal Verification of Microprocessors [p. 266]
Vellanki, P.: A Power and Performance Model for Network-on-Chip Architectures [p. 1250]
Vemuri, R.: Fast, Layout-Inclusive Analog Circuit Synthesis Using Pre-Compiled Parasitic-Aware Symbolic Performance Models [p. 604]; A Fast Algorithm for Finding Maximal Empty Rectangles for Dynamic FPGA Placement [p. 744]; Accurate Estimation of Parasitic Capacitances in Analog Circuits [p. 1364]
Veneris, A.: Managing Don't Cares in Boolean Satisfiability [p. 260]
Venkataraghavan, P.: A SystemC-Based Verification Methodology for Complex Wireless Software IP [p. 544]
Venkataraman, S.: Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis [p. 68]
Venkatasubramanian, N.: Energy-Aware System Design for Wireless Multimedia [p. 1124]
Verbauwhede, I.: A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation [p. 246]; Interactive Cosimulation with Partial Evaluation [p. 642]; Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing [p. 988]
Vergniault, M.: Nanometer Design: What are the Requirements for Manufacturing Test? [p. 930]
Verhaegen, W.: Fast, Layout-Inclusive Analog Circuit Synthesis Using Pre-Compiled Parasitic-Aware Symbolic Performance Models [p. 604]
Verkest, D.: Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study [p. 1224]
Verma, M.: Cache-Aware Scratchpad Allocation Algorithm [p. 1264]
Vernalde, S.: Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study [p. 1224]
Viamontes, G.: High-Performance QuIDD-Based Simulation of Quantum Circuits [p. 1354]
Viana, P.: Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology [p. 734]
Viaud, E.: STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores [p. 712]
Vijaykrishnan, N.: A Crosstalk Aware Interconnect with Variable Cycle Transmission [p. 102]; Scheduling Reusable Instructions for Power Reduction [p. 148]
Villar, E.: System-Level Performance Analysis in SystemC [p. 378]
Violante, M.: Automatic Generation of Validation Stimuli for Application-Specific Processors [p. 188]; Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA [p. 584]
Virazel, A.: Design of Routing-Constrained Low Power Scan Chains [p. 62]
von Vignau, R.: Energy-Aware System Design for Wireless Multimedia [p. 1124]
Vörg, A.: Measurement of IP Qualification Costs and Benefits [p. 996]
Vranken, H.: Impact of Test Point Insertion on Silicon Area and Timing during Layout [p. 810]
Vrudhula, S.: A Framework for Battery-Aware Sensor Management [p. 962]
Vuletic, M.: Operating System Support for Interface Virtualization of Reconfigurable Coprocessors [p. 748]

Wagner, F.: Unified Component Integration Flow for Multi-Processor SoC Design and Validation [p. 1132]
Wahlen, O.: A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models [p. 1276]
Waldschmidt, K.: Refinement of Mixed-Signal Systems with Affine Arithmetic [p. 372]
Wambacq, P.: Digital Ground Bounce Reduction by Phase Modulation of the Clock [p. 88]
Wan, B.: Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation [p. 1310]
Wang, K.: Crosstalk Minimization in Logic Synthesis for PLA [p. 790]
Wang, L.: Improved Symbolic Simulation by Dynamic Functional Space Partitioning [p. 42]; Random Jitter Extraction Technique in a Multi-Gigahertz Signal [p. 286]; Regression Simulation: Applying Path-Based Learning in Delay Test and Post-Silicon Validation [p. 692]; Pattern Selection for Testing of Deep Sub-Micron Timing Defects [p. 1060]
Wang, S.: Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets [p. 1296]
Wang, T.: Thermal and Power Integrity Based Power/Ground Networks Optimization [p. 830]
Wang, Z.: Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks [p. 312]
Wang, Z.: Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction [p. 824]
Watanabe, T.: Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits [p. 1327]
Watanabe, Y.: Eliminating False Positives in Crosstalk Noise Analysis [p. 1192]
Wedler, M.: Arithmetic Reasoning in DPLL-Based SAT Solving [p. 30]
Wehmeyer, L.: Cache-Aware Scratchpad Allocation Algorithm [p. 1264]
Wehn, N.: Chips of the Future: Soft, Crunchy or Hard? [p. 844]
Weigel, R.: SubCALM: A Program for Hierarchical Substrate Coupling Simulation on Floorplan Level [p. 616]
Westall, F.: Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays [p. 1230]
Westerlund, T.: Aspects of Formal and Graphical Design of a Bus System [p. 396]
Wieferink, A.: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms [p. 1256]
Wielage, P.: An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration [p. 878]
Wilson, P.: Efficient Mixed-Domain Behavioural Modeling of Ferromagnetic Hysteresis Implemented in VHDL-AMS [p. 742]
Wilson, R.: How Can System Level Design Solve the Interconnect Technology Scaling Problem? [p. 332]
Wingfield, J.: Balanced Excitation and its Effect on the Fortuitous Detection of Dynamic Defects [p. 1066]
Winkelmann, K.: Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor [p. 162]
Wolf, W.: A Case Study in Networks-on-Chip Design for Embedded Video [p. 770]
Wolff, F.: Test Compression and Hardware Decompression for Scan-Based SoCs [p. 716]; Designing Self Test Programs for Embedded DSP Cores [p. 816]
Wong, M.: Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus [p. 1104]
Wong, S.: Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus [p. 130]
Wu, A.: Decomposition of Instruction Decoder for Low Power Design [p. 664]
Wunderlich, H.: Impact of Test Point Insertion on Silicon Area and Timing during Layout [p. 810]

Xiong, J.: Full-Chip Multilevel Routing for Power and Signal Integrity [p. 1116]
Xu, A.: An Interconnect Channel Design Methodology for High Performance Integrated Circuits [p. 1138]
Xu, J.: A Case Study in Networks-on-Chip Design for Embedded Video [p. 770]
Xu, Q.: Wrapper Design for Testing IP Cores with Multiple Clock Domains [p. 416]

Yakovlev, A.: An Asynchronous Synthesis Toolset Using Verilog [p. 724]
Yang, C.: Value-Conscious Cache: Simple Technique for Reducing Cache Access Power [p. 16]
Yang, J.: Low Static-Power Frequent-Value Data Caches [p. 214]
Yelamanchili, V.: Accurate Estimation of Parasitic Capacitances in Analog Circuits [p. 1364]
Yoo, S.: Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent Software [p. 1382]
Youssef, M.: Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent Software [p. 1382]

Zafalon, R.: Analyzing On-Chip Communication in a MPSoC Environment [p. 752]
Zambolin, P.: Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA [p. 584]
Zambreno, J.: Flexible Software Protection Using Hardware/Software Codesign Techniques [p. 636]
Zeng, X.: Direct Nonlinear Order Reduction with Variational Analysis [p. 1316]; Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method [p. 1322]
Zhan, Y.: Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming [p. 622]
Zhang, C.: A Self-Tuning Cache Architecture for Embedded Systems [p. 142]; Low Static-Power Frequent-Value Data Caches [p. 214]; Using a Victim Buffer in an Application-Specific Memory Hierarchy [p. 220]
Zhang, R.: Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies [p. 904]
Zhang, Y.: State-Preserving vs. Non-State-Preserving Leakage Control in Caches [p. 22]; Task Feasibility Analysis and Dynamic Voltage Scaling in Fault-Tolerant Real-Time Embedded Systems [p. 1170]
Zhong, L.: Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies [p. 904]
Zhou, D.: Direct Nonlinear Order Reduction with Variational Analysis [p. 1316]; Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method [p. 1322]
Zhou, H.: Wire Retiming for System-On-Chip by Fixpoint Computation [p. 1092]
Zhou, S.: Profile Guided Management of Code Partitions for Embedded Systems [p. 1396]
Zhou, X.: Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method [p. 1322]
Zhu, X.: Using a Communication Architecture Specification in an Application-Driven Retargetable Prototyping Platform for Multiprocessing [p. 1244]
Ziegler, M.: A Unified Design Space for Regular Parallel Prefix Adders [p. 1386]
Zissulescu, C.: System Design Using Kahn Process Networks: The Compaan/Laura Approach [p. 340]
Ziv, A.: Stimuli Generation with Late Binding of Values [p. 558]
Zolotov, V.: False-Noise Analysis for Domino Circuits [p. 784]