Sessions: [Keynotes] [2.2] [2.3] [2.4] [2.5] [2.6] [2.7] [2.8] [3.2] [3.3] [3.4] [3.5] [3.6] [3.7] [3.8] [4.2] [4.3] [4.4] [4.5] [4.6] [4.7] [5.1] [5.2] [5.3] [5.4] [5.5] [5.6] [5.7] [6.1] [6.2] [6.3] [6.4] [6.5] [6.6] [6.7] [7.1] [7.2] [7.3] [7.4] [7.5] [7.6] [7.7] [8.1] [8.2] [8.3] [8.4] [8.5] [8.6] [8.7] [8.8] [9.1] [9.2] [9.3] [9.4] [9.5] [9.6] [9.7] [10.1] [10.2] [10.3] [10.4] [10.5] [10.6] [10.7] [10.8] [11.1] [11.2] [11.3] [11.4] [11.5] [11.6] [11.7] [11.8] [12.1] [12.2] [12.3] [12.4] [12.5] [12.6] [12.7] [12.8]

DATE Executive Committee
DATE Sponsors Committee
Technical Program Topic Chairs
Technical Program Committee
Reviewers
Foreword
Best Paper Awards
PH.D. Forum
Call for Papers: DATE 2014

Keynotes

Smart Systems for Internet of Things [p. 1]

Benedetto Vigna

Creating a Sustainable Information and Communication Infrastructure [p. 2]

Massoud Pedram

2.2: Acceleration and Verification of ESL and Analog Systems

Moderators: Alper Sen - Bogazici University, TR; Daniel Grosse - University of Bremen, DE

Optimized Out-of-Order Parallel Discrete Event Simulation Using Predictions [p. 3]

Weiwei Chen and Rainer D&omuml;er

Parallel Programming with SystemC for Loosely Timed Models: A Non-Intrusive Approach [p. 9]

Matthieu Moy

Accuracy vs Speed Tradeoffs in the Estimation of Fixed-Point Errors on Linear Time-Invariant Systems [p. 15]

David Novo, Sara El Alaoui and Paolo Ienne

Runtime Verification of Nonlinear Analog Circuits Using Incremental Time-Augmented RRT Algorithm [p. 21]

Seyed Nematollah Ahmadyan, Jayanand Asok Kumar and Shobha Vasudevan

An Automated Parallel Simulation Flow for Heterogeneous Embedded Systems [p. 27]

Seyed Hosein, Attarzadeh Niaki and Ingo Sander

Mutation Analysis with Coverage Discounting [p. 31]

Peter Lisherness, Nicole Lesperance and Kwang-Ting (Tim) Cheng

Scalable Fault Localization for SystemC TLM Designs [p. 35]

Hoang M. Le, Daniel Große and Rolf Drechsler

2.3: Energy Optimization in Multi-core Systems

Moderators: Thidapat Chantem - Utah State University, US; William Fornaciari - Politecnico di Milano, IT

Cherry-Picking: Exploiting Process Variations in Dark-Silicon Homogeneous Chip Multi-Processors [p. 39]

Bharathwaj Raghunathan, Yatish Turakhia, Siddharth Garg and Diana Marculescu

Energy Optimization with Worst-Case Deadline Guarantee for Pipelined Multiprocessor Systems [p. 45]

Gang Chen, Kai Huang, Christian Buckl and Alois Knoll

Self-Adaptive Hybrid Dynamic Power Management for Many-Core Systems [p. 51]

Muhammad Shafique, Benjamin Vogel and Jörg Henkel

SmartCap: User Experience-Oriented Power Adaptation for Smartphone's Application Processor [p. 57]

Xueliang Li, Guihai Yan, Yinhe Han and Xiaowei Li

Runtime Power Estimation of Mobile AMOLED Displays [p. 61]

Dongwon Kim, Wonwoo Jung and Hojung Cha

2.4: Memory and Cache Architectures

Moderators: Georgi Gaydadjiev - Chalmers University of Technology, SE; Todd Austin - Michigan University Ann Arbor, US

AVICA: An Access-time Variation Insensitive L1 Cache Architecture [p. 65]

Seokin Hong and Soontae Kim

Dual-addressing Memory Architecture for Two-dimensional Memory Access Patterns [p. 71]

Yen-Hao Chen and Yi-Yu Liu

Adaptive Cache Management for a Combined SRAM and DRAM Cache Hierarchy for Multi-cores [p. 77]

Fazal Hameed, Lars Bauer and Jörg Henkel

Combining RAM Technologies for Hard-error Recovery in L1 Data Caches Working at Very-low Power Modes [p. 83]

Vicente Lorente, Alejandro Valero, Julio Sahuquillo, Salvador Petit, Ramon Canal, Pedro López and José Duato

A Dual Grain Hit-Miss Detector for Large Die-Stacked DRAM Caches [p. 89]

Michel El-Nacouzi, Islam Atta, Myrto Papadopoulou, Jason Zebchuk, Natalie Enright Jerger and Andreas Moshovos

Reducing Writes in Phase-Change Memory Environments by Using Efficient Cache Replacement Policies [p. 93]

Roberto Rodríguez-Rodríguez, Fernando Castro, Daniel Chaver, Luis Pinuel and Francisco Tirado

2.5: Communications, Multimedia, and Consumer Electronics

Moderators: Theocharis Theocharides - University of Cyprus, CY; Amer Baghdadi - Telecom Bretagne/ Lab-STICC, FR

Low Complexity QR-Decomposition Architecture Using the Logarithmic Number System [p. 97]

Jochen Rust, Frank Ludwig and Steffen Paul

Perceptual Quality Preserving SRAM Architecture for Color Motion Pictures [p. 103]

Wen Yueh, Minki Cho and Saibal Mukhopadhyay

Parameterized Area-efficient Multi-standard Turbo Decoder [p. 109]

Purushotham Murugappa, Amer Baghdadi and Michel Jézéquel

An H.264 Quad-FullHD Low-Latency Intra Video Encoder [p. 115]

Muhammad Usman Karim Khan, Jan Micha Borrmann, Lars Bauer, Muhammad Shafique and Jörg Henkel

A 100 GOPS ASP Based Baseband Processor for Wireless Communication [p. 121]

Zhu Ziyuan, Tang Shan, Su Yongtao, Han Juan, Sun Gang and Shi Jinglin

Hardware-Software Collaborative Complexity Reduction Scheme for the Emerging HEVC Intra Encoder [p. 125]

Muhammad Usman Karim Khan, Muhammad Shafique, Mateus Grellert and Jörg Henkel

2.6: HOT TOPIC: Reliability Challenges of Real-time Systems in Forthcoming Technology Nodes

Organizers and Moderators: Said Hamdioui - Delft University of Technology, NL; Dimitris Gizopoulos - University of Athens, GR

Reliability Challenges of Real-Time Systems in Forthcoming Technology Nodes [p. 129]

Said Hamdioui, Dimitris Gizopoulos, Groeseneken Guido, Michael Nicolaidis, Arnaud Grasset, Philippe Bonnot

2.7: Safety Critical Real-Time Systems

Moderators: Michael Paulitsch - EADS, DE; Giuseppe Lipari - ENS - Cachan, FR

Sensitivity Analysis for Arbitrary Activation Patterns in Real-time Systems [p. 135]

Moritz Neukirchner, Sophie Quinton, Tobias Michaels, Philip Axer and Rolf Ernst

PT-AMC: Integrating Preemption Thresholds into Mixed-Criticality Scheduling [p. 141]

Qingling Zhao, Zonghua Gu and Haibo Zeng

An Elastic Mixed-Criticality Task Model and Its Scheduling Algorithm [p. 147]

Hang Su and Dakai Zhu

An Open Platform for Mixed-Criticality Real-time Ethernet [p. 153]

Gonzalo Carvajal and Sebastian Fischmeister

2.8: HOT TOPIC: IP Subsystems: The Next Productivity Wave?

Organizers and Moderators: Wido Kruijtzer - Synopsys, NL; Luciano Lavagno - Politecnico di Torino, IT

Modular SoC Integration with Subsystems: The Audio Subsystem Case [p. 157]

Pieter van der Wolf and Ruud Derwig

Configurability in IP Subsystems: Baseband Examples [p. 163]

Pierre-Xavier Thomas, Grant Martin, David Heine, Dennis Moolenaar, and James Kim

Configurable IO Integration to Reduce System-on-Chip Time to Market: DDR, PCIe Examples [p. 169]

Frank Martin and Peter Bennett

High-performance Imaging Subsystems and Their Integration in Mobile Devices [p. 170]

Menno Lindwer and Mark Ruvald Pedersen

3.2: PANEL: The Heritage of Mead & Conway: What Has Remained the Same, What Was Missed, What Has Changed, What Lies Ahead

Organizer: Marco Casale-Rossi - Synopsys, US
Moderators: Alberto Sangiovanni-Vincentelli - UCB, US; Marco Casale-Rossi - Synopsys, US

Panelists: Luca Carloni, Bernard Courtois, Hugo de Man, Antun Domic, and Jan Rabaey

PANEL: The Heritage of Mead & Conway: What Has Remained the Same, What Was Missed, What Has Changed, What Lies Ahead [p. 171]

3.3: Addressing Process and Delay Variation in High-Level Synthesis

Moderators: Lars Bauer - Karlsruhe Institute of Technology, DE; Hiroyuki Tomiyama - Ritsumeikan University, JP

Profit Maximization through Process Variation Aware High Level Synthesis with Speed Binning [p. 176]

Zhao Mengying, Orailoglu Alex and Xue Chun Jason

Instruction-Set Extension under Process Variation and Aging Effects [p. 182]

Yuko Hara-Azumi, Farshad Firouzi, Saman Kiamehr and Mehdi Tahoori

Multispeculative Additive Trees in High-Level Synthesis [p. 188]

Alberto A. Del Barrio, Roman Hermida, Seda Ogrenci Memik, Jose M. Mendis and Marla C. Molina

Multi-Pumping for Resource Reduction in FPGA High-Level Synthesis [p. 194]

Andrew Canis, Jason H. Anderson and Stephen D. Brown

Resource-Constrained High-Level Datapath Optimization in ASIP Design [p. 198]

Yuankai Chen and Hai Zhou

3.4: Microarchitectural Techniques for Reliability

Moderators: Todd Austin - Michigan University Ann Arbor, US; Mladen Berekovic - Technical University of Braunschweig, DE

Extracting Useful Computation from Error-Prone Processors for Streaming Applications [p. 202]

Yavuz Yetim, Margaret Martonosi and Sharad Malik

Orchestrator: A Low-cost Solution to Reduce Voltage Emergencies for Multi-threaded Applications [p. 208]

Xing Hu, Guihai Yan, Yu Hu and Xiaowei Li

Memory Array Protection: Check on Read or Check on Write? [p. 214]

Panagiota Nikolaou, Yiannakis Sazeides, Lorena Ndreu, Emre Özer and Sachin Idgunji

FaulTM: Error Detection and Recovery Using Hardware Transactional Memory [p. 220]

Gulay Yalcin, Osman Unsal and Adrian Cristal

Phoenix: Reviving MLC Blocks as SLC to Extend NAND Flash Devices Lifetime [p. 226]

Xavier Jimenez, David Novo and Paolo Ienne

3.5: Energy Efficient Mobile and Cloud Computing Systems

Moderators: Tajana Rosing - University of California San Diego, US; Theocharis Theocharides - University of Cyprus, CY

SCC Thermal Model Identification via Advanced Bias-Compensated Least-Squares [p. 230]

Roberto Diversi, Andrea Bartolini, Andrea Tilli, Francesco Beneventi and Luca Benini

System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs [p. 236]

Karthik Chandrasekar, Christian Weis, Benny Akesson, Norbert Wehn and Kees Goossens

Design of Low Energy, High Performance Synchronous and Asynchronous 64-Point FFT [p. 242]

William Lee, Vikas S. Vij, Anthony R. Thatcher and Kenneth S. Stevens

A Multi-Level Monte Carlo FPGA Accelerator for Option Pricing in the Heston Model [p. 248]

Christian de Schryver, Pedro Torruella and Norbert Wehn

Non-Speculative Double-Sampling Technique to Increase Energy-Efficiency in a High-Performance Processor [p. 254]

Junyoung Park, Ameya Chaudhari and Jacob A. Abraham

User-Aware Energy Efficient Streaming Strategy for Smartphone Based Video Playback Applications [p. 258]

Hao Shen and Qinru Qiu

Utility-Aware Deferred Load Balancing in the Cloud Driven by Dynamic Pricing of Electricity [p. 262]

Muhammad Abdullah Adnan and Rajesh Gupta

Leakage and Temperature Aware Server Control for Improving Energy Efficiency in Data Centers [p. 266]

Marina Zapater, José L. Ayala, José M. Moya, Kalyan Vaidyanathan, Kenny Gross and Ayse K. Coskun

3.6: Dealing with Timing Variation in Advanced Technologies

Moderators: Hans Manhaeve - Ridgetop Europe, BE; Saqib Khursheed - University of Southampton, UK

MTTF-Balanced Pipeline Design [p. 270]

Fabian Oboril and Mehdi B.Tahoori

Efficient Variation-Aware Statistical Dynamic Timing Analysis for Delay Test Applications [p. 276]

Marcus Wagner and Hans-Joachim Wunderlich

SlackProbe: A Low Overhead In Situ On-line Timing Slack Monitoring Methodology [p. 282]

Liangzhen Lai, Vikas Chandra, Robert Aitken and Puneet Gupta

Capturing Post-Silicon Variation by Layout-aware Path-delay Testing [p. 288]

Xiaolin Zhang, Jing Ye, Yu Hu and Xiaowei Li

Adaptive Reduction of the Frequency Search Space for Multi-Vdd Digital Circuits [p. 292]

Chandra K.H. Suresh, Ender Yilmaz, Sule Ozev and Ozgur Sinanoglu

3.7: Timing Analysis

Moderators: Stefan Petters - CISTER/INESC-TEC, ISEP, PT; Michael Paulitsch - EADS, DE

FIFO Cache Analysis for WCET Estimation: A Quantitative Approach [p. 296]

Nan Guan, Xinping Yang, Mingsong Lv and Wang Yi

Timing Analysis of Multi-Mode Applications on AUTOSAR Conform Multi-Core Systems [p. 302]

Mircea Negrean, Sebastian Klawitter, Rolf Ernst

Bounding SDRAM Interference: Detailed Analysis vs. Latency-Rate Analysis [p. 308]

Hardik Shah, Alois Knoll and Benny Akesson

3.8: HOT TOPIC: Design for Variability, Manufacturability, Reliability, and Debug: Many Faces of the Same Coin?

Organizer: Vikas Chandra - ARM, US
Moderators: Vikas Chandra - ARM, US; Kartik Mohanram - University of Pittsburgh, US

Role of Design in Multiple Patterning: Technology Development, Design Enablement and Process Control [p. 314]

Rani S. Ghaida and Puneet Gupta

Overcoming Post-Silicon Validation Challenges through Quick Error Detection (QED) [p. 320]

David Lin, Ted Hong, Yanjing Li, Farzan Fallah, Donald S. Gardner, Nagib Hakim and Subhasish Mitra

Stochastic Degradation Modeling and Simulation for Analog Integrated Circuits in Nanometer CMOS [p. 326]

Georges Gielen and Elie Maricau

4.2: The Quest for Better NoCs

Moderators: Pascal Vivet - CEA-Leti, FR; Riccardo Locatelli - ST Microelectronics, FR

A Transition-Signaling Bundled Data NoC Switch Architecture for Cost-effective GALS Multicore Systems [p. 332]

Alberto Ghiribaldi, Davide Bertozzi and Steven M. Nowick

SMART: A Single-Cycle Reconfigurable NoC for SoC Applications [p. 338]

Chia-Hsin Owen Chen, Sunghyun Park, Tushar Krishna, Suvinay Subramanian, Anantha P. Chandrakasan and Li-Shiuan Peh

Switch Folding: Network-on-Chip Routers with Time-Multiplexed Output Ports [p. 344]

G. Dimitrakopoulos, N. Georgiadis, C. Nicopoulos and E. Kalligeros

An Efficient Network-on-Chip Architecture Based on Isolating Local and Non-Local Communications [p. 350]

Vahideh Akhlaghi, Mehdi Kamal, Ali Afzali-Kusha and Massoud Pedram

SVR-NoC: A Performance Analysis Tool for Network-on-Chips Using Learning-based Support Vector Regression Model [p. 354]

Zhiliang Qian, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu and Radu Marculescu

4.3: EMBEDDED TUTORIAL: Reliability Analysis Reloaded: How Will We Survive?

Organizers: Goerschwin Fey - University of Bremen, DE; Matteo Sonza Reorda - Politecnico di Torino, IT
Moderators: Bernd Becker - University of Freiburg, DE; Xavier Vera - Intel, ES

Reliability Analysis Reloaded: How Will We Survive? [p. 358]

Robert Aitken, Görschwin Fey, Zbigniew T. Kalbarczyk, Frank Reichenbach, Matteo Sonza Reorda

4.4: Emerging Solutions to Manage Energy/Performance Trade-Offs along the Memory Hierarchy

Moderators: Mladen Berekovic - Technical University of Braunschweig, DE; Cristina Silvano - Politecnico di Milano, IT

MALEC: A Multiple Access Low Energy Cache [p. 368]

Matthias Boettcher, Giacomo Gabrielli, Bashir M. Al-Hashimi and Danny Kershaw

TreeFTL: Efficient RAM Management for High Performance of NAND Flash-based Storage Systems [p. 374]

Chundong Wang and Weng-Fai Wong

DA-RAID-5: A Disturb Aware Data Protection Technique for NAND Flash Storage Systems [p. 380]

Jie Guo, Wujie Wen, Yaojun Zhang Li, Sicheng Li, Hai Li and Yiran Chen

Exploiting Subarrays inside a Bank to Improve Phase Change Memory Performance [p. 386]

Jianhui Yue and Yifeng Zhu

Future of GPGPU Micro-Architectural Parameters [p. 392]

Cedric Nugteren, Gert-Jan van den Braak and Henk Corporaal

Synchronizing Code Execution on Ultra-Low-Power Embedded Multi-Channel Signal Analysis Platforms [p. 396]

Ahmed Yasir Dogan, Rubén Braojos, Jeremy Constantin, Giovanni Ansaloni, Andreas Burg and David Atienza

Using Synchronization Stalls in Power-aware Accelerators [p. 400]

Ali Jooya and Amirali Baniasadi

4.5: Device Identification and Protection

Moderators: Patrick Koeberl - Intel Labs, DE; Roel Maes - Intrinsic-ID, NL

Comprehensive Analysis of Software Countermeasures against Fault Attacks [p. 404]

Nikolaus Theißing, Dominik Merli, Michael Smola, Frederic Stumpf and Georg Sigl

An EDA-Friendly Protection Scheme against Side-Channel Attacks [p. 410]

Ali Galip Bayrak, Nikola Velickovic, Francesco Regazzoni, David Novo, Philip Brisk and Paolo Ienne

Design and Implementation of a Group-based RO PUF [p. 416]

Chi-En Yin, Gang Qu and Qiang Zhou

ClockPUF: Physical Unclonable Functions Based on Clock Networks [p. 422]

Yida Yao, MyungBo Kim, Jianmin Li, Igor L. Markov and Farinaz Koushanfar

Memristor PUFs: A New Generation of Memory-based Physically Unclonable Functions [p. 428]

Patrick Koeberl, Ünal Kocabas and Ahmad-Reza Sadeghi

Wireless Sensor Network Simulation for Security and Performance Analysis [p. 432]

A. Díaz, P. Sanchez, J. Sancho and J. Rico

4.6: New Techniques for Test Pattern Generation

Moderators: Sudhakar Reddy - University of Iowa, US; Matteo Sonza Reorda - Politecnico di Torino, IT

Accurate QBF-based Test Pattern Generation in Presence of Unknown Values [p. 436]

Stefan Hillebrecht, Michael A. Kochte, Dominik Erb, Hans-Joachim Wunderlich and Bernd Becker

Test Solution for Data Retention Faults in Low-Power SRAMs [p. 442]

L. B. Zordan, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel and N. Badereddine

Efficient SAT-based Dynamic Compaction and Relaxation for Longest Sensitizable Paths [p. 448]

Matthias Sauer, Sven Reimer, Tobias Schubert, Ilia Polian and Bernd Becker

Process-Variation-Aware Iddq Diagnosis for Nano-Scale CMOS Designs - The First Step [p. 454]

Chia-Ling (Lynn) Chang, Charles H.-P. Wen and Jayanta Bhadra

4.7: HOT TOPIC: Security Challenges in Automotive Hardware/Software Architecture Design

Organizer: Samarjit Chakraborty - TU Munich, DE
Moderators: Jason Xue - City Univ. of Hong Kong, HK; Dip Goswami - TU Munich, DE

Security Challenges in Automotive Hardware/Software Architecture Design [p. 458]

Florian Sagstetter, Martin Lukasiewycz, Sebastian Steinhorst; Marko Wolf, Alexandre Bouard, William R. Harris, Somesh Jha, Thomas Peyrin, Axel Poschmann, Samarjit Chakraborty

5.1: HOT TOPIC - System Approaches to Energy-Efficiency

Organizer: Ahmed Jerraya - CEA-Leti-MINATEC, FR
Moderators: Patrick Blouet - ST Ericsson, FR; Ahmed Jerraya - CEA-Leti-MINATEC, FR

Experiences with Mobile Processors for Energy Efficient HPC [p. 464]

Nikola Rajovic, Alejandro Rico, James Vipond, Isaac Gelado, Nikola Puzovic and Alex Ramirez

What Designs for Coming Supercomputers? [p. 469]

Xavier Vigouroux

Energy-Efficient In-Memory Database Computing [p. 470]

Wolfgang Lehner

Performance Analysis of HPC Applications on Low-Power Embedded Platforms [p. 475]

Luka Stanisic, Brice Videau, Johan Cronsioe, Augustin Degomme, Vania Marangozova-Martin, Arnaud Legrand, Jean-François Méhaut

5.2: PANEL: Can Energy Harvesting Deliver Enough Power for Automotive Electronics?

Organizers: Tom Kazmierski - University of Southampton, UK; Christoph Grimm - TU Kaiserslautern, DE
Moderators: Peter Neumann - Edacentrum, DE; Norbert Wehn - TU Kaiserslautern, DE

Alternative Power Supply Concepts for Self-Sufficient Wireless Sensor Nodes by Energy Harvesting [p. 481]

Robert Kappel, Günter Hofer, Gerald Holweg, Thomas Herndl

Adaptable, High Performance Energy Harvesters [p. 482]

Paul D. Mitcheson

Ultra-Low Power: An EDA Challenge [p. 483]

Christoph Grimm, Javier Moreno, Xiao Pan

DoE-based Performance Optimization of Energy Management in Sensor Nodes Powered by Tunable Energy-Harvesters [p. 484]

Tom J. Kazmierski, Leran Wang, Bashir Al-Hashimi, Geoff Merrett

5.3: Post-Silicon Debug Techniques

Moderators: Jaan Raik - Tallinn University of Technology, EE; Adrian Evans - iRoC Technologies, FR

A Hybrid Approach for Fast and Accurate Trace Signal Selection for Post-Silicon Debug [p. 485]

Min Li and Azadeh Davoodi

Machine Learning-based Anomaly Detection for Post-silicon Bug Diagnosis [p. 491]

Andrew DeOrio, Qingkun Li, Matthew Burgess and Valeria Bertacco

Space Sensitive Cache Dumping for Post-silicon Validation [p. 497]

Sandeep Chandran, Smruti R. Sarangi and Preeti Ranjan Panda

Fast and Accurate BER Estimation Methodology for I/O Links Based on Extreme Value Theory [p. 503]

Alessandro Cevrero, Nestor Evmorfopoulos, Charalampos Antoniadis, Paolo Ienne, Yusuf Leblebici, Andreas Burg and George Stamoulis

Automated Determination of Top Level Control Signals [p. 509]

Rohit Kumar Jain, Praveen Tiwari and Soumen Ghosh

5.4: Novel Approaches for Real-Time Architectures

Moderators: Cristina Silvano - Politecnico di Milano, IT; Andreas Moshovos - University of Toronto, CA

A Cache Design for Probabilistically Analysable Real-time Systems [p. 513]

Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones and Francisco J. Cazorla

MARTHA: Architecture for Control and Emulation of Power Electronics and Smart Grid Systems [p. 519]

Michel A. Kinsy, Ivan Celanovic, Omer Khan and Srinivas Devadas

Conservative Open-Page Policy for Mixed Time-Criticality Memory Controllers [p. 525]

Sven Goossens, Benny Akesson and Kees Goossens

An Efficient and Flexible Hardware Support for Accelerating Synchronization Operations on the STHORM Many-Core Architecture [p. 531]

Farhat Thabet, Yves Lhuillier, Caaliph Andriamisaina, Jean-Marc Philippe and Raphaël David

5.5: Error-Aware Adaptive Modern Computing Architectures

Moderators: Marco Santambroglio - Politecnico di Milano, IT; Marian Verhelst - Katholieke Universiteit Leuven, BE

Hot-Swapping Architecture with Back-biased Testing for Mitigation of Permanent Faults in Functional Unit Array [p. 535]

Zoltán Endre Rákossy, Masayuki Hiromoto, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura and Hiroyuki Ochi

Variation-tolerant OpenMP Tasking on Tightly-coupled Processor Clusters [p. 541]

Abbas Rahimi, Andrea Marongiu, Paolo Burgio, Rajesh K.Gupta and Luca Benini

Accurate and Efficient Reliability Estimation Techniques during ADL-Driven Embedded Processor Design [p. 547]

Zheng Wang, Kapil Singh, Chao Chen and Anupam Chattopadhyay

5.6: Advances in Mixed-Signal, RF, and MEMS Testing

Moderators: Salvador Mir - TIMA Laboratory, FR; Adoración Rueda - University of Seville, ES

Handling Discontinuous Effects in Modeling Spatial Correlation of Wafer-level Analog/RF Tests [p. 553]

Ke Huang, Nathan Kupp, John M. Carulli, Jr. and Yiorgos Makris

Fault Detection, Real-Time Error Recovery, and Experimental Demonstration for Digital Microfluidic Biochips [p. 559]

Kai Hu, Bang-Ning Hsu, Andrew Madison, Krishnendu Chakrabarty and Richard Fair

Fault Analysis and Simulation of Large Scale Industrial Mixed-Signal Circuits [p. 565]

Ender Yilmaz, Geoff Shofner, LeRoy Winemberg and Sule Ozev

Electrical Calibration of Spring-Mass MEMS Capacitive Accelerometers [p. 571]

Lingfei Deng, Vinay Kundur, Naveen Sai Jangala Naga, Muhlis Kenan Ozel, Ender Yilmaz, Sule Ozev, Bertan Bakkaloglu, Sayfe Kiaei, Divya Pratab and Tehmoor Dar

5.7: Compilers and Software Synthesis for Embedded Systems

Moderators: Björn Franke - University of Edinburgh, UK; Heiko Falk - Ulm University, DE

Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA [p. 575]

Christophe Alias, Alain Darte and Alexandru Plesco

Sequentially Constructive Concurrency - A Conservative Extension of the Synchronous Model of Computation [p. 581]

Reinhard von Hanxleden, Michael Mendler, Joaquin Aguado, Björn Duderstadt, Insa Fuhrmann, Christian Motika, Stephen Mercer and Owen O'Brien

Fast and Accurate Cache Modeling in Source-Level Simulation of Embedded Software [p. 587]

Zhonglei Wang and Jörg Henkel

Automatic and Efficient Heap Data Management for Limited Local Memory Multicore Architectures [p. 593]

Ke Bai and Aviral Shrivastava

Software Enabled Wear-Leveling for Hybrid PCM Main Memory on Embedded Systems [p. 599]

Jingtong Hu, Qingfeng Zhuge, Chun Jason Xue, Wei-Che Tseng, and Edwin H.-M.Sha

Probabilistic Timing Analysis on Conventional Cache Designs [p. 603]

Leonidas Kosmidis, Charlie Curtsinger, Eduardo Quiñones, Jaume Abella, Emery Berger and Francisco J. Cazorla

6.1: EMBEDDED TUTORIAL - HW-SW Architecture Approaches to Energy-Efficiency

Organizer: Ahmed Jerraya - CEA-Leti-MINATEC, FR
Moderators: Agnès Fritsch - Thales Group, FR; Ahmed Jerraya - CEA-Leti-MINATEC, FR

HW-SW Integration for Energy-Efficient/Variability-Aware Computing [p. 607]

Gasser Ayad, Andrea Acquaviva, Enrico Macii, Brahim Sahbi, Romain Lemaire

6.2: HOT TOPIC: Emerging Nanoscale Devices: A Booster for High Performance Computing

Organizers: Pierre-Emmanuel Gaillardon - EPFL, CH; Giovanni De Micheli - EPFL, CH
Moderators: Giovanni De Micheli - EPFL, CH; Ahmed Jerraya - CEA, LETI, Minatec, FR

Near-Threshold Voltage Design in Nanoscale CMOS [p. 612]

Vivek De

Ultra-Wide Voltage Range Designs in Fully-Depleted Silicon-On-Insulator FETs [p. 613]

E. Beigne, A. Valentian, B. Giraud, O. Thomas, T. Benoist, Y. Thonnart, S. Bernard, G. Moritz, O. Billoint, Y. Maneglia, P. Flatresse, J.P. Noel, F. Abouzeid, B. Pelloux- Prayer, A. Grover, S. Clerc, P. Roche, J. Le Coz, S. Engels and R. Wilson

Carbon Nanotube Circuits: Opportunities and Challenges [p. 619]

Hai Wei, Max Shulaker, Gage Hills, Hong-Yu Chen, Chi-Shuen Lee, Luckshitha Liyanage, Jie Zhang, H.-S. Philip Wong and Subhasish Mitra

Vertically-Stacked Double-Gate Nanowire FETs with Controllable Polarity: From Devices to Regular ASICs [p. 625]

Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Shashikanth Bobba, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici and Giovanni De Micheli

6.3: Verification and Simulation Support for Architecture

Moderators: Valeria Bertacco - University of Michigan, US; Elena Vatajelu - LIRMM, FR

On-the-fly Verification of Memory Consistency with Concurrent Relaxed Scoreboards [p. 631]

Leandro S. Freitas, Eberle A. Rambo and Luiz C. V. dos Santos

Fast Cache Simulation for Host-Compiled Simulation of Embedded Software [p. 637]

Kun Lu, Daniel Müller-Gritschneder and Ulf Schlichtmann

A Critical-Section-Level Timing Synchronization Approach for Deterministic Multi-Core Instruction-Set Simulations [p. 643]

Fan-Wei Yu, Bo-Han Zeng, Yu-Hung Huang, Hsin-I Wu, Che-Rung Lee and Ren-Song Tsay

Multi-level Phase Analysis for Sampling Simulation [p. 649]

Jiaxin Li, Weihua Zhang, Haibo Chen and Binyu Zang

Hypervised Transient SPICE Simulations of Large Netlists & Workloads on Multi-Processor Systems [p. 655]

Grigorios Lyras, Dimitrios Rodopoulos, Antonis Papanikolaou and Dimitrios Soudris

6.4: Design Space Exploration for Application Specific Architectures

Moderators: Andreas Moshovos - University of Toronto, CA; Georgi Gaydadjiev - Chalmers University of Technology, SE

A Meta-Model Assisted Coprocessor Synthesis Framework for Compiler/Architecture Parameters Customization [p. 659]

Sotirios Xydis, Gianluca Palermo, Vittorio Zaccaria and Cristina Silvano

Energy-Efficient Memory Hierarchy for Motion and Disparity Estimation in Multiview Video Coding [p. 665]

Felipe Sampaio, Bruno Zatt, Muhammad Shafique, Luciano Agostini, Sergio Bampi and Jörg Henkel

Improving Simulation Speed and Accuracy for Many-Core Embedded Platforms with Ensemble Models [p. 671]

E. Paone, N. Vahabi, V. Zaccaria, C. Silvano, D. Melpignano, G. Haugou and T. Lepley

Statically-scheduled Application-specific Processor Design: A Case-study on MMSE MIMO Equalization [p. 677]

Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Yasser Mohana and Youssef Atat

Exploring Resource Mapping Policies for Dynamic Clustering on NoC-based MPSoCs [p. 681]

Gustavo Girão, Thiago Santini and Flávio R. Wagner

Characterizing the Performance Benefits of Fused CPU/GPU Systems Using FusionSim [p. 685]

Vitaly Zakharenko, Tor Aamodt and Andreas Moshovos

6.5: Reliable Multi-Processor Computing Systems Design

Moderators: Jose Ayala - Complutense University of Madrid, ES; Vincenzo Rana - EPFL, CH

Reliability-Driven Task Mapping for Lifetime Extension of Networks-on-Chip Based Multiprocessor Systems [p. 689]

Anup Das, Akash Kumar and Bharadwaj Veeravalli

A Work-Stealing Scheduling Framework Supporting Fault Tolerance [p. 695]

Yizhuo Wang, Weixing Ji, Feng Shi and Qi Zuo

A Cost-Effective Selective TMR for Heterogeneous Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis [p. 701]

Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi and Takashi Sato

CSER: HW/SW Configurable Soft-Error Resiliency for Application Specific Instruction-Set Processors [p. 707]

Tuo Li, Muhammad Shafique, Semeen Rehman, Swarnalatha Radhakrishnan, Roshan Ragel, Jude Angelo Ambrose, Jörg Henkel and Sri Parameswaran

Reliability Analysis for Integrated Circuit Amplifiers Used in Neural Measurement Systems [p. 713]

Nico Hellwege, Nils Heidmann, Dagmar Peters-Drolshagen and Steffen Paul

On-Line Testing of Permanent Radiation Effects in Reconfigurable Systems [p. 717]

Luca Cassano, Dario Cozzi, Sebastian Korf, Jens Hagemeyer, Mario Porrmann and Luca Sterpone

An Approach for Redundancy in FlexRay Networks Using FPGA Partial Reconfiguration [p. 721]

Shanker Shreejith, Kizheppatt Vipin, Suhaib A Fahmy and Martin Lukasiewycz

6.6: HOT TOPIC: Energy-Efficient Design and Test Techniques for Future Multi-Core Systems

Organizer: Krishnendu Chakrabarty - Duke University, US
Moderators: Mehdi Tahoori - Karlsruhe Institute of Technology, DE; Paul Pop - Technical University of Denmark, DK

Energy-Efficient Multicore Chip Design through Cross-Layer Approach [p. 725]

Paul Wettin, Jacob Murray, Partha Pande, Behrooz Shirazi and Amlan Ganguly

Breaking the Energy Barrier in Fault-Tolerant Caches for Multicore Systems [p. 731]

Paul Ampadu, Meilin Zhang and Vladimir Stojanovic

Testing for SoCs with Advanced Static and Dynamic Power-Management Capabilities [p. 737]

Xrysovalantis Kavousianos and Krishnendu Chakrabarty

Towards Adaptive Test of Multi-core RF SoCs [p. 743]

Rajesh Mittal, Lakshmanan Balasubramanian, Chethan Kumar Y.B., V. R. Devanathan, Mudasir Kawoosa and Rubin A. Parekhji

6.7: Model-Based Design and Verification for Embedded Systems

Moderators: Wang Yi' - Uppsala University, SE; Saddek Bensalem - Verimag, FR

A Satisfiability Approach to Speed Assignment for Distributed Real-Time Systems [p. 749]

Pratyush Kumar, Devesh B. Chokshi and Lothar Thiele

Data Mining MPSoC Simulation Traces to Identify Concurrent Memory Access Patterns [p. 755]

Sofiane Lagraa, Alexandre Termier and Frédéric Pétrot

Model-Based Energy Optimization of Automotive Control Systems [p. 761]

Joost-Pieter Katoen, Thomas Noll, Hao Wu, Thomas Santen and Dirk Seifert

Formal Analysis of Sporadic Bursts in Real-Time Systems [p. 767]

Sophie Quinton, Mircea Negrean and Rolf Ernst

7.1: HOT TOPIC - Many-Core SoC Approaches to Energy-Efficiency

Organizer: Ahmed Jerraya - CEA-Leti-MINATEC, FR
Moderators: Marc Duranton - CEA, FR; Ahmed Jerraya - CEA-Leti-MINATEC, FR

Development of Low Power Many-Core SoC for Multimedia Applications [p. 773]

Takashi Miyamori, Hui Xu, Takeshi Kodaka, Hiroyuki Usui, Toru Sano and Jun Tanabe

SoC Low-Power Practices for Wireless Applications [p. 778]

Nicolas Darbel and Stephane Lecomte

3D Integration for Power-Efficient Computing [p. 779]

D. Dutoit, E. Guthmuller, I. Miro-Panades

7.2: Formal Verification Algorithms and Models

Moderators: Christoph Scholl - University of Freiburg, DE; Jason Baumgartner - IBM, US

Verifying Safety and Liveness for the FlexTM Hybrid Transactional Memory [p. 785]

Parosh Abdulla, Sandhya Dwarkadas, Ahmed Rezine, Arrvindh Shriraman and Yunyun Zhu

QF_BV Model Checking with Property Directed Reachability [p. 791]

Tobias Welp and Andreas Kuehlmann

A Semi-Canonical Form for Sequential AIGs [p. 797]

Alan Mishchenko, Niklas Een, Robert Brayton, Michael Case, Pankaj Chauhan and Nikhil Sharma

Fast Cone-Of-Influence Computation and Estimation in Problems with Multiple Properties [p. 803]

C. Loiacono, M. Palena, P. Pasini, D. Patti, S. Quer, S. Ricossa, D. Vendraminetto and J. Baumgartner

Using Cubes of Non-state Variables with Property Directed Reachability [p. 807]

John D. Backes and Marc D. Riedel

Bridging the Gap between Dual Propagation and CNF-based QBF Solving [p. 811]

Alexandra Goultiaeva, Martina Seidl and Armin Biere

7.3: Dynamic Reconfiguration

Moderators: Diana Goehringer - Karlsruhe Institute of Technology, DE; Fabrizio Ferrandi - Politecnico di Milano, IT

Dynamic Configuration Prefetching Based on Piecewise Linear Prediction [p. 815]

Adrian Lifa, Petru Eles and Zebo Peng

An Automatic Tool Flow for the Combined Implementation of Multi-mode Circuits [p. 821]

Brahim Al Farisi, Karel Bruneel, João M. P. Cardoso and Dirk Stroobandt

Support for Dynamic Issue Width in VLIW Processors Using Generic Binaries [p. 827]

Anthony Brandon and Stephan Wong

The RecoBlock SoC Platform: A Flexible Array of Reusable Run-Time-Reconfigurable IP-Blocks [p. 833]

Byron Navas, Ingo Sander and Johnny Öberg

DANCE: Distributed Application-aware Node Configuration Engine in Shared Reconfigurable Sensor Networks [p. 839]

Chih-Ming Hsieh, Zhonglei Wang and Jörg Henkel

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators [p. 843]

Cuong Pham-Quoc, Jan Heisswolf, Stephan Werner, Zaid Al-Ars, Jürgen Becker and Koen Bertels

7.4: Emerging Memory

Moderators: Ian O'Connor - Lyon Institute of Nanotechnology, FR; Siddharth Garg - University of Waterloo, CA

OAP: An Obstruction-Aware Cache Management Policy for STT-RAM Last-Level Caches [p. 847]

Jue Wang, Xiangyu Dong and Yuan Xie

STT-RAM Designs Supporting Dual-Port Accesses [p. 853]

Xiuyuan Bi, Mohamed Anis Weldon and Hai Li

Low Cost Power Failure Protection for MLC NAND Flash Storage Systems with PRAM/DRAM Hybrid Buffer [p. 859]

Jie Guo, Jun Yang, Youtao Zhang and Yiran Chen

SPaC: A Segment-based Parallel Compression for Backup Acceleration in Nonvolatile Processors [p. 865]

Xiao Sheng, Yiqun Wang, Yongpan Liu and Huazhong Yang

The Design of Sustainable Wireless Sensor Network Node Using Solar Energy and Phase Change Memory [p. 869]

Ping Zhou, Youtao Zhang and Jun Yang

Optical Look Up Table [p. 873]

Zhen Li, Sébastien Le Beux, Christelle Monat, Xavier Letartre and Ian O'Connor

A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions [p. 877]

Sandeep Miryrala, Mehrdad Montazeri, Andrea Calimera, Enrico Macii and Massimo Poncino

7.5: Energy-efficient Architectures and Software Design for Power-constrained Systems

Moderators: Geoff Merrett - University of Southampton, UK; Gangadhar Garipelli - EPFL, CH

Optimal Control of a Grid-Connected Hybrid Electrical Energy Storage System for Homes [p. 881]

Yanzhi Wang, Xue Lin, Massoud Pedram, Sangyoung Park and Naehyuck Chang

Radar Signature in Multiple Target Tracking System for Driver Assistant Application [p. 887]

Haisheng Liu and Smail Niar

Development of a Fully Implantable Recording System for ECoG Signals [p. 893]

Jonas Pistor, Janpeter Hoeffmann, David Rotermund, Elena Tolstosheeva, Tim Schellenberg, Dmitriy Boll, Victor Gordillo-Gonzales, Sunita Mandon, Dagmar Peters-Drolshagen, Andreas Kreiter, Martin Schneider, Walter Lang, Klaus Pawelzik and Steffen Paul

A Methodology for Embedded Classification of Heartbeats Using Random Projections [p. 899]

Rubén Braojos, Giovanni Ansaloni and David Atienza

A Survy of Multi-Source Energy Harvesting Systems [p. 905]

Alex S. Weddell, Michele Magno, Geoff V. Merrett, Davide Brunelli, Bashir M. Al-Hashimi and Luca Benini

Capital Cost-Aware Design and Partial Shading-Aware Architecture Optimization of a Reconfigurable Photovoltaic System [p. 909]

Yanzhi Wang, Xue Lin, Massoud Pedram, Jaemin Kim and Naehyuck Chang

An Ultra-Low Power Hardware Accelerator Architecture for Wearable Computers Using Dynamic Time Warping [p. 913]

Reza Lotfian and Roozbeh Jafari

Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes [p. 917]

Bojan Maric, Jaume Abella and Mateo Valero

7.6: On-Line Approaches towards Processor Resilience

Moderators: Yiorgos Makris - University of Dallas, US; Xavier Vera - Intel, ES 7.6.1 885

Efficient Software-Based Fault Tolerance Approach on Multicore Platforms [p. 921]

Hamid Mushtaq, Zaid Al-Ars and Koen Bertels

Using Explicit Output Comparisons for Fault Tolerant Scheduling (FTS) on Modern High-Performance Processors [p. 927]

Yue Gao, Sandeep K. Gupta and Melvin A. Breuer

Low Cost Permanent Fault Detection Using Ultra-Reduced Instruction Set Co-Processors [p. 933]

Sundaram Ananthanarayan, Siddharth Garg, Hiren D. Patel

Improving Fault Tolerance Utilizing Hardware-Software-Co-Synthesis [p. 939]

Heinz Riener, Stefan Frehse and Görschwin Fey

A Dynamic Self-Adaptive Correction Method for Error Resilient Application [p. 943]

Luming Yan, Huaguo Liang, Zhengfeng Huang

7.7: EMBEDDED TUTORIAL: From Multi-core SoC to Scale-out Processors

Organizer: Luca Fanucci - University of PISA, IT
Moderators: Marcello Coppola - STMicroelectronics, FR; Luca Fanucci - University of Pisa, IT

>From Embedded Multi-core SoCs to Scale-out Processors [p. 947]

Marcello Coppola, Babak Falsafi, John Goodacre and George Kornaros

8.1: HOT TOPIC - Fabrication Technology Approaches to Energy-Efficiency

Organizer: Ahmed Jerraya - CEA-Leti-MINATEC, FR
Moderator: Ahmed Jerraya - CEA-Leti-MINATEC, FR

UTBB FD-SOI: A Process/Design Symbiosis for Breakthrough Energy-efficiency [p. 952]

Philippe Magarshack, Philippe Flatresse and Giorgio Cesana

Wireless Interconnect for Board and Chip Level [p. 958]

Gerhard P. Fettweis, Najeeb ul Hassan, Lukas Landau and Erik Fischer

Future Memory and Interconnect Technologies [p. 964]

Yuan Xie

8.2: Scheduling for Real-Time Embedded Systems

Moderators: Wido Kruijtzer - Synopsys, NL; Jan Madsen - Technical University of Denmark, DK

Optimized Scheduling of Multi-IMA Partitions with Exclusive Region for Synchronized Real- Time Multi-Core Systems [p. 970]

Jung-Eun Kim, Man-Ki Yoon, Sungjin Im, Richard Bradford and Lui Sha

Quality-Aware Media Scheduling on MPSoC Platforms [p. 976]

Deepak Gangadharan, Samarjit Chakraborty and Roger Zimmermann

Priority Assignment for Event-triggered Systems Using Mathematical Programming [p. 982]

Martin Lukasiewycz, Sebastian Steinhorst and Samarjit Chakraborty

Efficient and Scalable OpenMP-based System-level Design [p. 988]

Alessandro Cilardo, Luca Gallo, Antonino Mazzeo and Nicola Mazzocca

Utilizing Voltage-Frequency Islands in C-to-RTL Synthesis for Streaming Applications [p. 992]

Xinyu He, Shuangchen Li, Yongpan Liu, X. Sharon Hu and Huazhong Yang

8.3: Logic Synthesis Techniques

Moderators: Michel Berkelaar - Delft University of Technology, NL; Jordi Cortadella - Universitat Politècnica Catalunya, ES

Minimization of P-Circuits Using Boolean Relations [p. 996]

Anna Bernasconi, Valentina Ciriani, Gabriella Trucco and Tiziano Villa

Intuitive ECO Synthesis for High Performance Circuits [p. 1002]

Haoxing Ren, Ruchir Puri, Lakshmi Reddy, Smita Krishnaswamy, Cindy Washburn, Joel Earl and Joachim Keinert

Retiming for Soft Error Minimization under Error-Latching Window Constraints [p. 1008]

Yinghai Lu and Hai Zhou

Biconditional BDD: A Novel Canonical BDD for Logic Synthesis Targeting XOR-rich Circuits [p. 1014]

Luca Amarú, Pierre-Emmanuel Gaillardon and Giovanni De Micheli

Optimizing BDDs for Time-Series Dataset Manipulation [p. 1018]

Stergios Stergiou and Jawahar Jain

Incorporating the Impacts of Workload-Dependent Runtime Variations into Timing Analysis [p. 1022]

Farshad Firouzi, Saman Kiamehr, Mehdi Tahoori and Sani Nassif

8.4: High-Speed Robust NoCs

Moderators: Luca Carloni - Columbia University, US; Georgios Dimitrakopoulos - Thrace University, GR

Exploring Topologies for a Source-synchronous Ring-based Network-on-Chip [p. 1026]

Ayan Mandal, Sunil P. Khatri and Rabi N. Mahapatra

Proactive Aging Management in Heterogeneous NoCs through a Criticality-driven Routing Approach [p. 1032]

Dean Michael Ancajas, Koushik Chakraborty and Sanghamitra Roy

Sensor-wise Methodology to Face NBTI Stress of NoC Buffers [p. 1038]

Davide Zoni and William Fornaciari

An Area-efficient Network Interface for a TDM-based Network-on-Chip [p. 1044]

Jens Sparsø, Evangelia Kasapaki and Martin Schoeberl

CARS: Congestion-Aware Request Scheduler for Network Interfaces in NoC-based Manycore Systems [p. 1048]

Masoud Daneshtalab, Masoumeh Ebrahimi, Juha Plosila and Hannu Tenhunen

8.5: Industrial Experiences with Embedded System Design

Moderators: Roberto Zafalon - ST Microelectronics, IT; Ralf Pferdmenges - Infineon Technologies, DE

Designing Tightly-coupled Extension Units for the STxP70 Processor [p. 1052]

Yves Janin, Valérie Bertin, Hervé Chauvet, Thomas Deruyter, Christophe Eichwald, Olivier-André Giraud, Vincent Lorquet and Thomas Thery

A Fast and Accurate Methodology for Power Estimation and Reduction of Programmable Architectures [p. 1054]

Erwan Piriou, Raphaël David, Fahim Rahim and Solaiman Rahim

A Gate Level Methodology for Efficient Statistical Leakage Estimation in Complex 32nm Circuits [p. 1056]

Smriti Joshi, Anne Lombardot, Marc Belleville, Edith Beigne and Stephane Girard

A Near-Future Prediction Method for Low Power Consumption on a Many-Core Processor [p. 1058]

Takeshi Kodaka, Akira Takeda, Shunsuke Sasaki, Akira Yokosawa, Toshiki Kizu, Takahiro Tokuyoshi, Hui Xu, Toru Sano, Hiroyuki Usui, Jun Tanabe, Takashi Miyamori and Nobu Matsumoto

Time- and Angle-triggered Real-time Kernel [p. 1060]

Damien Chabrol, Didier Roux, Vincent David, Mathieu Jan, Moha Ait Hmid, Patrice Oudin and Gilles Zeppa

An Extremely Compact JPEG Encoder for Adaptive Embedded Systems [p. 1063]

Josef Schneider and Sri Parameswaran

8.6: DfT Methods

Moderators: Peter Harrod - ARM, UK; Luigi Dillilo - LIRMM, FR

Non-Invasive Pre-Bond TSV Test Using Ring Oscillators and Multiple Voltage Levels [p. 1065]

Sergej Deutsch and Krishnendu Chakrabarty

LFSR Seed Computation and Reduction Using SMT-Based Fault-Chaining [p. 1071]

Dhrumeel Bakshi and Michael S. Hsiao

Scan Design with Shadow Flip-flops for Low Performance Overhead and Concurrent Delay Fault Detection [p. 1077]

Sébastien Sarrazin, Samuel Evain, Lirida Alves de Barros Naviner, Yannick Bonhomme and Valentin Gherman

On Candidate Fault Sets for Fault Diagnosis and Dominance Graphs of Equivalence Classes [p. 1083]

Irith Pomeranz

A Fast and Efficient DFT for Test and Diagnosis of Power Switches in SoCs [p. 1089]

Xiaoyu Huang, Jimson Mathew, Rishad A. Shafik, Subhasis Bhattacharjee and Dhiraj K Pradhan

8.7: Monitoring and Control of Cyber Physical Systems

Moderators: Rolf Ernst - Technische Universität Braunschweig, DE; Haibo Zeng - McGill University, CA

Control-Quality Driven Design of Cyber-Physical Systems with Robustness Guarantees [p. 1093]

Amir Aminifar, Petru Eles, Zebo Peng and Anton Cervin

Compositional Analysis of Switched Ethernet Topologies [p. 1099]

Reinhard Schneider, Licong Zhang, Dip Goswami, Alejandro Masrur and Samarjit Chakraborty

Supervisor Synthesis for Controller Upgrades [p. 1105]

Johannes Kloos and Rupak Majumdar

Event Density Analysis for Event Triggered Control Systems [p. 1111]

Tobias Bund, Benjamin Menhorn and Frank Slomka

Model Predictive Control over Delay-Based Differentiated Services Control Networks [p. 1117]

Riccardo Muradore, Davide Quaglia and Paolo Fiorini

Multirate Controller Design for Resource- and Schedule-Constrained Automotive ECUs [p. 1123]

Dip Goswami, Alejandro Masrur, Reinhard Schneider, Chun Jason Xue and Samarjit Chakraborty

Design of an Ultra-low Power Device for Aircraft Structural Health Monitoring [p. 1127]

Alessandro Perelli, Carlo Caione, Luca De Marchi, Davide Brunelli, Alessandro Marzani and Luca Benini

8.8: HOT TOPIC: Countering Counterfeit Attacks on Micro-Electronics

Organizers: Erik Jan Marinissen - IMEC, BE; Ingrid Verbauwhede - KU Leuven, BE
Moderators: Steven Jeter - Infineon Technologies, DE; Ingrid Verbauwhede - KU Leuven, BE

Qualification and Testing Process to Implement Anti-Counterfeiting Technologies into IC Packages [p. 1131]

Nathalie Kae-Nune and Stephanie Pesseguier

Anti-Counterfeiting with Hardware Intrinsic Security [p. 1137]

Vincent van der Leest and Pim Tuyls

9.1: HOT TOPIC: Smart Grid and Buildings

Organizer: Luca Benini - Università di Bologna, IT
Moderators: Andrea Acquaviva - Politecnico di Torino, IT; Luca Benini - Università di Bologna, IT

Sustainable Energy Policies: Research Challenges and Opportunities [p. 1143]

Michela Milano

Self-aware Cyber-physical Systems and Applications in Smart Buildings and Cities [p. 1149]

Levent Gurgen, Ozan Gunalp, Yazid Benazzouz and Mathieu Galissot

Perpetual and Low-cost Power Meter for Monitoring Residential and Industrial Appliances [p. 1155]

Danilo Porcarelli, Domenico Balsamo, Davide Brunelli and Giacomo Paci

9.2: System-Level Analysis and Simulation

Moderators: Wolfgang Müller - University of Paderborn, DE; Christian Haubelt - University of Rostock, DE

Analytical Timing Estimation for Temporally Decoupled TLMs Considering Resource Conflicts [p. 1161]

Kun Lu, Daniel Müller-Gritschneder and Ulf Schlichtmann

Towards Performance Analysis of SDFGs Mapped to Shared-Bus Architectures Using Model-Checking [p. 1167]

Maher Fakih, Kim Grüttner, Martin Fränzle and Achim Rettberg

Toward Polychronous Analysis and Validation for Timed Software Architectures in AADL [p. 1173]

Yue Ma, Huafeng Yu, Thierry Gautier, Paul Le Guernic, Jean-Pierre Talpin, Loïc Besnard and Maurice Heitz

Tuning Dynamic Data Flow Analysis to Support Design Understanding [p. 1179]

Jan Malburg, Alexander Finder and Görschwin Fey

Fast and Accurate TLM Simulations Using Temporal Decoupling for FIFO-based Communications [p. 1185]

Claude Helmstetter, Jérôme Cornet, Bruno Galilée, Matthieu Moy and Pascal Vivet

Determining Relevant Model Elements for the Verification of UML/OCL Specifications [p. 1189]

Julia Seiter, Robert Wille, Mathias Soeken and Rolf Drechsler

Towards a Generic Verification Methodology for System Models [p. 1193]

Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann and Rolf Drechsler

9.3: Thermal/Power Management Techniques for Energy-Efficient Systems

Moderators: Wolfgang Nebel - University of Oldenburg, DE; Alberto Macii - Politecnico di Torino, IT

A Sub-μA Power Management Circuit in 0.18μm CMOS for Energy Harvesters [p. 1197]

Biswajit Mishra, Cyril Botteron, Gabriele Tasselli, Christian Robert and Pierre-André Farine

Saliency Aware Display Power Management [p. 1203]

Yang Xiao, Kevin Irick, Vijay Narayanan, Dongwha Shin and Naehyuck Chang

Active-Mode Leakage Reduction with Data-Retained Power Gating [p. 1209]

Andrew B. Kahng, Seokhyeong Kang and Bongil Park

A Power-Driven Thermal Sensor Placement Algorithm for Dynamic Thermal Management [p. 1215]

Hai Wang, Sheldon X.-D. Tan, Sahana Swarup and Xue-Xin Liu

Active Power-Gating-Induced Power/Ground Noise Alleviation Using Parasitic Capacitance of On-Chip Memories [p. 1221]

Xuan Wang, Jiang Xu, Wei Zhang, Xiaowen Wu, Yaoyao Ye, Zhehui Wang, Mahdi Nikdast and Zhe Wang

Adaptive Thermal Management for Portable System Batteries by Forced Convection Cooling [p. 1225]

Qing Xie, Siyu Yue, Massoud Pedram, Donghwa Shin and Naehyuck Chang

9.4: Emerging Architectures

Moderators: Yvain Thonnart - CEA-Leti, FR; Michael Niemier - University of Notre Dame, US

Sparse-Rotary Oscillator Array (SROA) Design for Power and Skew Reduction [p. 1229]

Ying Teng and Baris Taskin

Reversible Logic Synthesis of k-Input, m-Output Lookup Tables [p. 1235]

Alireza Shafaei, Mehdi Saeedi and Massoud Pedram

3D-MMC: A Modular 3D Multi-Core Architecture with Efficient Resource Pooling [p. 1241]

Tiansheng Zhang, Alessandro Cevrero, Giulia Beanato, Panagiotis Athanasopoulos, Ayse K. Coskun and Yusuf Leblebici

Cache Coherence Enabled Adaptive Refresh for Volatile STT-RAM [p. 1247]

Jianhua Li, Liang Shi, Qing'an Li, Chun Jason Xue, Yiran Chen and Yinlong Xu

Is TSV-based 3D Integration Suitable for Inter-die Memory Repair? [p. 1251]

Mihai Lefter, George R. Voicu, Mottaqiallah Taouil, Marius Enachescu, Said Hamdioui and Sorin D. Cotofana

Thermomechanical Stress-Aware Management for 3D IC Designs [p. 1255]

Qiaosha Zou, Tao Zhang, Eren Kursun and Yuan Xie

9.5: Manufacturing and Design Security

Moderators: Fresco Regazzoni - TU Delft / University of Lugano, CH; Patrick Schaumont - Virginia Tech, US

Is Split Manufacturing Secure? [p. 1259]

Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu and Ramesh Karri

Trojan Detection via Delay Measurements: A New Approach to Select Paths and Vectors to Maximize Effectiveness and Minimize Cost [p. 1265]

Byeongju Cha and Sandeep K. Gupta

High-Sensitivity Hardware Trojan Detection Using Multimodal Characterization [p. 1271]

Kangqiao Hu, Abdullah Nazma Nowroz, Sherief Reda and Farinaz Koushanfar

Reverse Engineering Digital Circuits Using Functional Analysis [p. 1277]

Pramod Subramanyan, Nestan Tsiskaridze, Kanika Pasricha, Dillon Reisman, Adriana Susnea and Sharad Malik

A Practical Testing Framework for Isolating Hardware Timing Channels [p. 1281]

Jason Oberg, Sarah Meiklejohn, Timothy Sherwood and Ryan Kastner

9.6: Improving IC Quality and Lifetime Though Advanced Characterization

Moderators: Rob Aitken - ARM, US; Mehdi Tahoori - Karlsruhe Institute of Technology, DE

Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis and Modeling [p. 1285]

Yu Cai, Erich F. Haratsch, Onur Mutlu and Ken Mai

Efficient Importance Sampling for High-sigma Yield Analysis with Adaptive Online Surrogate Modeling [p. 1291]

Jian Yao, Zuochang Ye and Yan Wang

Metastability Challenges for 65nm and Beyond; Simulation and Measurements [p. 1297]

Salomon Beer, Ran Ginosar, Jerome Cox, Tom Chaney and David M. Zar

Design and Implementation of an Adaptive Proactive Reconfiguration Technique for SRAM Caches [p. 1303]

Peyman Pouyan, Esteve Amat, Francesc Moll and Antonio Rubio

9.7: Design and Scheduling

Moderators: Giuseppe Lipari - ENS - Cachan, FR; Stefan Petters - CISTER/INESC-TEC, ISEP, PT

Architecture and Optimal Configuration of a Real-Time Multi-Channel Memory Controller [p. 1307]

Manil Dev Gomony, Benny Akesson and Kees Goossens

Holistic Design Parameter Optimization of Multiple Periodic Resources in Hierarchical Scheduling [p. 1313]

Man-Ki Yoon, Jung-Eun Kim, Richard Bradford and Lui Sha

Robust and Extensible Task Implementations of Synchronous Finite State Machines [p. 1319]

Qi Zhu, Peng Deng, Marco Di Natale and Haibo Zeng

FBLT: A Real-Time Contention Manager with Improved Schedulability [p. 1325]

Mohammed Elshambakey and Binoy Ravindran

A Virtual Prototyping Platform for Real-time Systems with a Case Study for a Two-wheeled Robot [p. 1331]

Daniel Mueller-Gritschneder, Kun Lu, Erik Wallander, Marc Greim and Ulf Schlichtmann

Sufficient Real-Time Analysis for an Engine Control Unit with Constant Angular Velocities [p. 1335]

Victor Pollex, Timo Feld, Frank Slomka, Ulrich Margull, Ralph Mader and Gerhard Wirrer

10.1: HOT TOPIC: Smart Data Centers Design and Optimization

Organizer: David Atienza - EPFL, CH
Moderators: Roman Hermida - UCM, ES; Ayse Coskun - Boston University, US

Roadmap towards Ultimately-Efficient Zeta-Scale Datacenters [p. 1339]

Patrick Ruch, Thomas Brunschwiler, Stephan Paredes, Ingmar Meijer, and Bruno Michel

Correlation-Aware Virtual Machine Allocation for Energy-Efficient Datacenters [p. 1345]

Jungsoo Kim, Martino Ruggiero, David Atienza and Marcel Lederberger

Resource Efficient Computing for Warehouse-scale Datacenters [p. 1351]

Christos Kozyrakis

10.2: EMBEDDED TUTORIAL: On the Use of GP-GPUs for Accelerating Computing Intensive EDA Applications

Organizer: Franco Fummi - University of Verona, IT
Moderators: Franco Fummi - University of Verona, IT; Florian Letombe - SpringSoft, FR

On the Use of GP-GPUs for Accelerating Compute-intensive EDA Applications [p. 1357]

Valeria Bertacco, Debapriya Chatterjee, Nicola Bombieri, Franco Fummi, Sara Vinco, A.M. Kaushik, Hiren D. Patel

10.3: Thermal Analysis and Power Optimization Techniques

Moderators: Siddharth Garg - University of Waterloo, CA; Yiran Chen - University of Pittsburgh, US

Substitute-and-Simplify: A Unified Design Paradigm for Approximate and Quality Configurable Circuits [p. 1367]

Swagath Venkataramani, Kaushik Roy and Anand Raghunathan

Enhancing Multicore Reliability through Wear Compensation in Online Assignment and Scheduling [p. 1373]

Thidapat Chantem, Yun Xiang, X. Sharon Hu and Robert P. Dick

NUMANA: A Hybrid Numerical and Analytical Thermal Simulator for 3-D ICs [p. 1379]

Yu-Min Lee, Tsung-Heng Wu, Pei-Yu Huang and Chi-Ping Yang

Explicit Transient Thermal Simulation of Liquid-Cooled 3D ICs [p. 1385]

Alain Fourmigue, Giovanni Beltrame and Gabriela Nicolescu

Mitigating Dark Silicon Problems Using Superlattice-based Thermoelectric Coolers [p. 1391]

Francesco Paterna and Sherief Reda

Run-time Probabilistic Detection of Miscalibrated Thermal Sensors in Many-core Systems [p. 1395]

Jia Zhao, Shiting (Justin) Lu, Wayne Burleson and Russell Tessier

10.4: Abstraction Techniques and SAT/SMT-Based Optimizations

Moderators: Fahim Rahim - Atrenta, FR; Julian Schmaltz - Open University of the Netherlands, NL

GLA: Gate-Level Abstraction Revisited [p. 1399]

Alan Mishchenko, Niklas Een, Robert Brayton, Jason Baumgartner, Hari Mony and Pradeep Nalla

Lemma Localization: A Practical Method for Downsizing SMT-Interpolants [p. 1405]

Florian Pigorsch and Christoph Scholl

Core Minimization in SAT-based Abstraction [p. 1411]

Anton Belov, Huan Chen, Alan Mishchenko and Joao Marques-Silva

Optimization Techniques for Craig Interpolant Compaction in Unbounded Model Checking [p. 1417]

G. Cabodi, C. Loiacono and D. Vendraminetto

Formal Analysis of Steady State Errors in Feedback Control Systems Using HOL-Light [p. 1423]

Osman Hasan and Muhammad Ahmad

A Novel Concurrent Cache-friendly Binary Decision Diagram Construction for Multi-core Platforms [p. 1427]

Mahmoud Elbayoumi, Michael S. Hsiao and Mustafa ElNainay

10.5: Design and Verification of Mixed-Signal Circuits

Moderators: Catherine Dehollain - EPFL, CH; Gunhan Dundar - Bogazici University, TR

A Low-Power and Low-Voltage BBPLL-Based Sensor Interface in 130nm CMOS for Wireless Sensor Networks [p. 1431]

Jelle Van Rethy, Hans Danneels, Valentijn De Smedt, Wim Dehaene and Georges Gielen

Reachability Analysis of Nonlinear Analog Circuits through Iterative Reachable Set Reduction [p. 1436]

Seyed Nematollah Ahmadyan and Shohba Vasudevan

Formal Verification of Analog Circuit Parameters across Variation Utilizing SAT [p. 1442]

Merritt Miller and Forrest Brewer

Extracting Analytical Nonlinear Models from Analog Circuits by Recursive Vector Fitting of Transfer Function Trajectories [p. 1448]

Dimitri De Jonghe, Dirk Deschrijver, Tom Dhaene and Georges Gielen

Statistical Modeling with the Virtual Source MOSFET Model [p. 1454]

Li Yu, Lan Wei, Dimitri Antoniadis, Ibrahim Elfadel and Duane Boning

Automatic Circuit Sizing Technique for the Analog Circuits with Flexible TFTs Considering Process Variation and Bending Effects [p. 1458]

Yen-Lung Chen, Wan-Rong Wu, Guan-Ruei Lu and Chien-Nan Jimmy Liu

10.6: On-Line Testing Techniques

Moderators: Cecilia Metra - University of Bologna, IT; Cristiana Bolchini - Politecnico Di Milano, IT

On-Line Functionally Untestable Fault Identification in Embedded Processor Cores [p. 1462]

P. Bernardi, M. Bonazza, E. Sanchez, M. Sonza Reorda and O. Ballan

Capturing Vulnerability Variations for Register Files [p. 1468]

Javier Carretero, Enric Herrero, Matteo Monchiero and Tanausú Ramírez and Xavier Vera

Error Detection in Ternary CAMs Using Bloom Filters [p. 1474]

Salvatore Pontarelli, Marco Ottavi, Adrian Evans and Shi-Jie Wen

AVF-driven Parity Optimization for MBU Protection of In-core Memory Arrays [p. 1480]

Michail Maniatakos, Maria K. Michael and Yiorgos Makris

An Enhanced Double-TSV Scheme for Defect Tolerance in 3D-IC [p. 1486]

Hsiu-Chuan Shih and Cheng-Wen Wu

Mempack: An Order of Magnitude Reduction in the Cost, Risk, and Time for Memory Compiler Certification [p. 1490]

Kartik Mohanram, Matthew Wartell and Sundar Iyer

Exploiting Replicated Checkpoints for Soft Error Detection and Correction [p. 1494]

Fahrettin Koc, Kenan Bozdas, Burak Karsli and Oguz Ergin

10.7: Embedded Software for Many-Core Architectures

Moderators: Oliver Bringmann - University of Tübingen, DE; Sébastien Le Beux - Lyon Institute of Nanotechnology, FR

Game-Theoretic Analysis of Decentralized Core Allocation Schemes on Many-Core Systems [p. 1498]

Stefan Wildermann, Tobias Ziermann and Jürgen Teich

Enabling Fine-Grained OpenMP Tasking on Tightly-Coupled Shared Memory Clusters [p. 1504]

Paolo Burgio, Giuseppe Tagliavini, Andrea Marongiu and Luca Benini

ARTM: A Lightweight Fork-join Framework for Many-core Embedded Systems [p. 1510]

Maroun Ojail, Raphael David, Yves Lhuillier and Alexandre Guerre

Pipelets: Self-Organizing Software Pipelines for Many-Core Architctures [p. 1516]

Janmartin Jahn and Jörg Henkel

An Integrated Approach for Managing the Lifetime of Flash-Based SSDs [p. 1522]

Sungjin Lee, Taejin Kim, Ji-Sung Park and Jihong Kim

10.8: PANEL: Will 3D-IC Remain a Technology of the Future...Even in the Future?

Organizer: Marco Casale-Rossi - Synopsys, US
Moderators: Giovanni De Micheli - EPFL, CH; Marco Casale-Rossi - Synopsys, US

Invited Speaker: Patrick Leduc
Panelists: Patrick Blouet, Brendan Farley, Anna Fontanelli, Dragomir Milojevic, Steve Smith

PANEL: Will 3D-IC Remain a Technology of the Future...Even in the Future? [p. 1526]

11.1: HOT TOPIC: Smart Health

Organizers and Moderators: Daniela De Venuto - Politecnico di Bari, IT; Alberto Sangiovanni Vincentelli - University of California, Berkeley, US

Dr. Frankenstein's Dream Made Possible: Implanted Electronic Devices [p. 1531]

Daniela De Venuto and Alberto Sangiovanni Vincentelli

Addressing the Healthcare Cost Dilemma by Managing Health instead of Managing Illness - An Opportunity for Wearable Wireless Sensors [p. 1537]

Chris Van Hoof and Julien Penders

Electronic Implants: Power Delivery and Management [p. 1540]

Jacopo Olivo, Sara S. Ghoreishizadeh, Sandro Carrara and Giovanni De Micheli

Cyborg Insects, Neural Interfaces and Other Things: Building Interfaces between the Synthetic and the Multicellular [p. 1546]

J. Van Kleef, T. Massey, P. Ledochowitsch, R. Muller, R. Tiefenauer, T. Blanche, Hirotaka Sato and M.M. Maharbiz

11.2: High-Level Synthesis and Coarse-Grained Reconfigurable Architectures

Moderators: Philippe Coussy - Universite de Bretagne-Sud/Lab-STICC, FR; Fadi Kurdahi - University of California Irvine, US

Share with Care: A Quantitative Evaluation of Sharing Approaches in High-level Synthesis [p. 1547]

Alex Kondratyev, Luciano Lavagno, Mike Meyer and Yosinori Watanabe

FPGA Latency Optimization Using System-level Transformations and DFG Restructuring [p. 1553]

Daniel Gomez-Prado, Maciej Ciesielski and Russell Tessier

A Transparent and Energy Aware Reconfigurable Multiprocessor Platform for Simultaneous ILP and TLP Exploitation [p. 1559]

Mateus Beck Rutzig, Antonio Carlos S. Beck and Luigi Carro

High-Level Modeling and Synthesis for Embedded FPGAs [p. 1565]

Xiaolin Chen, Shuai Li, Jochen Schleifer, Thomas Coenen, Anupam Chattopadhyay, Gerd Ascheid and Tobias G. Noll

Scheduling Independent Liveness Analysis for Register Binding in High Level Synthesis [p. 1571]

Vito Giovanni Castellana and Fabrizio Ferrandi

Fast Shared On-Chip Memory Architecture for Efficient Hybrid Computing with CGRAs [p. 1575]

Jongeun Lee, Yeonghun Jeong and Sungsok Seo

Compiling Control-Intensive Loops for CGRAs with State-Based Full Predication [p. 1579]

Kyuseung Han, Kiyoung Choi and Jongeun Lee

11.3: Efficient NoC Routing Mechanisms

Moderators: Fabien Clermidy - CEA-Leti, FR; Jose Flich - Technical University of Valencia, ES

DeBAR: Deflection Based Adaptive Router with Minimal Buffering [p. 1583]

John Jose, Bhawna Nayak, Kranthi Kumar and Madhu Mutyam

Contrasting Wavelength-Routed Optical NoC Topologies for Power-Efficient 3D-Stacked Multicore Processors Using Physical-Layer Analysis [p. 1589]

Luca Ramini, Paolo Grani, Sandro Bartolini and Davide Bertozzi

Topology-Agnostic Fault-Tolerant NoC Routing Method [p. 1595]

Eduardo Wachter, Augusto Erichsen, Alexandre Amory and Fernando Moraes

Fault-Tolerant Routing Algorithm for 3D NoC Using Hamiltonian Path Strategy [p. 1601]

Masoumeh Ebrahimi, Masoud Daneshtalab and Juha Plosila

Modeling and Analysis of Fault-tolerant Distributed Memories for Networks-on-Chip [p. 1605]

Abbas BanaiyanMofrad, Nikil Dutt and Gustavo Girão

11.4: System-Level Modelling for Physical Properties

Moderators: Frank Oppenheimer - OFFIS, DE; François Pêcheux - UPMC, FR

System-Level Modeling of Energy in TLM for Early Validation of Power and Thermal Management [p. 1609]

Tayeb Bouhadiba, Matthieu Moy and Florence Maraninchi

System-Level Modeling and Microprocessor Reliability Analysis for Backend Wearout Mechanisms [p. 1615]

Chang-Chih Chen and Linda Milor

Automatic Success Tree-Based Reliability Analysis for the Consideration of Transient and Permanent Faults [p. 1621]

Hananeh Aliee, Michael Glaß, Felix Reimann and Jürgen Teich

Hybrid Prototyping of Multicore Embedded Systems [p. 1627]

Ehsan Saboori and Samar Abdi

11.5: Energy Challenges for Multi-Core and NoC Architectures

Moderators: Alberto Garcia-Ortiz - University of Bremen, DE; Domenik Helms - OFFIS, DE

Communication and Migration Energy Aware Design Space Exploration for Multicore Systems with Intermittent Faults [p. 1631]

Anup Das, Akash Kumar and Bharadwaj Veeravalli

40.4fJ/bit/mm Low-Swing On-Chip Signaling with Self-Resetting Logic Repeaters Embedded within a Mesh NoC in 45nm SOI CMOS [p. 1637]

Sunghyun Park, Masood Qazi, Li-Shiuan Peh and Anantha P. Chandrakasan

3D Reconfgurable Power Switch Network for Demand-supply Matching between Multi-output Power Converters and Many-core Microprocessors [p. 1643]

Kanwen Wang, Hao Yu, Benfei Wang and Chun Zhang

Thermal-Aware Datapath Merging for Coarse-Grained Reconfigurable Processors [p. 1649]

Sotirios Xydis, Gianluca Palermo and Cristina Silvano

11.6: Modelling and Design for Signal and Power Integrity

Moderators: Stefano Grivet-Talocia - Politecnico di Torino, IT; Piero Triverio - University of Toronto, CA

Placement Optimization of Power Supply Pads Based on Locality [p. 1655]

Pingqiang Zhou, Vivek Mishra and Sachin S. Sapatnekar

GPU-Friendly Floating Random Walk Algorithm for Capacitance Extraction of VLSI Interconnects [p. 1661]

Kuangya Zhai, Wenjian Yu and Hao Zhuang

Periodic Jitter and Bounded Uncorrelated Jitter Decomposition Using Incoherent Undersampling [p. 1667]

Nicholas L. Tzou, Debesh Bhatta, Sen-Wen Hsiao and Abhijit Chatterjee

Crosstalk Avoidance Codes for 3D VLSI [p. 1673]

Rajeev Kumar and Sunil P. Khatri

Large-Scale Flip-Chip Power Grid Reduction with Geometric Templates [p. 1679]

Zhuo Feng

11.7: Powerful Aging

Moderators: Jose Pineda de Gyvez - NXP Semiconductors, NL; Mehdi Tahoori - Karlsruhe Institute of Technology, DE

Impact of Adaptive Voltage Scaling on Aging-Aware Signoff [p. 1683]

Tuck-Boon Chan, Wei-Ting Jonas Chan and Andrew B. Kahng

A Parallel Fast Transform-Based Preconditioning Approach for Electrical-Thermal Co- Simulation of Power Delivery Networks [p. 1689]

Konstantis Daloukas, Alexia Marnari, Nestor Evmorfopoulos, Panagiota Tsompanopoulou and George I. Stamoulis

Hierarchically Focused Guardbanding: An Adaptive Approach to Mitigate PVT Variations and Aging [p. 1695]

Abbas Rahimi, Luca Benini and Rajesh K. Gupta

Effective Power Network Prototyping via Statistical-Based Clustering and Sequential Linear Programming [p. 1701]

Sean Shih-Ying Liu, Chieh-Jui Lee, Chuan-Chia Huang, Hung-Ming Chen, Chang-Tzu Lin and Chia-Hsin Lee

A Network-Flow Based Algorithm for Power Density Mitigation at Post-Placement Stage [p. 1707]

Sean Shih-Ying Liu, Ren-Guo Luo and Hung-Ming Chen

An Efficient Wirelength Model for Analytical Placement [p. 1711]

B.N.B. Ray and Shankar Balachandran

11.8: EMBEDDED TUTORIAL: Advances in Asynchronous Logic: From Principles to GALS & NoC, Recent Industry Applications, and Commercial CAD Tools

Organizer: Pascal Vivet - CEA-Leti, FR
Moderators: Robin Wilson - STMicroelectronics, FR; Beigné Edith - CEA-Leti, FR

Advances in Asynchronous Logic: From Principles to GALS & NoC, Recent Industry Applications, and Commercial CAD Tools [p. 1715]

Alex Yakovlev, Pascal Vivet, Marc Renaudin

12.1: HOT TOPIC: Internet of Energy - Connecting Smart Mobility in the Cloud

Organizer: Ovidiu Vermesan - SINTEF, NO
Session chairs: Andrea Acquavivia - Politecnico di Torino, IT; Marcello Coppola - STMicroelectronics, FR

Interactions of Large Scale EV Mobility and Virtual Power Plants [p. 1725]

R. Mock, J. Reinschke, T. S. Cinotti, L. Bononi

Innovative Energy Storage Solutions for Future Electromobility in Smart Cities [p. 1730]

Kevin Green, Salvador Rodriguez González, Ruud Wijtvliet

Automotive Ethernet: In-vehicle Networking and Smart Mobility [p. 1735]

Peter Hank, Steffen Müller, Ovidiu Vermesan, Jeroen Van Den Keybus

Smart, Connected and Mobile: Architecting Future Electric Mobility Ecosystems [p. 1740]

Ovidiu Vermesan, Lars-Cyril Blystad, Reiner John, Peter Hank, Roy Bahr, Alessandro Moscatelli

e-Mobility - The Next Frontier for Automotive Industry [p. 1745]

Roberto Zafalon, Giovanni Coppola, Ovidiu Vermesan

Semiconductor Technologies for Smart Mobility Management [p. 1749]

Reiner John, Martin Schulz, Ovidiu Vermesan, Kai Kriegel

12.2: Methodologies to Improve Yield, Reliability and Security in Embedded Systems

Moderators: Luciano Lavagno - Politecnico di Torino, IT; Jürgen Teich - University of Erlangen-Nuremberg, DE

A New Paradigm for Trading Off Yield, Area and Performance to Enhance Performance per Wafer [p. 1753]

Yue Gao, Melvin A. Breuer and Yanzhi Wang

Leveraging Variable Function Resilience for Selective Software Reliability on Unreliable Hardware [p. 1759]

Semeen Rehman, Muhammad Shafique, Pau Vilimelis Aceituno, Florian Kriebel, Jian-Jia Chen and Jörg Henkel

Optimization of Secure Embedded Systems with Dynamic Task Sets [p. 1765]

Ke Jiang, Petru Eles and Zebo Peng

12.3: NoC Mapping and Synthesis

Moderators: Andreas Hansson - ARM, UK; Jaime Murillo - EPFL, CH

Shared Memory Aware MPSoC Software Deployment [p. 1771]

Timo Schönwald, Alexander Viehl, Oliver Bringmann and Wolfgang Rosenstiel

Fast and Optimized Task Allocation Method for Low Vertical Link Density 3-Dimensional Networks-on-Chip Based Many Core Systems [p. 1777]

Haoyuan Ying, Thomas Hollstein and Klaus Hofmann

A Spectral Clustering Approach to Application-Specific Network-on-Chip Synthesis [p. 1783]

Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig and Ulf Schlichtmann

12.4: Emerging Logic

Moderators: Aida Todri-Sanial - CNRS-LIRMM, FR; Marco Ottavi - University of Rome "Tor Vegata", IT

A SPICE-Compatible Model of Graphene Nano-Ribbon Field-Effect Transistors Enabling Circuit-Level Delay and Power Analysis under Process Variation [p. 1789]

Ying-Yu Chen, Artem Rogachev, Amit Sangai, Giuseppe Iannaccone, Gianluca Fiori and Deming Chen

Systematic Design of Nanomagnet Logic Circuits [p. 1795]

Indranil Palit, X. Sharon Hu, Joshep Nahas and Michael Niemier

Defect-Tolerant Logic Hardening for Crossbar-based Nanosystems [p. 1801]

Yehua Su and Wenjing Rao

On Reconfigurable Single-Electron Transistor Arrays Synthesis Using Reordering Techniques [p. 1807]

Chang-En Chiang, Li-Fu Tang, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen, Suman Datta and Vijaykrishnan Narayanan

12.5: Emerging Technology Architectures for Energy-Efficient Memories

Moderators: Marisa López-Vallejo - Universidad Politecnica Madrid, ES; Naehyuck Chang - Seoul National University, KR

D-MRAM Cache: Enhancing Energy Efficiency with 3T-1MTJ DRAM / MRAM Hybrid Memory [p. 1813]

Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa and Hiroshi Nakamura

Leveraging Sensitivity Analysis for Fast, Accurate Estimation of SRAM Dynamic Write Vmin [p. 1819]

James Boley, Vikas Chandra, Robert Aitken and Benton Calhoun

DWM-TAPESTRI - An Energy Efficient All-Spin Cache Using Domain Wall Shift Based Writes [p. 1825]

Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy and Anand Raghunathan

12.6: Clock Distribution and Analogue Circuit Synthesis

Moderators: Tiziano Villa - University of Verona, IT; Georges Gielen - Katholieke Universiteit Leuven, BE

Co-Synthesis of Data Paths and Clock Control Paths for Minimum-Period Clock Gating [p. 1831]

Wen-Pin Tu, Shih-Hsu Huang and Chun-Hua Cheng

Slack Budgeting and Slack to Length Converting for Multi-Bit Flip-Flop Merging [p. 1837]

Chia-Chieh Lu and Rung-Bin Lin

Area Optimization on Fixed Analog Floorplans Using Convex Area Functions [p. 1843]

A. Unutulmaz, G. Dündar and F.V. Fernández

PAGE: Parallel Agile Genetic Exploration towards Utmost Performance for Analog Circuit Design [p. 1849]

Po-Cheng Pan, Hung-Ming Chen and Chien-Chih Lin

12.7: Physical Design

Moderators: Carl Sechen - University of Texas at Dallas, US; Bill Swartz - InternetCAD, US

Fast and Efficient Lagrangian Relaxation-Based Discrete Gate Sizing [p. 1855]

Vinicius S. Livramento, Chrystian Guth, José Luís Güntzel and Marcelo O. Johann

Enhanced Metamodeling Techniques for High-Dimensional IC Design Estimation Problems [p. 1861]

Andrew B. Kahng, Bill Lin and Siddhartha Nath

Sub-Quadratic Objectives in Quadratic Placement [p. 1867]

Markus Struzyna

CATALYST: Planning Layer Directives for Effective Design Closure [p. 1873]

Yaoguang Wei, Zhuo Li, Cliff Sze, Shiyan Hu, Charles J. Alpert and Sachin S. Sapatnekar

12.8: EMBEDDED TUTORIAL: Closed-Loop Control for Power and Thermal Management in Multi-core Processors: Formal Methods and Industrial Practice

Organizer: Ibrahim Elfadel - Masdar Institute of Science and Technology, AE
Moderators: Petru Eles - Linkopings University, SE; Jose Ayala - Complutense University of Madrid, ES

Closed-Loop Control for Power and Thermal Management in Multi-core Processors: Formal Methods and Industrial Practice [p. 1879]

Ibrahim (Abe) M. Elfadel, Radu Marculescu and David Atienza