DATE Executive Committee

Technical Program Chairs

DATE Sponsors Committee

Technical Program Committee

Reviewers

Foreword

Best Paper Awards

Tutorials

- EDA Challenges in the Converging Application World [p. 1]
*R. Penning de Vries*- Sociology of Design and EDA [p. 2]
*W. C. Rhines*

- Communication-Aware Allocation and Scheduling Framework for Stream-Oriented Multi-Processor Systems-on-Chip [p. 3]
*M. Ruggiero, A. Guerri, D. Bertozzi, F. Poletti, and M. Milano*- Efficient Link Capacity and QoS Design for Network-on-Chip [p. 9]
*Z. Guz, I. Walter, E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny*- Supporting Task Migration in Multi-Processor Systems-on-Chip: A Feasibility Study [p. 15]
*S. Bertozzi, A. Acquaviva, D. Bertozzi, and A. Poggiali*

- Time Domain Model Order Reduction by Wavelet Collocation Method [p. 21]
*X. Zeng, L. Feng, Y. Su, W. Cai, D. Zhou, C. Chiang*- Large Power Grid Analysis Using Domain Decomposition [p. 27]
*Q. Zhou, K. Sun, K. Mohanram and D. C. Sorensen*- Analysis and Modeling of Power Grid Transmission Lines [p. 33]
*J. Balachandran, S. Brebels, G. Carchon, T. Webers, W. De Raedt, B. Nauwelaers, and E. Beyne*- A Logarithmic Full-Chip Thermal Analysis Algorithm Based on Multi-Layer Green's Function [p. 39]
*B. Wang and P. Mazumder*

- Large Scale RLC Circuit Analysis Using RLCG-MNA Formulation [p. 45]
*Y. Tanji, T. Watanabe, H. Kubota and H. Asai*

- Soft Delay Error Analysis in Logic Circuits [p. 47]
*B. Gill, C. Papachristou and F. Wolff*- A Built-In Redundancy-Analysis Scheme for RAMS with 2D Redundancy Using 1D Local Bitmap [p. 53]
*T.-W. Tseng, J.-F. Li and D.-M. Chang*- Analysis of the Impact of Bus Implemented EDCs on On-Chip SSN [p. 59]
*D. Rossi, C. Steiner and C. Metra*- Optimal Periodic Testing of Intermittent Faults in Embedded Pipelined Processor Applications [p. 65]
*N. Kranitis, A. Merentitis, N. Laoutaris, G. Theodorou, A. Paschalis, D. Gizopoulos and C. Halatsis*

- Berger Code-Based Concurrent Error Detection in Asynchronous Burst-Mode Machines [p. 71]
*S. Almukhaizim and Y. Makris*

- Two-Phase Resonant Clocking for Ultra-Low-Power Hearing Aid Applications [p. 73]
*F. Carbognani, F. Buergin, N. Felber, H. Kaeslin and W. Fichtner*- A Network-On-Chip with 3gbps/Wire Serialized On-Chip Interconnect Using Adaptive Control Schemes [p. 79]
*S.-J. Lee, K. Kim, H. Kim, N. Cho and H.-J. Yoo*- A Single Photon Avalanche Diode Array Fabricated in Deep-Submicron CMOS Technology [p. 81]
*C. Niclass, M. Sergio and E. Charbon*

- MATLAB/Simulink for Automotive Systems Design [p. 87]
*J. Friedman*- Model-Based Development of In-Vehicle Software [p. 89]
*M. Conrad and H. Doerr*- Model-Based Testing of Automotive Electronics [p. 91]
*K. Lamberg*- Designing Signal Processing Systems for FPGAs [p. 92]
*J. Heighton*- From UML/SysML to Matlab/Simulink: Current State and Future Perspectives [p. 93]
*Y. Vanderperren and W. Dehaene*

- An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles [p. 94]
*E. Viaud, F. Pecheux and A. Greiner*- Exploiting TLM and Object Introspection for System-Level Simulation [p. 100]
*G. Beltrame, D. Sciuto, C. Silvano, D. Lyonnard and C. Pilkington*- Efficient Assertion Based Verification Using TLM [p. 106]
*A. Habibi, S. Tahar, A. Samarah, D. Li and O. A. Mohamed*- Constructing Portable Compiled Instruction-Set Simulators -- An ADL-Driven Approach [p. 112]
*J. D'Errico and W. Qin*

- A Methodology for Mapping Multiple Use-Cases onto Networks on Chips [p. 118]
*S. Murali, M. Coenen, A. Radulescu, K. Goossens, and G. De Micheli*- Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness [p. 124]
*F. Angiolini, P. Meloni, S. Carta, L. Benini and L. Raffo*- A Low Complexity Heuristic for Design of Custom Network-on-Chip Architectures [p. 130]
*K. Srinivasan and K. S. Chatha*

- A Dynamically Reconfigurable Packet-Switched Network-on-Chip [p. 136]
*T. Pionteck, C. Albrecht and R. Koch*

- Arbitrary Design of High Order Noise Transfer Function for a Novel Class of Reduced-Sample- Rate Delta-Sigma-Pipeline ADCs [p. 138]
*V. Majidzadeh and O. Shoaei*- Systematic and Optimal Design of CMOS Two-Stage Opamps with Hybrid Cascode Compensation [p. 144]
*M. Yavari, O. Shoaei and A. Rodriguez-Vazquez*- Systematic Stability-Analysis Method for Analog Circuits [p. 150]
*G. Vandersteen, S. Bronckers, P. Dobrovolny and Y. Rolain*- ALAMO: An Improved Sigma-Space Based Methodology for Modeling Process Parameter Variations in Analog Circuits [p. 156]
*H. Zhang, Y. Zhao and A. Doboli*

- A Synthesis Tool for Power-Efficient Base-Band Filter Design [p. 162]
*V. Giannini, P. Nuzzo, F. De Bernardinis, J. Craninckx, B. Come, S. D'Amico and A. Baschirotto*

- An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits [p. 164]
*R. Rao, K. Chopra, D. Blaauw and D. Sylvester*- Low-Cost and Highly Reliable Detector for Transient and Crosstalk Faults Affecting FPGA Interconnects [p. 170]
*M. Omaña, J. M. Cazeaux; D. Rossi and C. Metra*- Evaluating Coverage of Error Detection Logic for Soft Errors Using Formal Methods [p. 176]
*U. Krautz, M. Pflanz, C. Jacobi, H. W. Tast, K. Weber and H. T. Vierhaus*- Soft-Error Classification and Impact Analysis on Real-Time Operating Systems [p. 182]
*N. Ignat, B. Nicolescu, Y. Savaria and G. Nicolescu*

- 40Gbps De-Layered Silicon Protocol Engine for TCP Record [p. 188]
*H. Shrikumar*- A Reconfigurable HW/SW Platform for Computation Intensive High-Resolution Real-Time Digital Film Applications [p. 194]
*A. do Carmo Lucas, S. Heithecker, P. Rueffer, R. Ernst, H. Rueckert, G. Wischermann, K. Gebel, R. Fach, W. Huther, S. Eichner and G. Scheller*- Disclosing the LDPC Code Decoder Design Space [p. 200]
*T. Brack, F. Kienle and N. Wehn*

- Automating Processor Customisation: Optimised Memory Access and Resource Sharing [p. 206]
*R. Dimond, O. Mencer and W. Luk*- Automatic Identification of Application-Specific Functional Units with Architecturally Visible Storage [p. 212]
*P. Biswas, N. Dutt, P. Ienne and L. Pozzi*- Combining Algorithm Exploration with Instruction Set Design: A Case Study in Elliptic Curve Cryptography [p. 218]
*J. Groszschaedl, P. Ienne, L. Pozzi, S. Tillich and A. K. Verma*- Simultaneously Improving Code Size, Performance, and Energy in Embedded Processors [p. 224]
*A. Zmily and C. Kozyrakis*

- Quantitative Analysis of Transaction Level Models for the AMBA Bus [p. 230]
*G. Schirner and R. Doemer*- Combining Simulation and Formal Methods for System-Level Performance Analysis [p. 236]
*S. Kuenzli, F. Poletti, L. Benini and L. Thiele*- Formal Performance Analysis and Simulation of UML/SysML Models for ESL Design [p. 242]
*A. Viehl, T. Schoenwald, O. Bringmann and W. Rosenstiel*- Performance Evaluation for System-on-Chip Architectures Using Trace-Based Transaction Level Simulation [p. 248]
*T. Wild, A. Herkersdorf and R. Ohlendorf*

Moderator: J. Cohn, IBM Microelectronics, US

- Is "Network" the Next "Big Idea" in Design? [p. 254]
*R. Marculescu, J. Rabaey and A. Sangiovanni-Vincentelli*

- Verifying Analog Oscillator Circuits Using Forward/Backward Abstraction Refinement [p. 257]
*G. Frehse, B. H. Krogh and R. A. Rutenbar*- Efficient AC Analysis of Oscillators Using Least-Squares Methods [p. 263]
*T. Mei and J. Roychowdhury*- Double-Strength CAFFEINE: Fast Template-Free Symbolic Modeling of Analog Circuits via Implicit Canonical Form Functions and Explicit Introns [p. 269]
*T. McConaghy and G. Gielen*- Top-Down Heterogeneous Synthesis of Analog and Mixed-Signal Systems [p. 275]
*E. Martens and G. Gielen*

- Nonlinear Model Order Reduction Using Remainder Functions [p. 281]
*J. A. Martinez, S. P. Levitan and D. M. Chiarulli*- Efficient Temperature-Dependent Symbolic Sensitivity Analysis and Symbolic Performance Evaluation in Analog Circuit Synthesis [p. 283]
*H. Yang and R. Vemuri*

- Hierarchy-Aware and Area-Efficient Test Infrastructure Design for Core-Based System Chips [p. 285]
*A. Sehgal, S. K. Goel, E. J. Marinissen and K. Chakrabarty*- Power Constrained and Defect-Probability Driven SoC Test Scheduling with Test Set Partitioning [p. 291]
*Z. He, Z. Peng and P. Eles*- Power-Constrained Test Scheduling for Multi-Clock Domain SoCs [p. 297]
*T. Yoneda, K. Masuda and H. Fujiwara*- Reuse-Based Test Access and Integrated Test Scheduling for Network-on-Chip Systems [p. 303]
*C. Liu, Z. Link and D. K. Pradhan*

- A Design for Failure Analysis (DFFA) Technique to Ensure Incorruptible Signatures [p. 309]
*S. Kundu*

- Test Generation for Combinational Quantum Cellular Automata (QCA) Circuits [p. 311]
*P. Gupta, N. K. Jha and L. Lingappan*- Analysis and Synthesis of Quantum Circuits by Using Quantum Decision Diagrams [p. 317]
*A. Abdollahi and M. Pedram*- Droplet Routing in the Synthesis of Digital Microfluidic Biochips [p. 323]
*F. Su, W. Hwang and K. Chakrabarty*- Priority Scheduling in Digital Microfluidics-Based Biochips [p. 329]
*A. J. Ricketts, K. Irick, N. Vijaykrishnan and M. J. Irwin*

- A Hybrid Framework for Design and Analysis of Fault-Tolerant Architectures for Nanoscale Molecular Crossbar Memories [p. 335]
*D. Bhaduri, S. Shukla, D. Coker, V. Taylor, P. Graham and M. Gokhale*- (774)Optical Routing for 3D System-on-Package [p. 337]
*J. R. Minz, S. Thyagaraja and S.-K. Lim*

- Distributed Loop Controller Architecture for Multi-Threading in Uni-Threaded VLIW Processors [p. 339]
*P. Raghavan, A. Lambrechts, M. Jayapala, F. Catthoor and D. Verkest*- Compositional, Efficient Caches for a Chip Multi-Processor [p. 345]
*A. M. Molnos, M. J. M. Heijligers, S. D. Cotofana and J. T. J. Van Eijndhoven*- Efficient Design Space Exploration of High Performance Embedded Out-of-Order Processors [p. 351]
*S. Eyerman, L. Eeckhout and K. De Bosschere*- Application-Specific Reconfigurable XOR-Indexing to Eliminate Cache Conflict Misses [p. 357]
*H. Vandierendonck, P. Manet and J.-D. Legat*

- A Spatial Mapping Algorithm for Heterogeneous Coarse-Grained Reconfigurable Architectures [p. 363]
*M. Ahn, J. W. Yoon, Y. Paek, Y. Kim, M. Kiemb and K. Choi*- Compiler-Driven FPGA-Area Allocation for Reconfigurable Computing [p. 369]
*E. M. Panainte, K. Bertels and S. Vassiliadis*- Temporal Partitioning for Image Processing Based on Time-Space Complexity in Reconfigurable Architectures [p. 375]
*P. S. Brandão do Nascimento and M. E. de Lima*- System-Level Scheduling on Instruction Cell Based Reconfigurable Systems [p. 381]
*Y. Yi, I. Nousias , M. Milward, S. Khawam, T. Arslan and I. Lindsay*

Moderator: A. Ripp, MunEDA GmbH, DE

- DFM/DFY Design for Manufacturability and Yield - Influence of Process Variations and Increased Defect Sensitivity in Digital, Analogue and Mixed-Signal Circuit Design [p. 387]
*M. Buehler, J. Koehl, J. Bickford, J. Hibbeler, U. Schlichtmann, R. Sommer, M. Pronath and A. Ripp*

- Systematic Methodology for Designing Reconfigurable ΔΣ Modulator Topologies for Multimode Communication Systems [p. 393]
*Y. Wei, H. Tang and A. Doboli*- Double-Sampling Single-Loop Sigma-Delta Modulator Topologies for Broadband Applications [p. 399]
*M. Yavari, O. Shoaei and A. Rodriguez-Vazquez*- A 10 GHz 15 dB Four-Stage Distributed Amplifier in 0.18 μm CMOS Process [p. 405]
*K. K. Moez and M. I. Elmasry*

- Bootstrapped Full-Swing CMOS Driver for Low Supply Voltage Operation
*J. Garcia, J. A. Montiel-Nelson and S. Nooshabadi [p. 410]*

- An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis In SoCs [p. 412]
*P. Bernardi, E. Sánchez, M. Schillaci, G. Squillero and M. Sonza Reorda*- Timing-Reasoning-Based Delay Fault Diagnosis [p. 418]
*K. Yang and K.-.T Cheng*- Multiple-Fault Diagnosis Based on Single-Fault Activation and Single-Output Observation [p. 424]
*Y.-C. Lin and K.-T. Cheng*- Software-Based Self-Test of Processors under Power Constraints [p. 430]
*J. Zhou and H.-J. Wunderlich*

- Diagnosis of Defects on Scan Enable and Clock Trees [p. 436]
*Y. Huang and K. Gallie*

- Lock-Free Synchronization for Dynamic Embedded Real-Time Systems [p. 438]
*H. Cho, B. Ravindran and E. D. Jensen*- Performance Analysis of Greedy Shapers in Real-Time Systems [p. 444]
*E. Wandeler, A. Maxiaguine and L. Thiele*- Improved Offset-Analysis Using Multiple Timing-References [p. 450]
*R. Henia and R. Ernst*- Procrastinating Voltage Scheduling with Discrete Frequency Sets [p. 456]
*Z. Lu, Y. Zhang, M. Stan, J. Lach and K. Skadron*

- Communication and Co-Simulation Infrastructure for Heterogeneous System Integration [p. 462]
*G. Yang, X. Chen, F. Balarin, H. Hsieh and A. Sangiovanni-Vincentelli*- A SW Performance Estimation Framework for Early System-Level-Design Using Fine-Grained Instrumentation [p. 468]
*T. Kempf, K. Karuri, S. Wallentowitz, G. Ascheid, R. Leupers and H. Meyr*- A Unified System-Level Modeling and Simulation Environment for MPSoC Design: MPEG-4 Decoder Case Study [p. 474]
*V. Reyes, W. Kruijtzer, T. Bautista, G. Alkadi and A. Nuñez*

- (145)Task-Accurate Performance Modeling in SystemC for Real-Time Multi-Processor Architectures [p. 480]
*M. Streubuehr, J. Falk, C. Haubelt, J. Teich, R. Dorsch and T. Schlipf*

Moderator: O. Schliebusch, CoWare Inc, DE

- Distributed Object Models for Multi-Processor SoC's, with Application to Low-Power Multimedia Wireless Systems [p. 482]
*P. G. Paulin, C. Pilkington, M. Langevin, E. Bensoudane, O. Benny, D. Lyonnard, B. Lavigeuer and D. Lo*- Virtual Prototyping of Embedded Platforms for Wireless and Multimedia [p. 488]
*T. Kogel and M. Braun*- Application Specific NoC Design [p. 491]
*L. Benini*

- Automatic Insertion of Low Power Annotations in RTL for Pipelined Microprocessors [p. 496]
*V. Viswanath, J. A. Abraham and W. A. Hunt Jr.*- Power Analysis of Mobile 3D Graphics [p. 502]
*B. Mochocki, K. Lahiri and S. Cadambi*- Automatic Run-Time Selection of Power Policies for Operating Systems [p. 508]
*N. Pettis, J. Ridenour and Y.-H. Lu*- Energy Reduction by Workload Adaptation in a Multi-Process Environment [p. 514]
*C. Xian and Y.-H. Lu*

- Dynamic Bit-Width Adaptation in DCT : Image Quality Versus Computation Energy Trade-Off [p. 520]
*J. Park, J. H. Choi and K. Roy*

- Bus Stuttering: An Encoding Technique to Reduce Inductive Noise in Off-Chip Data Transmission [p. 522]
*B. J. LaMeres and S. P. Khatri*- Statistical Timing Analysis with Path Reconvergence and Spatial Correlations [p. 528]
*L. Zhang, Y. Hu and C.C-P. Chen*- Non-Gaussian Statistical Interconnect Timing Analysis [p. 533]
*S. Abbaspour, H. Fatemi and M. Pedram*- Cell Delay Analysis Based on Rate-of-Current Change [p. 539]
*S. Nazarian and M. Pedram*

- A Practical Method to Estimate Interconnect Responses to Variabilities [p. 545]
*F. Liu*

Moderator: C. Sebeke, Robert Bosch GmbH, DE

Panellists: C. Jung, BMW Group, DE; K. Harbich, Robert Bosch GmbH, DE; S. Fuchs, Credence Systems GmbH, DE; J. Schwarz, DaimlerChrysler AG, DE; P. Goehner, Stuttgart U, DE

- Test and Reliability Challenges in Automotive Microelectronics [p. 547]
*C. Jung, K. Harbich, S. Fuchs, J. Schwarz and P. Goehner*

- Exploring Trade-offs between Centralized versus Decentralized Automotive Architectures Using a Virtual Integration Environment [p. 548]
*S. Kanajan, H. Zeng, C. Pinello and A. Sangiovanni-Vincentelli*- Management of Complex Automotive Communication Networks [p. 554]
*T. Weber*- AutoVision - Flexible Processor Architecture for Video-assisted Driving [p. 556]
*A. Herkersdorf*- Domain Specific Model Driven Design for Automotive Electronic Control Units [p. 557]
*K. D. Mueller-Glaser*- Electric and Electronic Vehicle Architecture Assessment [p. 558]
*P. Dégardins*- Automotive Semi-Conductor Trend and Challenges [p. 559]
*P. Leteinturier*

- A Systematic IP and Bus Subsystem Modeling for Platform-Based System Design [p. 560]
*J. Um, W.-C. Kwon, S. Hong, Y.-T. Kim, K.-M. Choi, J.-T. Kong, S.-K. Eo and T. Kim*- Heterogeneous Behavioral Hierarchy for System Level Designs [p. 565]
*H. D. Patel, S. K. Shukla and R.A. Bergamaschi*- Design with Race-Free Hardware Semantics [p. 571]
*P. Schaumont, S. Shukla and I. Verbauwhede*

- Comfortable Modeling of Complex Reactive Systems [p. 577]
*S. Prochnow and R. von Hanxleden*- Faster Exploration of High Level Design Alternatives Using UML for Better Partitions [p. 579]
*W. Ahmed and D. Myers*

Moderator: G. Ascheid, RWTH Aachen U, DE

- A Design Flow for Configurable Embedded Processors Based on Optimized Instruction Set Extension Synthesis [p. 581]
*R. Leupers, K. Karuri, S. Kraemer and M. Pandey*- Energy Efficiency vs. Programmability Trade-off: Architectures and Design Principles [p. 587]
*J.P. Robelly, H. Seidel, K.C. Chen, and G. Fettweis*- Advanced Receiver Algorithms for MIMO Wireless Communication [p. 593]
*A. Burg, M. Borgmann, M. Wenk, C. Studer and H. Boelcskei*

- Next Generation Architectures Can Dramatically Reduce the 4G Deployment Cycle [p. 599]
*D. Shaver*

- Automatic ADL-Based Operand Isolation for Embedded Processors [p. 600]
*A. Chattopadhyay, B. Geukes, D. Kammler, E. M. Witte, O. Schliebusch, H. Ishebabi, R. Leupers, G. Ascheid and H. Meyr*- Power/Performance Hardware Optimization for Synchronization Intensive Applications in MPSoCs [p. 606]
*M. Monchiero, G. Palermo, C. Silvano and O. Villa*- An Analytical State Dependent Leakage Power Model for FPGAs [p. 612]
*A. Kumar and M. Anis*- Smart Bit-Width Allocation for Low Power Optimization in a SystemC Based ASIC Design Environment [p. 618]
*A. Mallik, D. Sinha, P. Banerjee and H. Zhou*

- Value-Based Bit Ordering for Energy Optimization of On-Chip Global Signal Buses [p. 624]
*K. Sundaresan and N. R. Mahapatra*

- Modeling Multiple Input Switching of CMOS Gates in DSM Technology Using HDMR [p. 626]
*J. Sridharan and T. Chen*- A Signal Theory Based Approach to the Statistical Analysis of Combinatorial Nanoelectronic Circuits [p. 632]
*O. Soffke, P. Zipf, T. Murgan and M. Glesner*- Using Conjugate Symmetries to Enhance Gate-Level Simulations [p. 638]
*P. M. Maurer*

- HDL Models of Ferromagnetic Core Hysteresis Using Timeless Discretisation of the Magnetic Slope [p. 644]
*H. Al-Junaid and T. Kazmierski*

- An RF Improved Loopback for Test Time Reduction [p. 646]
*M. Negreiros, L. Carro and A. A. Susin*- Test Scheduling with Thermal Optimization for Network-on-Chip Systems Using Variable-Rate On-Chip Clocking [p. 652]
*C. Liu and V. Iyengar*- Online RF Checkers for Diagnosing Multi-Gigahertz Automatic Test Boards on Low Cost ATE Platforms [p. 658]
*G. Srinivasan, F. Taenzler and A. Chatterjee*- Pseudorandom Functional BIST for Linear and Nonlinear MEMS [p. 664]
*A. Dhayni, S. Mir, L. Rufer and A. Bounceur*

- On-Chip 8GHz Non-Periodic High-Swing Noise Detector [p. 670]
*M. Abbas, M. Ikeda and K. Asada*

- Battery-Aware Code Partitioning for a Text to Speech System [p. 672]
*A. Lahiri, A. Basu, M. Choudhury and S. Mitra*- Performance Optimization for Energy-Aware Adaptive Checkpointing in Embedded Real-Time Systems [p. 678]
*Z. Li, H. Chen and S. Yu*- Software Annotations for Power Optimization on Mobile Devices [p. 684]
*R. Cornea, A. Nicolau and N. Dutt*- Dynamic Partitioning of Processing and Memory Resources in Embedded MPSoC Architectures [p. 690]
*L. Xue, O. Ozturk, F. Li, M. Kandemir and I. Kolcu*

- Activity Clustering for Leakage Management in SPMs [p. 696]
*M. Kandemir, G. Chen, F. Li, M. J. Irwin and I. Kolcu*- Adaptive Data Placement in an Embedded Multiprocessor Thread Library [p. 698]
*P. Stanley-Marbell, K. Lahiri and A. Raghunathan*

- COSMECA: Application Specific Co-Synthesis of Memory and Communication Architectures for MPSoC [p. 700]
*S. Pasricha and N. Dutt*- Synthesis of Fault-Tolerant Schedules with Transparency/Performance Trade-Offs for Distributed Embedded Systems [p. 706]
*V. Izosimov, P. Pop, P. Eles and Z. Peng*- Communication Architecture Optimization: Making the Shortest Path Shorter in Regular Networks-on-Chip [p. 712]
*U. Y. Ogras, R. Marculescu, H. G. Lee and N. Chang*- Buffer Space Optimisation with Communication Synthesis and Traffic Shaping for NoCs [p. 718]
*S. Manolache, P. Eles and Z. Peng*

- Cooptimization of Interface Hardware and Software for I/O Controllers [p. 724]
*K. J. Lin, S. H. Huang and S. C. Fang*

Moderator: L. Gaszi, Infineon, DE

- Cross Disciplinary Aspects (4G Wireless Special Day) [p. 726]
*Speakers: T. G. Noll and U. Lambrette*- SoC - Fuelling the Hopes of the Mobile Industry [p. 727]
*U. Lambrette*

- Integrated Data Relocation and Bus Reconfiguration for Adaptive System-on-Chip Platforms [p. 728]
*K. Sekar, K. Lahiri, A. Raghunathan and S. Dey*- FPGA Architecture Characterization for System Level Performance Analysis [p. 734]
*D. Densmore, A. Donlin and A. Sangiovanni-Vincentelli*- Dynamic Data Type Refinement Methodology for Systematic Performance-Energy Design Exploration of Network Applications [p. 740]
*A. Bartzas, S. Mamagkakis, G. Pouiklis, D. Atienza, F. Catthoor, D. Soudris and A. Thanailakis,*- Customization of Application Specific Heterogeneous Multi-Pipeline Processors [p. 746]
*S. Radhakrishnan, H. Guo and S. Parameswaran*

- Impact of Bit-Width Specification on the Memory Hierarchy for a Real-Time Video Processing System [p. 752]
*B. Thornberg and M. O'Nils*- Efficient Factorization of DSP Transforms Using Taylor Expansion Diagram [p. 754]
*J. Guillot, E. Boutillon, Q. Ren, M. Ciesielski, D. Gomez-Prado and S. Askar*

- Integrated Placement and Skew Optimization for Rotary Clocking [p. 756]
*G. Venkataraman, J. Hu, F. Liu and C.-N. Sze*- Associative Skew Clock Routing for Difficult Instances [p. 762]
*M.-S. Kim and J. Hu*- Efficient Timing-Driven Incremental Routing for VLSI Circuits Using DFs and Localized Slack-Satisfaction Computations [p. 768]
*S. Dutt, H. Arslan*

- Defect Tolerance of QCA Tiles [p. 774]
*J. Huang, M. Momenzadeh and F. Lombardi*- Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits [p. 780]
*B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam and K. Roy*- Novel Designs for Thermally Robust Coplanar Crossing in QCA [p. 786]
*S. Bhanja, M. Ottavi, F. Lombardi and S. Pontarelli*

- Designing MRF Based Error Correcting Circuits for Memory Elements [p. 792]
*K. Nepal, R. I. Bahar, J. Mundy, W. R. Patterson and A. Zaslavsky*

- A Time-Triggered Ethernet (TTE) Switch [p. 794]
*K. Steinhammer, P. Grillinger, A. Ademaj and H. Kopetz*- A Time Predictable Java Processor [p. 800]
*M. Schoeberl*- Optimizing the Generation of Object-Oriented Real-Time Embedded Applications Based on the Real-Time Specification for Java [p. 806]
*M. A. Wehrmeister, C. E. Pereira and L. B. Becker*

- Quantifier Structure in Search Based Procedures for QBFs [p. 812]
*E. Giunchiglia, M. Narizzano and A. Tacchella*- Strong Conflict Analysis for Propositional Satisfiability [p. 818]
*H. S. Jin and F. Somenzi*- Equivalence Verification of Arithmetic Datapaths with Multiple Word-Length Operands [p. 824]
*N. Shekhar, P Kalla and F. Enescu*

- 4G Applications, Architectures, Design Methodology and Tools for MPSoC [p. 830]

- Thermal Resilient Bounded-Skew Clock Tree Optimization Methodology [p. 832]
*A. Chakraborty, P. Sithambaram, K. Duraisami, A. Macii, E. Macii and M. Poncino,*- Exploring "Temperature-Aware" Design in Low-Power MPSoCs [p. 838]
*G. Paci, P. Marchal, F. Polett and L. Benini*- Adaptive Chip-Package Thermal Analysis for Synthesis and Design [p. 844]
*Y. Yang, Z. Gu, C. Zhu, L. Shang and R.P. Dick*- On-Chip Bus Thermal Analysis and Optimization [p. 850]
*F. Wang, Y. Xie, N. Vijaykrishnan and M. J. Irwin*

- Ultralow Power Computing with Sub-Threshold Leakage: A Comparative Study of Bulk and SOI Technologies [p. 856]
*A. Raychowdhury, B.C. Paul, S. Bhunia and K. Roy*- Low Power Synthesis of Dynamic Logic Circuits Using Fine-Grained Clock Gating [p. 862]
*N. Banerjee, K. Roy, H. Mahmoodi and S. Bhunia*- Enabling Fine-Grain Leakage Management by Voltage Anchor Insertion [p. 868]
*P. Babighian, L Benini, A. Macii and E. Macii*

- Automated Exploration of Pareto-Optimal Configurations in Parameterized Dynamic Memory Allocation for Embedded Systems [p. 874]
*S. Mamagkakis, D. Atienza, C. Poucet, F. Catthoor, D. Soudris and J. M. Mendias*- A Control Theoretic Approach to Run-Time Energy Optimization of Pipelined Processing in MPSoCs [p. 876]
*A. Alimonda, A. Acquaviva, S. Carta and A. Pisano*

- 3D Floorplanning with Thermal Vias [p. 878]
*E. Wong and S. K. Lim*- Timing-Driven Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization [p. 884]
*T. Iizuka, M. Ikeda and K. Asada*- Lens Aberration Aware Timing-Driven Placement [p. 890]
*A. B. Kahng, C.-H. Park, P. Sharma and Q. Wang*

- On Test Conditions for the Detection of Open Defects [p. 896]
*B. Kruseman and M. Heiligers*- A Compact Model to Identify Delay Faults Due to Crosstalk [p. 902]
*J. L. Rossello and J. Segura*- Generation of Broadside Transition Fault Test Sets That Detect Four-Way Bridging Faults [p. 907]
*I. Pomeranz and S. M. Reddy*- Extraction of Defect Density and Size Distributions from Wafer Sort Test Results [p. 913]
*J. E. Nelson, T. Zanon, R. Desineni, J. G. Brown, N. Patil, W. Maly and R. D. Blanton*

- An Interprocedural Code Optimization Technique for Network Processors Using Hardware Multi-Threading Support [p. 919]
*H. Scharwaechter, M. Hohenauer, R. Leupers, G. Ascheid and H. Meyr*- An Integrated Scratch-Pad Allocator for Affine and Non-Affine Code [p. 925]
*S. Udayakumaran and R. Barua*- Dynamic Scratch-Pad Memory Management for Irregular Array Access Patterns [p. 931]
*G. Chen, O. Ozturk, M. Kandemir and M. Karakoy*- Restructuring Field Layouts for Embedded Memory System [p. 937]
*K. Shin, J. Kim, S. Kim and H. Han*

- Power-Aware Compilation for Embedded Processors with Dynamic Voltage Scaling and Adaptive Body Biasing Capabilities [p. 943]
*P.-K. Huang and S. Ghiasi*- Dynamic Code Overlay of SDF-Modeled Programs on Low-End Embedded Systems [p. 945]
*H.-W. Park, K. Oh, S. Park, M.-M. Sim, and S. Ha*

- optiMap: A Tool for Automated Generation of NoC Architectures Using Multi-Port Routers for FPGAs [p. 947]
*B. Sethuraman and R. Vemuri*- Hardware Efficient Architectures for Eigenvalue Computation [p. 953]
*Y. Liu, C.-S. Bouganis, P. Y. K. Cheung, P. H. W. Leong and S. J. Motley*- Memory Centric Thread Synchronization on Platform FPGAs [p. 959]
*C. Kulkarni and G. Brebner*- A Parallel Configuration Model for Reducing the Run-Time Reconfiguration Overhead [p. 965]
*Y. Qu, J.-P. Soininen and J. Nurmi*

- Wireless Sensor Networks and Beyond [p. 970]
*P. J. M. Havinga*- The Ultra Low-Power WiseNET System [p. 971]
*A. El-Hoyidi, C. Arm, R. Caseiro, S. Cserveny, J.-D. Decotignie, C. Enz, F. Giroud, S. Gyger, E. Leroux, T. Melly, V. Peiris, F. Pengg, P.-D. Pfister, N. Raemy, A. Ribordy, D. Ruffieux and P. Volet*- Fast-prototyping Using the BTnode Platform [p. 977]
*J. Beutel*

- Circuit-Aware Device Design Methodology for Nanometer Technologies: A Case Study for Low Power SRAM Design [p. 983]
*Q. Chen, S. Mukhopadhyay, A. Bansal and K. Roy*- Architectural and Technology Influence on the Optimal Total Power Consumption [p. 989]
*C. Schuster, J.-L. Nagel, C. Piguet and P.-A. Farine*- Reducing the Sub-Threshold and Gate-Tunneling Leakage of SRAM Cells Using Dual-Vt and Dual-Tox Assignment [p. 995]
*B. Ameliard, F. Fallah and M. Pedram*- Exploiting Data-Dependent Slack Using Dynamic Multi-VDD to Minimize Energy Consumption in Datapath Circuits [p. 1001]
*K. R. Gandhi and N. R. Mahapatra*

- On the Evaluation of Transactor-Based Verification for Reusing TLM Assertions and Testbenches at RTL [p. 1007]
*N. Bombieri, F. Fummi and G. Pravadelli*- Functional Verification Methodology Based on Formal Interface Specification and Transactor Generation [p. 1013]
*F. Balarin and R. Passerone*- A Coverage Metric for the Validation of Interacting Processes [p. 1019]
*I. G. Harris*- New Methods and Coverage Metrics for Functional Verification [p. 1025]
*V. Jerinic, J. Langer, U. Heinkel and D. Mueller*

- Classification Trees for Random Tests and Functional Coverage [p. 1031]
*A. Krupp and W. Mueller*

- Efficient Test-Data Compression for IP Cores Using Multilevel Huffman Coding [p. 1033]
*X. Kavousianos, E. Kalligeros and D. Nikolos*- Functional Constraints vs. Test Compression in Scan-Based Delay Testing. [p. 1039]
*I. Polian and H. Fujiwara*- Concurrent Core Test for SoC Using Shared Test Set and Scan Chain Disable [p. 1045]
*G. Zeng and H. Ito*

- Efficient Unknown Blocking Using LFSR Reseeding [p. 1051]
*S. Wang, K. J. Balakrishnan and S. T. Chakradhar*- Coverage Loss by Using Space Compactors in Presence of Unknown Values [p. 1053]
*M. C.-T. Chao, S. Wang, S. T. Chakradhar, W. Wei and K.-T. Cheng*

- Online Energy-Aware I/O Device Scheduling for Hard Real-Time Systems [p. 1055]
*H. Cheng and S. Goddard*- Multiprocessor Synthesis for Periodic Hard Real-Time Tasks under a Given Energy Constraint [p. 1061]
*H.-.R Hsu, J.-J. Chen and T.-W. Kuo*- Scheduling under Resource Constraints Using Dis-Equations [p. 1067]
*H. Cherroun, A. Darte and P. Feautrier*- Scalable Performance-Energy Trade-Off Exploration of Embedded Real-Time Systems on Multiprocessor Platforms [p. 1073]
*Z. Ma and F. Catthoor*

- Building a Better Boolean Matcher and Symmetry Detector [p. 1079]
*D. Chai and A. Kuehlmann*- Optimizing Sequential Cycles through Shannon Decomposition and Retiming [p. 1085]
*C. Soviani, O. Tardieu and S. A. Edwards*- Efficient Incremental Clock Latency Scheduling for Large Circuits [p. 1091]
*C. Albrecht*- Analyzing Timing Uncertainty in Mesh-Based Clock Architectures [p. 1097]
*S. M. Reddy, G. R. Wilke and R. Murgai*

- Deploying Networks Based on TinyOS
*D. Culler*- Platform-Based Design of Wireless Sensor Networks for Industrial Applications [p. 1103]
*A. Bonivento, L. P. Carloni and A. Sangiovanni-Vincentelli*- An Environment for Controlled Experiments with In-House Sensor Networks [p. 1108]
*V. Handziski, A. Koepke, A. Willig and A. Wolisz*

- Hogthrob: Towards a Sensor Network Infrastructure for Sow Monitoring [p. 1109]
*P. Bonnet, M. Leopold and K. Madsen*

- Ultra Efficient (Embedded) SoC Architectures Based on Probabilistic CMOS (PCMOS) Technology [p. 1110]
*L. N. Chakrapani, B. E. S. Akgul, S. Cheemalavagu, P. Korkmaz, K. V. Palem and B. Seshasayee*- Minimizing Ohmic Loss and Supply Voltage Variation Using a Novel Distributed Power Supply Network [p. 1116]
*M. Budnik and K. Roy*- An Ultra Low-Power TLB Design [p. 1122]
*Y.-J. Chang*- Determining the Optimal Timeout Values for a Power-Managed System Based on the Theory of Markovian Processes: Offline and Online Algorithms [p. 1128]
*P. Rong and M. Pedram*

- A Formal Model and Efficient Traversal Algorithm for Generating Testbenches for Verification of IEEE Standard Floating Point Division [p. 1134]
*D. W. Matula and L. D. McFearin*- On the Relation between Simulation-Based and SAT-Based Diagnosis [p. 1139]
*G. Fey, S. Safarpour, A. Veneris and R. Drechsler*- An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration [p. 1145]
*F. Angiolini, J. Ceng, R. Leupers, F. Ferrari, C. Ferri and, L. Benini*- Parallel Co-Simulation Using Virtual Synchronization with Redundant Host Execution [p. 1151]
*D. Kim, S. Ha and R. Gupta*

- An Efficient and Portable Scheduler for RTOS Simulation and its Certified Integration to SystemC [p. 1157]
*H. Nakamura, N. Sato and N. Tabuchi*

- Minimizing Test Power in SRAM through Reduction of Pre-Charge Activity [p. 1159]
*L. Dilillo, P. Rosinger, B. M. Al-Hashimi and P. Girard*- Efficient On-Line Interconnect Testing in FPGAs with Provable Detectability for Multiple Faults [p. 1165]
*V. Suthar and S. Dutt*- A Concurrent Testing Method for NoC Switches [p. 1171]
*M. Hosseinabady, A. Banaiyan, M. N. Bojnordi and Z. Navabi*

- A Secure Scan Design Methodology [p. 1177]
*D. Hély, F. Bancel, M.-L. Flottes and B. Rouzeyre*

- RAS-NANO: A Reliability-Aware Synthesis Framework for Reconfigurable Nanofabrics [p. 1179]
*C. He and M. F. Jacome*- Layout Driven Data Communication Optimization for High Level Synthesis [p. 1185]
*R. Kastner, W. Gong, X. Hao, F. Brewer, A. Kaplan, P. Brisk and M. Sarrafzadeh*- Physical-Aware Simulated Annealing Optimization of Gate Leakage in Nanoscale Datapath Circuits [p. 1191]
*S. P. Mohanty, R. Velagapudi and E. Kougianos*- Automatic Generation of Operation Tables for Fast Exploration of Bypasses in Embedded Processors [p. 1197]
*S. Park, A. Shrivastava, N. Dutt, E. Earlie, A. Nicolau and Y. Paek*

- High Level Synthesis of Higher Order Continuous Time State Variable Filters with Minimum Sensitivity and Hardware Count [p. 1203]
*S. Pandit, S. Kar, C. Mandal and A. Patra*

- Disjunctive Image Computation for Embedded Software Verification [p. 1205]
*C. Wang, Z. Yang, F. Ivancic and A. Gupta*- Distance-Guided Hybrid Verification with GUIDO [p. 1211]
*S. Shyam and V. Bertacco*- What Lies between Design Intent Coverage and Model Checking? [p. 1217]
*S. Das, P. Basu, P. Dasgupta and P. P. Chakrabarti*

- On the Numerical Verification of Probabilistic Rewriting Systems [p. 1223]
*J. Ben Hassen and S. Tahar*- Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks [p. 1225]
*G. Fey, D. Grosse and R. Drechsler*

Panel Moderator: G. De Micheli, EPFL Lausanne, CH

- Low-Power Design Tools: Are EDA Vendors Taking this Matter Seriously? [p. 1227]
*E. Macii, M. Pedram, D. Friebel, R. Aitken, A. Domic and R. Zafalon*

Panel Moderator: G. De Micheli, EPFL Lausanne, CH

- Low-Power Design Tools: Are EDA Vendors Taking this Matter Seriously? [p. 1227]
*E. Macii, M. Pedram, D. Friebel, R. Aitken, A. Domic and R. Zafalon*

- Formal Verification of SystemC Designs Using a Petri-Net Based Representation [p. 1228]
*D. Karlsson, P. Eles and Z. Peng*- Monolithic Verification of Deep Pipelines with Collapsed Flushing [p. 1234]
*R. Kane, P. Manolios and S. K. Srinivasan*- Functional Test Generation Using Property Decompositions for Validation of Pipelined Processors [p. 1240]
*H.-M. Koo and P. Mishra*- Proven Correct Monitors from PSL Specifications [p. 1246]
*K. Morin-Allory and D. Borrione*

- Space of DRAM Fault Models and Corresponding Testing [p. 1252]
*Z. Al-Ars, S. Hamdioui and A. J. van de Goor*- Automatic March Tests Generations for Static Linked Faults in SRAMs [p. 1258]
*A. Benso, A. Bosio, S. Di Carlo, G. Di Natale and P. Prinetto*- Test Compaction for Transition Faults under Transparent-Scan [p. 1264]
*I. Pomeranz and S. M. Reddy*- Test Set Enrichment Using a Probabilistic Fault Model and the Theory of Output Deviations [p. 1270]
*Z. Wang, K. Chakrabarty and M. Goessel*

- Vulnerability Analysis of L2 Cache Elements to Single Event Upsets [p. 1276]
*H. Asadi, V. Sridharan, M. B. Tahoori and D. Kaeli*- Area-Efficient Error Protection for Caches [p. 1282]
*S. Kim*- Microarchitectural Floorplanning under Performance and Thermal Tradeoff [p. 1288]
*M. Healy, M. Vittes, M. Ekpanyapong, C. Ballapuram, S. K. Lim, H.-H. S. Lee and G. H. Loh*

- Optimizing High Speed Arithmetic Circuits Using Three-Term Extraction [p. 1294]
*A. Hosangadi, F. Fallah and R. Kastner*- Efficient Minimization of Fully Testable 2-SPP Networks [p. 1300]
*A. Bernasconi, V. Ciriani, R. Drechsler and T. Villa*- Pre-Synthesis Optimization of Multiplications to Improve Circuit Performance [p. 1306]
*R. Ruiz-Sautua, M. C. Molina, J. M. Mendias and R. Hermida*- Crosstalk-Aware Domino Logic Synthesis [p. 1312]
*Y.-Y. Liu and T. T. Hwang*

- TRAIN: A Virtual Transaction Layer Architecture for TLM-Based HW/SW Codesign of Synthesizable MPSoC [p. 1318]
*W. Klingauf, H. Gaedke, R. Guenzel*- Configurable Multiprocessor Platform with RTOS for Distributed Execution of UML 2.0 Designed Applications [p. 1324]
*T. Arpinen, P. Kukkala, E. Salminen, M. Hännikäinen and T. D. Hämäläinen*- ASIP-Based Multiprocessor SoC Design for Simple and Double Binary Turbo Decoding [p. 1330]
*O. Muller, A. Baghdadi and M. Jézéquel*