Sessions: [Keynote Address] [2.2] [2.3] [2.4] [2.5] [2.6] [2.7] [2.8] [3.2] [3.3] [3.4] [3.5] [3.6] [3.7] [3.8] [IP1] [4.2] [4.3] [4.4] [4.5] [4.6] [4.7] [5.1] [5.2] [5.3] [5.4] [5.5] [5.6] [5.7] [IP2] [6.1.1] [6.1.2] [6.2] [6.3] [6.4] [6.5] [6.6] [6.7] [6.8] [7.1] [7.2] [7.3] [7.4] [7.5] [7.6] [7.7] [7.8] [IP3] [8.1] [8.2] [8.3] [8.4] [8.5] [8.6] [8.7] [8.8] [9.1] [9.2] [9.3] [9.4] [9.5] [9.6] [9.7] [IP4] [10.1.1] [10.1.2] [10.2] [10.3] [10.4] [10.5] [10.6] [10.7] [10.8] [11.1] [11.2] [11.3] [11.4] [11.5] [11.6] [11.7] [11.8] [IP5] [12.1] [12.2] [12.3] [12.4] [12.5] [12.6] [12.7] [12.8]

DATE Executive Committee
DATE Sponsors
Technical Program Topic Chairs
Technical Program Committee
Best Paper Awards
PH.D. Forum
Call for Papers: DATE 2012

Keynote Address

PDF icon Biologically-Inspired Massively-Parallel Architectures - Computing Beyond A Million Processors [p. 1]
S. Furber

2.2: System-Level Techniques to Handle Performance, Reliability and Thermal Issues

Moderators: D. Goswami, TU Munich, DE; T. Stefanov, Leiden U, NL
PDF icon VESPA: Variability Emulation for System-on-Chip Performance Analysis [p. 2]
V. Kozhikkottu, R. Venkatesan, A. Raghunathan and S. Dey

PDF icon Thermal-Aware On-Line Task Allocation for 3D Multi-Core Processor Throughput Optimization [p. 8]
C.-L. Lung, Y.-L. Ho, D.-M. Kwai and S.-C. Chang

PDF icon An Endurance-Enhanced Flash Translation Layer via Reuse for NAND Flash Memory Storage Systems [p. 14]
Y. Wang, D. Liu, Z. Qin and Z. Shao

PDF icon Register Allocation for Simultaneous Reduction of Energy and Peak Temperature on Registers [p. 20]
T. Liu, A. Orailoglu, C.J. Xue and M. Li

2.3: Modeling and Simulation of Interconnects

Moderators: W. Schilders, TU Eindhoven, NL; S. Grivet-Talocia, Politecnico di Torino, IT
PDF icon A Parallel Hamiltonian Eigensolver for Passivity Characterization and Enforcement of Large Interconnect Macromodels [p. 26]
L. Gobbato, A. Chinea and S. Grivet-Talocia

PDF icon Fast Statistical Analysis of RC Nets Subject to Manufacturing Variabilities [p. 32]
Y. Bi, K.-J. van der Kolk, J. Fernández Villena, L.M. Silveira and N. van der Meijs

PDF icon A Scaled Random Walk Solver for Fast Power Grid Analysis [p. 38]
B. Boghrati and S. Sapatnekar

PDF icon A Block-Diagonal Structured Model Reduction Scheme for Power Grid Networks [p. 44]
Z. Zhang, X. Hu, C.-K. Cheng and N. Wong

2.4: PANEL AND EMBEDDED TUTORIAL SESSION - Logic Synthesis and Place and Route: After 20 Years of Engagement, Wedding in View? [p. 50]

Moderator: A Domic, Synopsys, US

Panelists: G. De Micheli, P. Groeneveld, H. Hiller, E. Macii, P. Magarshack

PDF icon Logic synthesis and Physical Design: Quo Vadis [p. 51]
G. De Micheli

2.5: Transient Faults and Soft Errors

Moderators: D. Appello, STMicroelectronics, IT; C. Metra, Bologna U, IT
PDF icon Time Redundant Parity for Low-Cost Transient Error Detection [p. 52]
D.J. Palframan, N.S. Kim and M.H. Lipasti

PDF icon Cross-Layer Optimized Placement and Routing for FPGA Soft Error Mitigation [p. 58]
K. Huang, Y. Hu and X. Li

PDF icon Trigonometric Method to Handle Realistic Error Probabilities in Logic Circuits [p. 64]
C.-C. Yu and J.P. Hayes

PDF icon Soft Error Rate Estimation of Digital Circuits in the Presence of Multiple Event Transients (METs) [p. 70]
M. Fazeli, S.N. Ahmadian, S.G. Miremadi, H. Asadi, M.B. Tahoori

2.6: Networked Embedded Systems

Moderators: L. Almeida, Porto U, PT; P. Puschner, TU Vienna, AT
PDF icon FlexRay Switch Scheduling - A Networking Concept for Electric Vehicles [p. 76]
M. Lukasiewycz, S. Chakraborty and P. Milbredt

PDF icon A Reconfiguration Approach for Fault-Tolerant FlexRay Networks [p. 82]
K. Klobedanz, A. Koenig and W. Mueller

PDF icon Simplified Programming of Faulty Sensor Networks via Code Transformation and Run-Time Interval Computation [p. 88]
L.S. Bai, R.P. Dick, P.A. Dinda and P.H. Chou

2.7: Design of Energy-Efficient and Automotive Systems

Moderators: K. Danne, Intel; M. Di Natale, Scuola S S Anna, IT
PDF icon Parallel Accelerators for GlimmerHMM Bioinformatics Algorithm [p. 94]
N. Chrysanthou, G. Chrysos, E. Sotiriades and I. Papaefstathiou

PDF icon An Efficient On-Line Task Allocation Algorithm for QoS and Energy Efficiency in Multicore Multimedia Platforms [p. 100]
F. Paterna, A. Acquaviva, A. Caprara, F. Papariello, G. Desoli and L. Benini

PDF icon Sub-Clock Power-Gating Technique for Minimising Leakage Power During Active Mode [p. 106]
J.N. Mistry, B.M. Al-Hashimi, D. Flynn and S. Hill

PDF icon An Automated Data Structure Migration Concept - From CAN to Ethernet/IP in Automotive Embedded Systems (CANoverIP) [p. 112]
A. Kern, T. Streichert and J. Teich

PDF icon Formal Specification and Systematic Model-Driven Testing of Embedded Automotive Systems [p. 118]
S. Siegl, K.-S. Hielscher, R. German and C. Berger

2.8: EMBEDDED TUTORIAL - Addressing Critical Power Management Verification Issues in Low Power Designs p. 124]

Moderator: K. Just, Infineon, DE

PDF icon

3.2: Power Optimization of Multi-Core Architectures

Moderators: C. Piguet, CSEM, CH; M. Lopez-Vallejo,, UP Madrid, ES
PDF icon Topologically Homogeneous Power-Performance Heterogeneous Multicore Systems [p. 125]
K. Chakraborty and S. Roy

PDF icon Variability-Aware Duty Cycle Scheduling in Long Running Embedded Sensing Systems [p. 131]
L. Wanner, R. Balani, S. Zahedi, C. Apte, P. Gupta and M. Srivastava

PDF icon Reliability-aware Thermal Management for Hard Real-time Applications on Multi-core Processors [p. 137]
V. Hanumaiah and S. Vrudhula

3.3: Core Algorithms for Formal Verification Engines

Moderators: S. Quer, Politecnico di Torino, IT; S. Seshia, UC Berkeley, US
PDF icon Clause Simplification through Dominator Analysis [p. 143]
H. Han, H. Jin and F. Somenzi

PDF icon Integration of Orthogonal QBF Solving Techniques [p. 149]
S. Reimer, F. Pigorsch, C. Scholl and B. Becker

PDF icon STABLE: A New QF-BV SMT Solver for Hard Verification Problems combining Boolean Reasoning with Computer Algebra [p. 155]
E. Pavlenko, M. Wedler, D. Stoffel, W. Kunz, A. Dreyer, F. Seelisch and G.-M. Greuel

3.4: Predicting Bugs and Generating Tests for Validation

Moderators: D. Grosse, Bremen U, DE; V. Bertacco, U of Michigan, US
PDF icon Empirical Design Bugs Prediction for Verification [p. 161]
Q. Guo, T. Chen, H. Shen, Y. Chen, Y. Wu and W. Hu

PDF icon Decision Ordering Based Property Decomposition for Functional Test Generation [p. 167]
M. Chen and P. Mishra

PDF icon Towards Coverage Closure: Using Goldmine Assertions for Generating Design Validation Stimulus [p. 173]
L. Liu, D. Sheridan, W. Tuohy and S. Vasudevan

PDF icon Scalable Hybrid Verification for Embedded Software [p. 179]
J. Behrend, D. Lettnin, P. Heckeler, J. Ruf, T. Kropf and W. Rosenstiel

3.5: Timing Related Issues in Test

Moderators: H.-J. Wunderlich, Stuttgart U, DE; S.K. Goel, TSMC, US
PDF icon Diagnosing Scan Chain Timing Faults through Statistical Feature Analysis of Scan Images [p. 185]
M. Chen and A. Orailoglu

PDF icon Design-for-Test Methodology for Non-Scan At-Speed Testing [p. 191]
M. Banga, N. Rahagude and M.S. Hsiao

PDF icon A Clock-Gating Based Capture Power Droop Reduction Methodology for At-Speed Scan Testing [p. 197]
B. Yang, A. Sanghani, S. Sarangi and C. Liu

3.6: Performance and Timing Analysis

Moderators: H. Falk, TU Dortmund, DE; R. Wilhelm, Saarland U, DE
PDF icon Pruning Infeasible Paths for Tight WCRT Analysis of Synchronous Programs [p. 204]
S. Andalam, P.S. Roop and A. Girault

PDF icon Fast and Accurate Resource Conflict Simulation for Performance Analysis of Multi-Core Systems [p. 210]
S. Stattelmann, O. Bringmann and W. Rosenstiel

PDF icon An Approach to Improve Accuracy of Source-Level TLMs of Embedded Software [p. 216]
Z. Wang, K. Lu and A. Herkersdorf

PDF icon Host-Compiled Multicore RTOS Simulator for Embedded Real-Time Software Development [p. 222]
P. Razaghi and A. Gerstlauer

3.7: Implementations for Digital Baseband Processing

Moderators: F. Kienle, TU Kaiserslautern, DE; F. Clermidy, CEA-LETI, FR
PDF icon A Flexible High Throughput Multi-ASIP Architecture for LDPC and Turbo Decoding [p. 228]
P. Murugappa, R. Al-Khayat, A. Baghdadi and M. Jezequel

PDF icon A Low-Power VLIW Processor for 3GPP-LTE Complex Numbers Processing [p. 234]
C. Bernard and F. Clermidy

PDF icon Architecture and FPGA-Implementation of a High Throughput K+-Best Detector [p. 240]
N. Heidmann, T. Wiegand and S. Paul

PDF icon An Energy-Efficient 64-QAM MIMO Detector for Emerging Wireless Standards [p. 246]
N. Moezzi-Madani, T. Thorolfsson, J. Crop, P. Chiang and W.R. Davis

3.8: PANEL SESSION - Power Formats: Beyond UPF and CPF

Moderator: B. Pangrle, Mentor Graphics, US

PDF icon Beyond UPF & CPF: Low-Power Design and Verification [p. 252]
B. Pangrle

Panelists: J. Biggs, C. Clavel, O. Domerego, K. Just

IP1: Interactive Presentations

PDF icon Buffering Implications for the Design Space of Streaming MEMS Storage [p. 253]
M.G. Khatib and L. Abelmann

PDF icon Efficient RC Power Grid Verification Using Node Elimination [p. 257]
A. Goyal and F.N. Najm

PDF icon A Novel TSV Topology for Many-Tier 3D Power-Delivery Networks [p. 261]
M.B. Healy and S.K. Lim

PDF icon Cost-Efficient Fault-Tolerant Decoder for Hybrid Nanoelectronic Memories [p. 265]
N.Z. Haron and S. Hamdioui

PDF icon DynOAA - Dynamic Offset Adaptation Algorithm for Improving Response Times of CAN Systems [p. 269]
T. Ziermann, J. Teich and Z. Salcic

PDF icon A Sensor Fusion Algorithm for an Integrated Angular Position Estimation with Inertial Measurement Units [p. 273]
S. Sabatelli, F. Sechi, L. Fanucci and A. Rocchi

PDF icon Speeding-up SIMD Instructions Dynamic Binary Translation in Embedded Processor Simulation [p. 277]
L. Michel, N. Fournel and F. Pétrot

PDF icon System-Level Energy-Efficient Scheduling for Hard Real-Time Embedded Systems [p. 281]
L. Niu

PDF icon Timing Error Statistics for Energy-Efficient Robust DSP Systems [p. 285]
R.A. Abdallah, Y.-H. Lee and N.R. Shanbhag

PDF icon ScTMR: A Scan Chain-Based Error Recovery Technique for TMR Systems in Safety-Critical Applications [p. 289]
M. Ebrahimi, S.G. Miremadi and H. Asadi

4.2: Robust and Low Power Systems

Moderators: C. Silvano, Politecnico di Milano, IT; M. Berekovic, TU Braunschweig, DE
PDF icon Enabling Improved Power Management in Multicore Processors through Clustered DVFS [p. 293]
T. Kolpe, A. Zhai and S.S. Sapatnekar

PDF icon Dynamic Thermal Management in 3D Multi-Core Architecture through Run-Time Adaptation [p. 299]
F. Hameed, M.A. Al Faruque and J. Henkel

PDF icon Distributed Hardware Matcher Framework for SoC Survivability [p. 305]
I. Wagner and S.-L. Lu

PDF icon A Cost-Effective Substantial-Impact-Filter Based Method to Tolerate Voltage Emergencies [p. 311]
S. Pan, Y. Hu, X. Hu and X. Li

4.3: Formal Verification Techniques and Applications

Moderators: M. Wedler, Kaiserslautern U, DE; C. Scholl, Freiburg U, DE
PDF icon Interpolation Sequences Revisited [p. 317]
G. Cabodi, S. Nocco and S. Quer

PDF icon Automated Debugging of SystemVerilog Assertions [p. 323]
B. Keng, S. Safarpour and A. Veneris

PDF icon Counterexample-Guided SMT-Driven Optimal Buffer Sizing [p. 329]
B.A. Brady, D. Holcomb and S.A. Seshia

4.4: System Level Simulation and Validation

Moderators: F. Fummi, Verona U, IT; P. Sanchez, Cantabria U, ES
PDF icon DOM: A Data-Dependency-Oriented Modeling Approach for Efficient Simulation of OS Preemptive Scheduling [p. 335]
P.-C. Wang, M.-H. Wu and R.-S. Tsay

PDF icon Cycle-Count-Accurate Processor Modeling for Fast and Accurate System-Level Simulation [p. 341]
C.-K. Lo, L.-C. Chen, M.-H. Wu and R.-S. Tsay

PDF icon A Shared-Variable-Based Synchronization Approach to Efficient Cache Coherence Simulation for Multi-Core Systems [p. 347]
C.-Y. Fu, M.-H. Wu and R.-S. Tsay

PDF icon Speeding up MPSoC Virtual Platform Simulation by Ultra Synchronization Checking Method [p. 353]
Y.-F. Yeh, C.-Y. Huang, C.-A. Wu and H.-C. Lin

4.5: Advances in Analogue, Mixed Signal and RF Testing

Moderators: A. Richardson, Lancaster U, UK; H. Stratigopoulos, IMAG, FR
PDF icon An All-Digital Built-In Self-Test Technique for Transfer Function Characterization of RF PLLs [p. 359]
P.-Y. Wang, H.-M. Chang and K.-T. Cheng

PDF icon A True Power Detector for RF PA Built-In Calibration and Testing [p. 365]
J. Machado da Silva and P. Fonseca da Mota

PDF icon Test Time Reduction in Analogue/Mixed-Signal Devices by Defect Oriented Testing: An Industrial Example [p. 371]
H. Hashempour, J. Dohmen, B. Tasic, B. Kruseman, C. Hora, M. van Beurden and Y. Xing

PDF icon Testing of High-Speed DACs Using PRBS Generation with "Alternate-Bit-Tapping" [p. 377]
M. Singh, M. Sakare and S. Gupta

4.6: Design Automation Methodologies and Architectures for Three-Dimensional ICs

Moderators: Y. Xie, Penn State U, US; H. Li, New York U, US
PDF icon Statistical Thermal Evaluation and Mitigation Techniques for 3D Chip-Multiprocessors in the Presence of Process Variations [p. 383]
D.-C. Juan, S. Garg and D. Marculescu

PDF icon Design Space Exploration for 3D-Stacked DRAMs [p. 389]
C. Weis, N. Wehn, I. Loi and L. Benini

PDF icon Analytical Heat Transfer Model for Thermal Through-Silicon Vias [p. 395]
H. Xu, V.F. Pavlidis and G. De Micheli

PDF icon A New Architecture for Power Network in 3D IC [p. 401]
H.-T. Chen, H.-L. Lin, Z.-C. Wang and T.T. Hwang

4.7: Resource Management for QoS Guaranteed NoCs

Moderators: A. Hansson, Twente U, NL; F. Petrot, TIMA Laboratory, FR
PDF icon Achieving Composability in NoC-Based MPSoCs Through QoS Management at Software Level [p. 407]
E. Carara, G.M. Almeida, G. Sassateli and F.G. Moraes

PDF icon Supporting Non-Contiguous Processor Allocation in Mesh-Based CMPs Using Virtual Point-to-Point Links [p. 413]
M. Asadinia, M. Modarressi, A. Tavakkol and H. Sarbazi-Azad

PDF icon Guaranteed Service Virtual Channel Allocation in NoCs for Run-Time Task Scheduling [p. 419]
M. Winter and G.P. Fettweis

PDF icon An FPGA Bridge Preserving Traffic Quality of Service for On-Chip Network-Based Systems [p. 425]
A. Beyranvand Nejad, M. Escudero Martinez and K. Goossens

5.1: SMART DEVICES EMBEDDED TUTORIAL - Smart Devices for the Cloud Era

Moderators: A. Jerraya, CEA-LETI MINATEC, FR; J. Goodacre, ARM, UK
PDF icon Entering the Path towards Terabit/s Wireless Links [p. 431]
G. Fettweis, F. Guderian and S. Krone

PDF icon Smart Imagers of the Future [p. 437]
A. Dupret, M. Tchagaspanian, A. Verdant, L. Alacoque and A. Peizerat

5.2: An Encyclopedia of Routing

Moderators: D. Stroobandt, Ghent U, BE; I. Markov, U of Michigan, US
PDF icon Power-Driven Global Routing for Multi-Supply Voltage Domains [p. 443]
T.-H. Wu, A. Davoodi and J.T. Linderoth

PDF icon Obstacle-Aware Multiple-Source Rectilinear Steiner Tree with Electromigration and IR-Drop Avoidance [p. 449]
J.-T. Yan and Z.-W. Chen

PDF icon Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing [p. 455]
J. Lu, V. Honkote, X. Chen and B. Taskin

PDF icon On Routing Fixed Escaped Boundary Pins for High Speed Boards [p. 461]
T.-Y. Tsai, R.-J. Lee, C.-Y. Chin, C.-Y. Kuan, H.-M. Chen and Y. Kajitani

5.3: Temperature and Variation Aware Design in Low Power Systems

Moderators: D. Helms, OFFIS, DE; N. Chang, Seoul National U, KR
PDF icon Dynamic Write Limited Minimum Operating Voltage for Nanoscale SRAMs [p. 467]
S. Nalam, V. Chandra, R.C. Aitken and B.H. Calhoun

PDF icon Variation Aware Dynamic Power Management for Chip Multiprocessor Architectures [p. 473]
M. Ghasemazar and M. Pedram

PDF icon Leakage Aware Energy Minimization for Real-Time Systems under the Maximum Temperature Constraint [p. 479]
H. Huang and G. Quan

5.4: Advanced NoC Tooling and Architectures

Moderators: A. Jantsch, KTH, SE; S Yoo, Pohang U of Science and Technology, KR
PDF icon Multi-Objective Tabu Search Based Topology Generation Technique for Application-Specific Network-on-Chip Architectures [p. 485]
A. Tino and G.N. Khan

PDF icon A Fully-Synthesizable Single-Cycle Interconnection Network for Shared-L1 Processor Clusters [p. 491]
A. Rahimi, I. Loi, M.R. Kakoee and L. Benini

PDF icon Run-Time Deadlock Detection in Networks-on-Chip Using Coupled Transitive Closure Networks [p. 497]
R. Al-Dujaily, T. Mak, F. Xia, A. Yakovlev and M. Palesi


Moderators: E.J. Marinissen, IMEC, BE; W. Nebel, OFFIS, DE
PDF icon Developing an Integrated Verification and Debug Methodology [p. 503]
A. Matsuda and T. Ishihara

PDF icon An Analytical Compact Model for Estimation of Stress in Multiple Through-Silicon Via Configurations [p. 505]
G. Eneman, J. Cho, V. Moroz, D. Milojevic, M. Choi, K. De Meyer, A. Mercha, E. Beyne, T. Hoffmann and G. Van der Plas

PDF icon Power Management Verification Experiences in Wireless SoCs [p. 507]
B. Kapoor, A. Hunter, and P. Tiwari

PDF icon Challenges in Designing High Speed Memory Subsystem for Mobile Applications [p. 509]
T.G. Yip, P. Yeung, M. Li and D. Dressler

PDF icon Solid State Photodetectors for Nuclear Medical Imaging Applications [p. 511]
M. Mazzillo, P.G. Fallica, E. Ficarra, A. Messina, M. Romeo and R. Zafalon

PDF icon Fault Grading of Software-Based Self-Test Procedures for Dependable Automotive Applications [p. 513]
P. Bernardi, M. Grosso, E. Sanchez and O. Ballan

5.6: Analysis, Compilation and Runtime Techniques

Moderators: H. Falk, TU Dortmund, DE; H. van Someren, ACE Associated Compiler Experts, NL
PDF icon CARAT: Context-Aware Runtime Adaptive Task Migration for Multi Core Architectures [p. 515]
J. Jahn, M.A. Al Faruque and J. Henkel

PDF icon A Rule-Based Static Dataflow Clustering Algorithm for Efficient Embedded Software Synthesis [p. 521]
J. Falk, C. Zebelein, C. Haubelt and J. Teich

PDF icon Demand Code Paging for NAND Flash in MMU-less Embedded Systems [p. 527]
J.A. Baiocchi and B.R. Childers

5.7: EMBEDDED TUTORIAL - Architectures for Online Error Detection and Recovery in Multicore Processors

Moderator: X. Vera, Intel Corporation, ES
PDF icon Architectures for Online Error Detection and Recovery in Multicore Processors [p. 533]
D. Gizopoulos, M. Psarakis, S.V. Adve, P. Ramachandran, S.K.S. Hari, D. Sorin, A. Meixner, A. Biswas and X. Vera

IP2: Interactive Presentations

PDF icon An Energy-Efficient 3D CMP Design with Fine-Grained Voltage Scaling [p. 539]
J. Zhao, X. Dong and Y. Xie

PDF icon Optimized Model Checking of Multiple Properties [p. 543]
G. Cabodi and S. Nocco

PDF icon A New Distributed Event-Driven Gate-Level HDL Simulation by Accurate Prediction [p. 547]
D. Kim, M. Ciesielski and S. Yang

PDF icon Circuit and DFT Techniques for Robust and Low Cost Qualification of a Mixed-Signal SoC with Integrated Power Management System [p. 551]
L. Balasubramanian, P. Sabbarwal, R.K. Mittal, P. Narayanan, R.K. Dash, A.D. Kudari, S. Manian, S. Polarouthu, H. Parthasarathy, R.C. Vijayaraghavan, S. Turkewadikar

PDF icon A 3D Reconfigurable Platform for 4G Telecom Applications [p. 555]
W. Lafi, D. Lattard and A. Jerraya

PDF icon An LOCV-Based Static Timing Analysis Considering Spatial Correlations of Power Supply Variations [p. 559]
S. Kobayashi and K. Horiuchi

PDF icon Compiling SyncCharts to Synchronous C [p. 563]
C. Traulsen, T. Amende and R. von Hanxleden

PDF icon Optimization of Stateful Hardware Acceleration in Hybrid Architectures [p. 567]
X. Chang, Y. Ma, H. Franke, K. Wang, R. Hou, H. Yu and T. Nelms

PDF icon Formal Reset Recovery Slack Calculation at the Register Transfer Level [p. 571]
C.-N. Chung, C.-W. Chang, K.-H. Chang and S.-Y. Kuo

PDF icon Multi-Granularity Thermal Evaluation of 3D MPSoC Architectures [p. 575]
A. Fourmigue, G. Beltrame, G. Nicolescu, E.M. Aboulhamid and I. O. Connor

PDF icon Two Methods for 24 Gbps Test Signal Synthesis [p. 579]
D.C. Keezer and C.E. Gray

PDF icon 3D-ICML: A 3D Bipolar ReRAM Design with Interleaved Complementary Memory Layers [p. 583]
Y.-C. Chen, H. Li, Y. Chen and R.E. Pino

PDF icon Architectural Exploration of 3D FPGAs towards a Better Balance between Area and Delay [p. 587]
C.-I. Chen, B.-C. Lee and J.-D. Huang

PDF icon NoC-MPU: A Secure Architecture for Flexible Co-Hosting on Shared Memory MPSoCs [p. 591]
J. Porquet, A. Grenier and C. Schwarz


Moderators: J. Goodacre, ARM, UK; A. Jerraya, CEA-LETI MINATEC, FR
PDF icon Low Power Smart Industrial Control [p. 595]
A. Bilgic, V. Pichot, M. Gerding and F. Bruns

PDF icon Low Power Interconnects for SIMD Computers [p. 600]
M. Woh, S. Satpathy, R.G. Dreslinski, D. Kershaw, D. Sylvester, D. Blaauw and T. Mudge


Moderator: A. Jerraya, CEA-LETI MINATEC, FR
PDF icon Wireless Innovations for Smartphones [p. 606]
H. Kauppinen

6.2: Placement and Floorplanning

Moderators: R. Otten, TU Eindhoven, NL; A. Davoodi, Wisconsin U, US
PDF icon Flow-based Partitioning and Position Constraints in VLSI Placement [p. 607]
M. Struzyna

PDF icon Integrated Circuit White Space Redistribution for Temperature Optimization [p. 613]
Y. Chen, H. Zhou and R.P. Dick

PDF icon Timing-Constrained I/O Buffer Placement for Flip-Chip Designs [p. 619]
Z.-W. Chen and J.-T. Yan

PDF icon Floorplanning Exploration and Performance Evaluation of a New Network-on-Chip [p. 625]
L. Xue, W. Ji, Q. Zuo and Y. Zhang

6.3: Power Modeling, Analysis and Optimization

Moderators: J. Henkel, Karlsruhe Institute of Technology, DE; M. Poncino, Politecnico di Torino, IT
PDF icon Worst-Case Temperature Analysis for Real-Time Systems [p. 631]
D. Rai, H. Yang, I. Bacivarov, J.-J. Chen and L. Thiele

PDF icon Black-Box Leakage Power Modeling for Cell Library and SRAM Compiler [p. 637]
C.-K. Tseng, S.-Y. Huang, C.-C. Weng, S.-C. Fang and J.-J. Chen

PDF icon Clock Gating Optimization with Delay-Matching [p. 643]
S.-J. Hsu and R.-B. Lin

PDF icon A Low Complexity Stopping Criterion for Reducing Power Consumption in Turbo Decoders [p. 649]
P. Reddy, F. Clermidy, A. Baghdadi and M. Jezequel

PDF icon A Novel Tag Access Scheme for Low Power L2 Cache [p. 655]
H. Park, S. Yoo and S. Lee

6.4: Design and Test of Fault Resilient NoC Architectures

Moderators: M. Coppola, ST Microelectronics, FR; K. Goossens, TU Eindhoven, NL
PDF icon Exploiting Network-on-Chip Structural Redundancy for a Cooperative and Scalable Built-In Self-Test Architecture [p. 661]
A. Strano, C. Gomez, D. Ludovici, M. Favalli, M.E. Gomez and D. Bertozzi

PDF icon ReliNoC: A Reliable Network for Priority-Based On-Chip Communication [p. 667]
M.R. Kakoee, V. Bertacco and L. Benini

PDF icon FARM: Fault-Aware Resource Management in NoC-Based Multiprocessor Platforms [p. 673]
C.-L. Chou and R. Marculescu

6.5: New Techniques for Diagnosis and Debug

Moderators: S. Reddy, Iowa U, US; B. Vermeulen, NXP Semiconductors, NL
PDF icon On Diagnosis of Multiple Faults Using Compressed Responses [p. 679]
J. Ye, Y. Hu and X. Li

PDF icon On Multiplexed Signal Tracing for Post-Silicon Debug [p. 685]
X. Liu and Q. Xu

PDF icon Eliminating Data Invalidation in Debugging Multiple-Clock Chips [p. 691]
J. Gao, Y. Han and X. Li

6.6: Embedded Software for Parallel Architectures

Moderators: O. Bringmann, FZI Karlsruhe, DE; F. Slomka, Ulm U, DE
PDF icon Parallelization of While Loops in Nested Loop Programs for Shared-Memory Multiprocessor Systems [p. 697]
S.J. Geuns, M.J.G. Bekooij, T. Bijlsma and H. Corporaal

PDF icon Gemma in April: A Matrix-Like Parallel Programming Architecture on OpenCL [p. 703]
T. Wu, D. Wu, Y. Wang, X. Zhang, H. Luo, N. Xu and H. Yang

PDF icon Evaluating the Potential of Graphics Processors for High Performance Embedded Computing [p. 709]
S. Mu, C. Wang, M. Liu, D. Li, M. Zhu, X. Chen, X. Xie and Y. Deng

6.7: HOT TOPIC - Virtual Manycore Platforms: Moving Towards 100+ Processor Cores

Moderator: F. Ghenassia, STMicroelectronics, FR
PDF icon Virtual Manycore Platforms: Moving Towards 100+ Processor Cores [p. 715]
R. Leupers, G. Martin, N. Topham, L. Eeckhout, F. Schirrmeister and X. Chen

6.8: PANEL SESSION - Embedded Software Debug and Test

Moderator: M. Winterholer, Cadence, DE
PDF icon Embedded Software Debug and Test - Needs and Requirements for Innovations in Debugging [p. 721]
M. Winterholer

Panelists: F. Cerisier, S. Davidmann, L. Ducuosso, J. Engblom, and A. Mayer

7.1: SMART DEVICES HOT TOPIC - Smart Medical Implants

Moderator: S. Yoo, POSTECH, KR
PDF icon Powering and Communicating with mm-size Implants [p. 722]
J.M. Rabaey, M. Mark, D. Chen, C. Sutardja, C. Tang, S. Gowda, M. Wagner and D. Werthimer

PDF icon An Antenna-Filter Co-Design for Cardiac Implants [p. 728]
E. de Foucauld, J.-B. David, C. Delaveaud and P. Ciais

7.2: Emerging Memory Technologies

Moderators: H. Li, New York U, US; Y. Chen, Pittsburgh U, US
PDF icon Design Implications of Memristor-Based RRAM Cross-Point Structures [p. 734]
C. Xu, X. Dong, N.P. Jouppi and Y. Xie

PDF icon Robust 6T Si Tunneling Transistor SRAM Design [p. 740]
X. Yang and K. Mohanram

PDF icon Towards Energy Efficient Hybrid On-Chip Scratch Pad Memory with Non-Volatile Memory [p. 746]
J. Hu, C.J. Xue, Q. Zhuge, W.-C. Tseng, E.H.-M. Sha

7.3: Architectural Optimization for Low Power Systems

Moderators: A. Nannarelli, TU Denmark, DK; W. Nebel, Oldenburg U and OFFIS, DE
PDF icon A New Reconfigurable Clock-Gating Technique for Low Power SRAM-Based FPGAs [p. 752]
L. Sterpone, L. Carro, D. Matos, S. Wong and F. Fakhar

PDF icon Controlled Timing-Error Acceptance for Low Energy IDCT Design [p. 758]
K. He, A. Gerstlauer and M. Orshansky

PDF icon Energy Parsimonious Circuit Design through Probabilistic Pruning [p. 764]
A. Lingamneni, C. Enz, J.-L. Nagel, K. Palem and C. Piguet

PDF icon Stage Number Optimization for Switched Capacitor Power Converters in Micro-Scale Energy Harvesting [p. 770]
C. Lu, S.P. Park, V. Raghunathan and K. Roy

7.4: Advanced Technologies for NoC Implementation

Moderators: D. Bertozzi, Ferrara U, IT; P. Vivet, CEA-LETI, FR
PDF icon Interconnect-Fault-Resilient Delay-Insensitive Asynchronous Communication Link Based on Current-Flow Monitoring [p. 776]
N. Onizawa, A. Matsumoto and T. Hanyu

PDF icon VANDAL: A Tool for the Design Specification of Nanophotonic Networks [p. 782]
G. Hendry, J. Chan, L.P. Carloni and K. Bergman

PDF icon Optical Ring Network-on-Chip (ORNoC): Architecture and Design Methodology [p. 788]
S. Le Beux, J. Trajkovic, I. O'Connor, G, Nicolescu, G. Bois and P. Paulin

7.5: Emerging Test Solutions for Advanced Technologies, RF and MEMS Devices

Moderators: S. Khursheed, Southampton U, UK; J. Machado da Silva, INESC Porto, PT
PDF icon Multidimensional Parametric Test Set Optimization of Wafer Probe Data for Predicting in Field Failures and Setting Tighter Test Limits [p. 794]
D. Drmanac, N. Sumikawa, L. Winemberg, L.-C. Wang and M.S. Abadir

PDF icon On Design of Test Structures for Lithographic Process Corner Identification [p. 800]
A. Sreedhar and S. Kundu

PDF icon An Electrical Test Method for MEMS Convective Accelerometers: Development and Evaluation [p. 806]
A.A. Rekik, F. Azaïs, N. Dumas, F. Mailly and P. Nouet

PDF icon Correlating Inline Data with Final Test Outcomes in Analog/RF Devices [p. 812]
N. Kupp, M. Slamani and Y. Makris

7.6: Innovative Power-Aware Systems for a Green and Healthy Society

Moderators: W. Eberle, IMEC, BE; E. Popovici, National U of Ireland, IE
PDF icon Systematic Design of a Programmable Low-Noise CMOS Neural Interface for Cell Activity Recording [p. 818]
C.M. López, S. Musa, C. Bartic, R. Puers, G. Gielen and W. Eberle

PDF icon A Real-Time Compressed Sensing-Based Personal Electrocardiogram Monitoring System [p. 824]
K. Kanoun, H. Mamaghanian, N. Khaled and D. Atienza

PDF icon A Distributed and Self-Calibrating Model-Predictive Controller for Energy and Thermal Management of High-Performance Multicores [p. 830]
A. Bartolini, M. Cacciari, A. Tilli and L. Benini

PDF icon An Effective Multi-Source Energy Harvester for Low Power Applications [p. 836]
D. Carli, D. Brunelli, L. Benini and M. Ruggeri

7.7: HOT TOPIC - Foundations of Component-Based Design for Embedded Systems

Moderators: A. Sangiovanni-Vincentelli, UC Berkeley, US and Trento U, IT; J. Sifakis, VERIMAG, FR
PDF icon Composing Heterogeneous Components for System-Wide Performance Analysis [p. 842]
S. Perathoner, K. Lampka and L. Thiele

7.8: EMBEDDED TUTORIAL - Predictable System Integration

Moderator: W. Kruijtzer, Synopsys, NL
PDF icon Building Real-time HDTV Applications in FPGAs Using Processors, AXI Interfaces and High Level Synthesis Tools [p. 848]
K. Vissers, S. Neuendorffer and J. Noguera

PDF icon Architectures and Modeling of Predictable Memory Controllers for Improved System Integration [p. 851]
B. Akesson and K. Goossens

PDF icon SoC Infrastructures for Predictable System Integration [p. 857]
P. van der Wolf and J. Geuzebroek

IP3: Interactive Presentations

PDF icon Early Chip Planning Cockpit [p. 863]
J. Shin, J.A. Darringer, G. Luo, A.J. Weger and C.L. Johnson

PDF icon Power Reduction via Near-Optimal Library-Based Cell-Size Selection [p. 867]
M. Rahman, H. Tennakoon and C. Sechen

PDF icon Scalable Packet Classification via GPU Metaprogramming [p. 871]
K. Kang and Y.S. Deng

PDF icon Battery-Supercapacitor Hybrid System for High-Rate Pulsed Load Applications [p. 875]
D. Shin, Y. Kim, J. Seo, N. Chang, Y. Wang and M. Pedram

PDF icon Feedback Based Droop Mitigation [p. 879]
S. Pontarelli, M. Ottavi, A. Salsano and K. Zarrineh

PDF icon A 0.964mW Digital Hearing Aid System [p. 883]
P. Qiao, H. Corporaal and M. Lindwer

PDF icon HypoEnergy: Hybrid Supercapacitor-Battery Power-Supply Optimization for Energy Efficiency [p. 887]
A. Mirhoseini and F. Koushanfar

PDF icon Fine-Grain OpenMP Runtime Support with Explicit Communication Hardware Primitives [p. 891]
P. Tendulkar, V. Papaefstathiou, G. Nikiforos, S. Kavadias, D.S. Nikolopoulos and M. Katevenis

PDF icon Transition-Time-Relation Based Capture-Safety Checking for At-Speed Scan Test Generation [p. 895]
K. Miyase, X. Wen, M. Aso, H. Furukawa, Y. Yamato and S. Kajihara

PDF icon 2D and 3D Integration with Organic and Silicon Electronics [p. 899]
C.K. Landrock, B. Omrane, Y. Chuo, B. Kaminska and J. Aristizabal

PDF icon Ultra Low-Power Photovoltaic MPPT Technique for Indoor and Outdoor Wireless Sensor Nodes [p. 905]
A.S. Weddell, G.V. Merrett and B.M. Al-Hashimi

PDF icon A fault-Tolerant Deadlock-Free Adaptive Routing for On Chip Interconnects [p. 909]
F. Chaix, D. Avresky, N.-E. Zergainoh and M. Nicolaidis

8.1: SMART DEVICES PANEL SESSION - Integrating the Real World Interfaces [p. 913]

Moderators: A. Jerraya, CEA-LETI MINATEC, FR; J. Goodacre, ARM, UK

Panelists: P. Urard, J. Rabaey, R. Bramley, A. King-Smith, W. Burleson, and F. Perruchot

PDF icon

8.2: System-Level Design Techniques for Automotive Systems

Moderators: J. Teich, Erlangen-Nuremberg U, DE; L. Lavagno, Politecnico di Torino, IT
PDF icon Re-Engineering Cyber-Physical Control Applications for Hybrid Communication Protocols [p. 914]
D. Goswami, R. Schneider and S. Chakraborty

PDF icon Precise WCET Calculation in Highly Variant Real-Time Systems [p. 920]
P. Montag and S. Altmeyer

PDF icon Optimal Scheduling of Switched FlexRay Networks [p. 926]
T. Schenkelaars, B. Vermeulen and K. Goossens

8.3: Power/Error Tradeoffs

Moderators: L. Bai, U of Michigan, US; J. Chen, Karlsruhe Institute of Technology, DE
PDF icon On the Efficacy of NBTI Mitigation Techniques [p. 932]
T.-B. Chan, J. Sartori, P. Gupta and R. Kumar

PDF icon Partitioned Cache Architectures for Reduced NBTI-Induced Aging [p. 938]
A. Calimera, M. Loghi, E. Macii and M. Poncino

PDF icon Adaptive Voltage Over-Scaling for Resilient Applications [p. 944]
P.K. Krause and I. Polian

PDF icon Design of Voltage-Scalable Meta Functions for Approximate Computing [p. 950]
D. Mohapatra, V.K. Chippa, A. Raghunathan and K. Roy

8.4: Memory System Architectures

Moderators: T. Austin, U of Michigan, US; G. Gaydadjiev, TU Delft, NL
PDF icon MLP Aware Heterogeneous Memory System [p. 956]
S. Phadke and S. Narayanasamy

PDF icon Impact of Process Variation on Endurance Algorithms for Wear-Prone Memories [p. 962]
A.P. Ferreira, S. Bock, B. Childers, R. Melhem and D. Mossé

PDF icon FlexMemory: Exploiting and Managing Abundant Off-Chip Optical Bandwidth [p. 968]
Y. Wang, L. Zhang, Y. Han, H. Li and X. Li

PDF icon Scratchpad Memory Optimizations for Digital Signal Processing Applications [p. 974]
S.Z. Gilani, N.S. Kim and M. Schulte

8.5: Testing and Designing SRAM Memories

Moderators: S. Nassif, IBM, US; X. Wen, Kyushu Institute of Technology, JP
PDF icon Robustness Analysis of 6T SRAMs in Memory Retention Mode under PVT Variations [p. 980]
E.I. Vatajelu and J. Figueras

PDF icon Stability Optimization of Embedded 8T SRAMs Using Word-Line Voltage Modulation [p. 986]
B. Alorda, G. Torrens, S. Bota and J. Segura

PDF icon Proactive Recovery for BTI in High-K SRAM Cells [p. 992]
L. Li, Y. Zhang and J. Yang

8.6: Cryptoanalysis, Attacks and Countermeasures

Moderators: K. Sakiyama, U of Electro-Communications, Tokyo, JP; L. Torres, LIRMM, FR
PDF icon The Potential of Reconfigurable Hardware for HPC Cryptanalytic of SHA-1 [p. 998]
A. Cilardo

PDF icon Enhancement of Simple Electro-Magnetic Attacks by Pre-Characterization in Frequency Domain and Demodulation Techniques [p. 1004]
O. Meynard, D. Réal, F. Flament, S. Guilley, N. Homma and J.-L. Danger

PDF icon LOEDAR: A Low Cost Error Detection and Recovery Scheme for ECC [p. 1010]
K. Ma and K. Wu

PDF icon Low-cost Fault Detection Method for ECC Using Montgomery Powering Ladder [p. 1016]
D. Karaklajic, J. Fan, J.-M. Schmidt and I. Verbauwhede

8.7: HOT TOPIC - Flows, Application and Future of Component-based Design for Embedded Systems

Moderator: A. Sangiovanni-Vincentelli, UC Berkeley, US and Trento U, IT
PDF icon Methods and Tools for Component-Based System Design [p. 1022]
J Sifakis

PDF icon Using Contract-Based Component Specifications for Virtual Integration Testing and Architecture Design [p. 1023]
W. Damm, H. Hungar, B. Josko, T. Peikenkamp and I. Stierand

PDF icon Component-Based Design for the Future [p. 1029]
E.A. Lee and A.L. Sangiovanni-Vincentelli

8.8: EMBEDDED TUTORIAL - Communication Networks in Next Generation Automobiles

Moderator: C. Grimm, TU Vienna, AT
PDF icon Sensor Networks on the Car: State of the Art and Future Challenges [p. 1030]
L. D'Orazio, F. Visintainer and M. Darin

PDF icon Real-Time Wireless Communication in Automotive Applications [p. 1036]
R. Matischek, T. Herndl, C. Grimm and J. Haase

PDF icon Wireless Communication and Energy Harvesting in Automobiles [p. 1042]
S. Mahlknecht, T. Kazmierski, C. Grimm and L. Wang

9.1: INTELLIGENT ENERGY MANAGEMENT TUTORIAL - Energy Transfer, Generation and Power Electronics

Moderator: P. Mitcheson, Imperial College, UK
PDF icon Power Management Trends in Portable Consumer Applications [p. 1048]
J. Brown

9.2: Design Automation Methodologies for Emerging Technologies

Moderators: K. Mohanram, Rice U, US; S. Bhanja, South Florida U, US
PDF icon An Efficient Mask Optimization Method Based on Homotopy Continuation Technique [p. 1053]
F. Liu and X. Shi

PDF icon Waste-Aware Dilution and Mixing of Biochemical Samples with Digital Microfluidic Biochips [p. 1059]
S. Roy, B.B. Bhattacharya and K. Chakrabarty

PDF icon High-Temperature (>500°C) Reconfigurable Computing Using Silicon Carbide NEMS Switches [p. 1065]
X. Wang, S. Narasimhan, A. Krishna, F.G. Wolff, S. Rajgopal, T.-H. Lee, M. Mehregany and S. Bhunia

PDF icon Case Study: Alleviating Hotspots and Improving Chip Reliability via Carbon Nanotube Thermal Interface [p. 1071]
W. Zhang, J. Huang, S. Yang and P. Gupta

9.3: System Modeling

Moderators: J. Haase, TU Vienna, AT; D. Borrione, TIMA Laboratory, FR
PDF icon Verifying Dynamic Aspects of UML Models [p. 1077]
M. Soeken, R. Wille and R. Drechsler

PDF icon Automated Construction of Fast and Accurate System-Level Models for Wireless Sensor Networks [p. 1083]
L.S. Bai, R.P. Dick, P. Chou and P.A. Dinda

PDF icon Fast and Accurate Transaction-Level Model of a Wormhole Network-on-Chip with Priority Preemptive Virtual Channel Arbitration [p. 1089]
L.S. Indrusiak and O.M. dos Santos

PDF icon A High-Level Analytical Model for Application Specific CMP Design Exploration [p. 1095]
A. Cassidy, K. Yu, H. Zhou and A.G. Andreou

9.4: Modeling and Verification of Analogue and RF Circuits

Moderators: L. Hedrich, Frankfurt U, DE; M. Olbrich, Hannover U, DE
PDF icon Global Optimization of Integrated Transformers for High Frequency Microwave Circuits Using a Gaussian Process Based Surrogate Model [p. 1101]
B. Liu, Y. He, P. Reynaert and G. Gielen

PDF icon A Method for Fast Jitter Tolerance Analysis of High-Speed PLLs [p. 1107]
S. Erb and W. Pribyl

PDF icon SAMURAI: An Accurate Method for Modeling and Simulating Non-Stationary Random Telegraph Noise in SRAMs [p. 1113]
K.V. Aadithya, A. Demir, S. Venugopalan and J. Roychowdhury


Moderators: D. Sciuto, Politecnico di Milano, IT; L. Anghel, TIMA Laboratory, FRA
PDF icon Characterization of an Intelligent Power Switch for LED Driving with Control of Wiring Parasitics Effects [p. 1119]
G. Pasetti, N. Constantino, F. Tinfena, R. Serventi, P. D'Abramo, S. Saponara and L. Fanucci

PDF icon Energy Analysis Methods and Tools For Modelling and Optimizing Tyre Systems [p. 1121]
A. Bonanno, A. Bocca and M. Sabatini

PDF icon System Level Techniques to Improve Reliability in High Power Microcontrollers for Automotive Applications [p. 1123]
A. Acquaviva, M. Poncino, M. Ottella and M. Sciolla

PDF icon System-Level Power Estimation Methodology Using Cycle- and Bit-Accurate TLM [p. 1125]
M.D. Grammatikakis, S. Politis, J.-P. Schoellkopf and C. Papadas

PDF icon Moving to Green ICT: From Stand-Alone Power-Aware IC Design to an Integrated Approach to Energy Efficient Design of Heterogeneous Electronic Systems [p. 1127]
S. Rinaudo, G. Gangemi, A. Calimera, A. Macii and M. Poncino

9.6: Embedded System Resource Allocation and Management

Moderators: S. Chakraborty, TU Munich, DE; A. Girault, INRIA, Rhone-Alpes, FR
PDF icon A Workflow for Runtime Adaptive Task Allocation on Heterogeneous MPSoCs [p. 1129]
J. Huang, A. Raabe, C. Buckl and A. Knoll

PDF icon Energy-Efficient Scheduling of Real-Time Tasks on Cluster-Based Multicores [p. 1135]
F. Kong, W. Yi and Q. Deng

PDF icon E-RoC: Embedded Raids-on-Chip for Low Power Distributed Dynamically Managed Reliable Memories [p. 1141]
L.A.D. Bathen and N.D. Dutt

9.7: EMBEDDED TUTORIAL - Sub-Wave Length Lithography and Variability Aware Test and Characterization Methods

Moderator: R. Galivanche, Intel Corporation, US
PDF icon Modeling Manufacturing Process Variation for Design and Test [p. 1147]
S. Kundu and A. Sreedhar

PDF icon Variability Aware Modeling for Yield Enhancement of SRAM and Logic [p. 1153]
M. Miranda, P. Zuber, P. Dobrovolný and P. Roussel

PDF icon Correlating Models and Silicon for Improved Parametric Yield [p. 1159]
R. Aitken, G. Yeric and D. Flynn

IP4: Interactive Presentations

PDF icon Evaluating Energy Consumption of Homogeneous MPSoCs Using Spare Tiles [p. 1164]
A.M. Amory, L.C. Ost, C.A.M. Marcon, F.G. Moraes and M.S. Lubaszewski

PDF icon Improving the Efficiency of a Hardware Transactional Memory on an NoC-based MPSoC [p. 1168]
L. Kunz, G. Girão and F.R. Wagner

PDF icon Analytical Model for SRAM Dynamic Write-Ability Degradation Due to Gate Oxide Breakdown [p. 1172]
V. Chandra and R. Aitken

PDF icon Multi-Level Attacks: An Emerging Security Concern for Cryptographic Hardware [p. 1176]
S.S. Ali, R.S. Chakraborty, D. Mukhopadhyay and S. Bhunia

PDF icon A New Reversible Design of BCD Adder [p. 1180]
H. Thapliyal and N. Ranganathan

PDF icon jTLM: An Experimentation Framework for the Simulation of Transaction-Level Models of Systems-on-Chip [p. 1184]
G. Funchal and M. Moy

PDF icon Ensuring Correctness of Analog Circuits in Presence of Noise and Process Variations Using Pattern Matching [p. 1188]
R. Narayanan, M.H. Zaki and S. Tahar

PDF icon A Multi-Objective Decision-Theoretic Exploration Algorithm for Platform-Based Design [p. 1192]
G. Beltrame and G. Nicolescu

PDF icon Predicting Bus Contention Effects on Energy and Performance in Multi-Processor SoCs [p. 1196]
S. Penolazzi, I. Sander and A. Hemani

PDF icon A Specialized Low-Cost Vectorized Loop Buffer for Embedded Processors [p. 1200]
L. Huang, Z. Wang, L. Shen, H. Lu, N. Xiao and C. Liu

PDF icon Determining the Minimal Number of Lines for Large Reversible Circuits [p. 1204]
R. Wille, O. Keszöcze and R. Drechsler

PDF icon Dynamic Applications on Reconfigurable Systems: From UML Model Design to FPGAs Implementation [p. 1208]
J. Vidal, F. de Lamotte, G. Gogniat, J.-P. Diguet and S. Guillet

PDF icon A Symbolic Technique for Automated Characterization of the Uniqueness and Similarity of Analog Circuit Design Features [p. 1212]
C. Ferent and A. Doboli

PDF icon Coordinate Strip-Mining and Kernel Fusion to Lower Power Consumption on GPU [p. 1216]
G. Wang

PDF icon An Efficient Quantum-Dot Cellular Automata Adder [p. 1220]
F. Bruschi, F. Perini, V. Rana and D. Sciuto

10.1.1: INTELLIGENT ENERGY MANAGEMENT - Smart Energy Generation: Design Automation and the Smart-Grid

Moderators: P.K. Wright, UK Berkeley, US
PDF icon Understanding the Role of Buildings in a Smart Microgrid [p. 1224]
Y. Agarwal, T. Weng and R.K. Gupta


Moderator: P.K. Wright, UC Berkeley, US
PDF icon Smart Systems at ST [p. 1230]
C. Papa

10.2: Advanced Algorithms and Applications for Reconfigurable Computing

Moderators: M. Huebner, Karlsruhe Institute of Technology (KIT), DE; C. Passerone, Politecnico di Torino, IT
PDF icon Theoretical Modeling of the Itoh-Tsujii Inversion Algorithm for Enhanced Performance on k-LUT Based FPGAs [p. 1231]
S.S. Roy, C. Rebeiro and D. Mukhopadhyay

PDF icon SHARC: A Streaming Model for FPGA Accelerators and its Application to Saliency [p. 1237]
S. Kestur, D. Dantara and V. Narayanan

PDF icon A Reconfigurable, Pipelined, Conflict Directed Jumping Search SAT Solver [p. 1243]
M. Safar, M.W. El-Kharashi, M. Shalan and A. Salem

10.3: System Optimizations and Adaptivity

Moderators: M. Berekovic, TU Braunschweig, DE; S. Yehia, Thales Research and Technology, FR
PDF icon Reducing the Cost of Redundant Execution in Safety-Critical Systems Using Relaxed Dedication [p. 1249]
B.H. Meyer, N. George, B. Calhoun, J. Lach and K. Skadron

PDF icon Frugal but Flexible Multicore Topologies in Support of Resource Variation-Driven Adaptivity [p. 1255]
C. Yang and A. Orailoglu

PDF icon Minority-Game-Based Resource Allocation for Run-Time Reconfigurable Multi-Core Processors [p. 1261]
M. Shafique, L. Bauer, W. Ahmed and J. Henkel

10.4: Design and Simulation of Mixed-Signal Systems

Moderators: M. Louerat, UPMC Paris, FR; I. O'Connor, EC Lyon, FR
PDF icon Accelerated Simulation of Tunable Vibration Energy Harvesting Systems Using a Linearised State-Space Technique [p. 1267]
L. Wang, T.J. Kazmierski, B.M. Al-Hashimi, A.S. Weddell, G.V. Merrett and I.N. Ayala Garcia

PDF icon Simulation Based Tuning of System Specification [p. 1273]
Y. Zaidi, C. Grimm and J. Haase

PDF icon An Extension to SystemC-A to Support Mixed-Technology Systems with Distributed Components [p. 1279]
C. Zhao and T.J. Kazmierski

PDF icon Stochastic Circuit Reliability Analysis [p. 1285]
E. Maricau and G. Gielen

10.5: Advances in Test Generation and Fault Simulation

Moderators: I. Polian, Passau U, DE; A. Virazel, LIRMM, FR
PDF icon As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects Using Pseudo-Boolean Optimization [p. 1291]
S. Eggersglüβ and R. Drechsler

PDF icon Built-In Generation of Functional Broadside Tests [p. 1297]
I. Pomeranz

PDF icon SAT-Based Fault Coverage Evaluation in the Presence of Unknown Values [p. 1303]
M.A. Kochte and H.-J. Wunderlich

10.6: Model Based Verification and Synthesis of Embedded Systems

Moderators: R. Majumdar, Max Planck Institute for Software Systems, DE; P. Pop, TU Denmark, DK
PDF icon When to Stop Verification? Statistical Trade-Off between Expected Loss and Simulation Cost [p. 1309]
S.K. Jha, C.J. Langmead, S. Mohalik and S. Ramesh

PDF icon Resynchronization of Cyclo-Static Dataflow Graphs [p. 1315]
J.P.H.M. Hausmans, M.J.G. Bekooij and H. Corporaal

PDF icon Pipeline Schedule Synthesis for Real-Time Streaming Tasks with Inter/Intra-Instance Precedence Constraints [p. 1321]
Y.-S. Chiu, C.-S. Shih, S.-H. Hung

10.7: EMBEDDED TUTORIAL - Die Stacking Goes Mobile and Embedded

Moderator: Y. Xie, Penn State U, US

PDF icon 3D Embedded Multi-Core: Some Perspectives [p. 1327]
F. Clermidy, F. Darve, D. Dutoit, W. Lafi and P. Vivet

PDF icon A Quantitative Analysis of Performance Benefits of 3D Die Stacking on Mobile and Embedded SoC [p. 1333]
D. Kim, S. Yoo, S. Lee, J.H. Ahn and H. Jung

10.8: PANEL SESSION - State of the Art Verification Methodologies in 2015 [p. 1339]

Moderator: A.. Crone

Panelists: O. Bringmann, C. Chevallaz, B. Dickman, V. Esen, and M. Rohleder

PDF icon

11.1: INTELLIGENT ENERGY MANAGEMENT - Smart Energy Utilization: From Circuits to Consumer Products

Moderator: P. Mitcheson, Imperial College, UK
PDF icon Energy-Modulated Computing [p. 1340]
A. Yakovlev

11.2: Architectural Innovations for Reconfigurable Computing

Moderators: D. Goehringer, Fraunhofer Institute, DE; K. Bertels, TU Delft, NL
PDF icon I2CRF: Incremental Interconnect Customization for Embedded Reconfigurable Fabrics [p. 1346]
J.W. Yoon, J. Lee, J. Jung, S. Park, Y. Kim, Y. Paek and D. Cho

PDF icon MARC II: A Parametrized Speculative Multi-Ported Memory Subsystem for Reconfigurable Computers [p. 1352]
H. Lange, T. Wink and A. Koch

PDF icon Targeting Code Diversity with Run-Time Adjustable Issue-Slots in a Chip Multiprocessor [p. 1358]
F. Anjam, M. Nadeem and S. Wong

11.3: Asynchronous Circuits and Advanced Timing Issues in Logic Synthesis

Moderators: T. Villa, Verona U, IT; P. Vivet, CEA-LETI, FR
PDF icon An Efficient Algorithm for Multi-Domain Clock Skew Scheduling [p. 1364]
Y. Zhi, W.-S. Luk, H. Zhou, C. Yan, H. Zhu and X. Zeng

PDF icon A Delay-Insensitive Bus-Invert Code and Hardware Support for Robust Asynchronous Global Communication [p. 1370]
M.Y. Agyekum and S.M. Nowick

PDF icon Redressing Timing Issues for Speed-Independent Circuits in Deep Submicron Age [p. 1376]
Y. Li, T. Mak and A. Yakovlev

11.4: High Level Synthesis

Moderators: S. Singh, Microsoft Research, UK; P. Brisk, UC Riverside, US
PDF icon Realistic Performance-Constrained Pipelining in High-Level Synthesis [p. 1382]
A. Kondratyev, L. Lavagno, M. Meyer and Y. Watanabe

PDF icon Optimization of Mutually Exclusive Arithmetic Sum-of-Products [p. 1388]
T. Drane and G. Constantinides

PDF icon Intermediate Representations for Controllers in Chip Generators [p. 1394]
K. Kelley, M. Wachs, A. Danowitz, P. Stevenson, S. Richardson and M. Horowitz

PDF icon Power Optimization in Heterogenous Datapaths [p. 1400]
A.A. Del Barrio, S.O. Memik, M.C. Molina, J.M. Mendias and R. Hermida

PDF icon Abstract State Machines as an Intermediate Representation for High-Level Synthesis [p. 1406]
R. Sinha and H.D. Patel

11.5: New Directions in Testing

Moderators: J. Schloeffel, Mentor Graphics, DE; J. Tyszer, TU Poznan, PL
PDF icon Design Automation for IEEE P1687 [p. 1412]
F.G. Zadegan, U. Ingelsson, G. Carlsson and E. Larsson

PDF icon On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs [p. 1418]
M. Buttrick and S. Kundu

PDF icon Hyper-Graph Based Partitioning to Reduce DFT Cost for Pre-Bond 3D-IC Testing [p. 1424]
A. Kumar, S.M. Reddy, I. Pomeranz and B. Becker

PDF icon Adaptive Test Optimization through Real Time Learning of Test Effectiveness [p. 1430]
B. Arslan and A. Orailoglu

11.6: Hardware Design for Multimedia Applications

Moderators: F. Clermidy, CEA-LETI, FR; A. Baghdadi, Telecom Bretagne, FR
PDF icon A High-Performance Parallel Implementation of the Chambolle Algorithm [p. 1436]
A. Akin, I. Beretta, A.A. Nacci, V. Rana, M.D. Santambrogio and D. Atienza

PDF icon Depth-Directed Hardware Object Detection [p. 1442]
C. Kyrkou, C. Ttofis and T. Theocharides

PDF icon Multi-Level Pipelined Parallel Hardware Architecture for High Throughput Motion and Disparity Estimation in Multiview Video Coding [p. 1448]
B. Zatt, M. Shafique, S. Bampi and J. Henkel

11.7: HOT TOPIC - New Frontiers in Embedded Systems Design: Technology and Applications

Moderator: H. Meyr, RWTH Aachen U, DE
PDF icon An Integrated Platform for Advanced Diagnostics [p. 1454]
G. De Micheli, S.S. Ghoreishizadeh, C. Boero, F. Valgimigli and S. Carrara

PDF icon X-SENSE: Sensing in Extreme Environments [p. 1460]
J. Beutel, B. Buchli, F. Ferrari, M. Keller, M. Zimmerling and L. Thiele

PDF icon Towards Thermally-Aware Design of 3D MPSoCs with Inter-Tier Cooling [p. 1466]
M.M. Sabry, A. Sridhar, D. Atienza, Y. Temiz, Y. Leblebici, S. Szczukiewicz, N. Borhani, J.R. Thome, T. Brunschwiler and B. Michel

PDF icon A Circuit Technology Platform for Medical Data Acquisition and Communication [p. 1472]
Q. Huang, C. Dehollain, C. Enz and T. Burger

11.8: HOT TOPIC - Stochastic Circuit Reliability Analysis in Nanometer CMOS

Moderator: G. Gielen, KU Leuven, BE
PDF icon Analog Circuit Reliability in Sub-32 Nanometer CMOS: Analysis and Mitigation [p. 1474]
G. Gielen, E. Maricau and P. De Wit

PDF icon Statistical Aspects of NBTI/PBTI and Impact on SRAM Yield [p. 1480]
A. Asenov, A.R. Brown and B. Cheng

PDF icon Mathematical Approach Based on a "Design of Experiment" to Simulate Process Variations [p. 1486]
E. Rémond, E. Nercessian, C. Bernicot and R. Mina

PDF icon System-Assisted Analog Mixed-Signal Design [p. 1491]
N. Shanbhag and A. Singer

IP5: Interactive Presentations

PDF icon Priority Division: A High-Speed Shared-Memory Bus Arbitration with Bounded Latency [p. 1497]
H. Shah, A. Raabe and A. Knoll

PDF icon System-Level Modeling of a Mixed-Signal System on Chip for Wireless Sensor Networks [p. 1501]
G.S. Beserra, J.E.G. de Medeiros, A.M. Sampaio, J. Camargo da Costa

PDF icon A UML 2-Based Hardware/Software Co-Design Framework for Body Sensor Network Applications [p. 1505]
Z. Sun, C.-T. Yeh and W.-F. Wong

PDF icon An Area-Efficient Multi-Level Single-Track Pipeline Template [p. 1509]
P. Golani and P.A. Beerel

PDF icon Slack-Aware Scheduling on Coarse Grained Reconfigurable Arrays [p. 1513]
G. Ansaloni, L. Pozzi, K. Tanimura and N. Dutt

PDF icon Timing Variation-Aware Custom Instruction Extension Technique [p. 1517]
M. Kamal, A. Afzali-Kusha and M. Pedram

PDF icon Pseudo Circuit Model for Representing Uncertainty in Waveforms [p. 1521]
A. Nigam, Q. Tang, A. Zjajo, M. Berkelaar, and N. van der Meijs

PDF icon A Global Postsynthesis Optimization Method for Combinational Circuits [p. 1525]
Z. Vasicek and L. Sekanina

PDF icon An Algorithm to Improve Accuracy of Criticality in Statistical Static Timing Analysis [p. 1529]
S. Tsukiyama and M. Fukui

PDF icon An Approach for Dynamic Selection of Synthesis Transformations Based on Markov Decision Processes [p. 1533]
T. Welp and A. Kuehlmann

PDF icon Modeling Circuit Performance Variations Due to Statistical Variability: Monte Carlo Static Timing Analysis [p. 1537]
M. Merrett, P. Asenov, Y. Wang, M. Zwolinski, D. Reid, C. Millar, S. Roy, Z. Liu, S. Furber and A. Asenov

12.1: INTELLIGENT ENERGY MANAGEMENT PANEL SESSION - The Role of the EDA Community in the Future of World Energy Supply and Conservation?

Moderators: P.K. Wright, UC Berkeley, US; P. Mitcheson, Imperial College, UK

PDF icon What Does the Power Industry Need from the EDA Industry and What Is the EDA Industry Doing About It? [p. 1541]
P.K. Wright

Panelists: L. Bomhold, T. Green, A. Ephrimides, C. Blumstein

12.2: Design and Run-Time Support for Dynamic Reconfigurability

Moderators: P. Lysaght, Xilinx, US; F. Ferrandi, Politecnico di Milano, IT
PDF icon Fast Startup for Spartan-6 FPGAs Using Dynamic Partial Reconfiguration [p. 1542]
J. Meyer, J. Noguera, M. Hübner, L. Braun, O. Sander, R.M. Gil, R. Stewart and J. Becker

PDF icon Loop Distribution for K-Loops on Reconfigurable Architectures [p. 1548]
O.S. Dragomir and K. Bertels

PDF icon mRTS: Run-Time System for Reconfigurable Processors with Multi-Grained Instruction-Set Extensions [p. 1554]
W. Ahmed, M. Shafique, L. Bauer and J. Henkel

12.3: Reliability and Error Tolerance in Logic Synthesis

Moderators: S. Nowick, Columbia U, US; A. Yakovlev, Newcastle U, UK
PDF icon Reliability-driven Don't Care Assignment for Logic Synthesis [p. 1560]
A. Zukoski, M.R. Choudhury and K. Mohanram

PDF icon A New Circuit Simplification Method for Error Tolerant Applications [p. 1566]
D. Shin and S.K. Gupta

PDF icon Aging-Aware Timing Analysis and Optimization Considering Path Sensitization [p. 1572]
K.-C. Wu and D. Marculescu

12.4: Multilevel Simulation and Validation

Moderators: A. Acquaviva, Politecnico di Torino, IT; E. Aboulhamid, Montreal U, CA
PDF icon Efficient Parameter Variation Sampling for Architecture Simulations [p. 1578]
F. Lu, R. Joseph, G. Trajcevski and S. Liu

PDF icon Temporal Parallel Simulation: A Fast Gate-Level HDL Simulation Using Higher Level Models [p. 1584]
D. Kim, M. Ciesielski, K. Shim and S. Yang

PDF icon A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation [p. 1590]
A. Adir, S. Copty, S. Landa, A. Nahir, G. Shurek, A. Ziv, C. Meissner and J. Schumann

PDF icon Efficient Validation Input Generation in RTL by Hybridized Source Code Analysis [p. 1596]
L. Liu and S. Vasudevan

PDF icon An Efficient and Scalable STA Tool with Direct Path Estimation and Exhaustive Sensitization Vector Exploration for Optimal Delay Computation [p. 1602]
S. Barceló, X. Gili, S. Bota and J. Segura

12.5: Error Correction and Resilience

Moderators: J. Abella, Barcelona Supercomputing Center, ES; D. Gizopoulos, Piraeus U, GR
PDF icon A Confidence-Driven Model for Error-Resilient Computing [p. 1608]
C.-H. Chen, Y. Kim, Z. Zhang, D. Blaauw, D. Sylvester, H. Naeimi and S. Sandhu

PDF icon Eliminating Speed Penalty in ECC Protected Memories [p. 1614]
M. Nicolaidis, T. Bonnoit and N.-E. Zergainoh

PDF icon Error Correcting Code Analysis for Cache Memory High Reliability and Performance [p. 1620]
D. Rossi, N. Timoncini, M. Spica and C. Metra

PDF icon Error Prediction Based on Concurrent Self-Test and Reduced Slack Time [p. 1626]
V. Gherman, J. Massas, S. Evain, S. Chevobbe and Y. Bonhomme

12.6: Security Modules from Layout to Network-on-Chip

Moderators: L. Fesquet, TIMA Laboratory, FR; V. Fischer, St. Etienne U, FR
PDF icon Physically Unclonable Functions for Embedded Security Based on Lithographic Variation [p. 1632]
A. Sreedhar and S. Kundu

PDF icon RON: An On-Chip Ring Oscillator Network for Hardware Trojan Detection [p. 1638]
X. Zhang and M. Tehranipoor

PDF icon Arithmetic Logic Units with High Error Detection Rates to Counteract Fault Attacks [p. 1644]
M. Medwed and S. Mangard

PDF icon Data-Oriented Performance Analysis of SHA-3 Candidates on FPGA Accelerated Computers [p. 1650]
Z. Chen, X. Guo, A. Sinha and P. Schaumont

12.7: HOT TOPIC - Sustainability through Massively Integrated Computing: Are We Ready to Break the Energy Efficiency Wall for Single-Chip Platforms?

Moderator: N. Nicolici, McMaster U, CA
PDF icon Sustainability through Massively Integrated Computing: Are We Ready to Break the Energy Efficiency Wall for Single-Chip Platforms? [p. 1656]
P. Pande, F. Clermidy, D. Puschini, I. Mansouri, P. Bogdan, R. Marculescu and A. Ganguly

12.8: HOT TOPIC - Synthesis Supported Increase of Efficiency in Analog Design

Moderator: R. Sommer, TU Ilmenau, DE
PDF icon Automated Constraint-Driven Topology Synthesis for Analog Circuits [p. 1662]
O. Mitea, M. Meissner, L. Hedrich and P. Jores

PDF icon A New Method for Automated Generation of Compensation Networks - The EDA Designer Finger [p. 1666]
R. Sommer, D. Krausse, E. Hennig, E. Schaefer and C. Sporrer

PDF icon Strategies for Initial Sizing and Operating Point Analysis of Analog Circuits [p. 1672]
V. Boos, J. Nowak, M. Sylvester, S. Henker, S. Höppner, H. Grimm, D. Krausse and R. Sommer

PDF icon Generator Based Approach for Analog Circuit and Layout Design and Optimization [p. 1675]
A. Graupner, R. Jancke and R. Wittmann