DATE 2011 AUTHOR INDEX
[A]
[B]
[C]
[D]
[E]
[F]
[G]
[H]
[I]
[J]
[K]
[L]
[M]
[N]
[O]
[P]
[Q]
[R]
[S]
[T]
[V]
[W]
[X]
[Y]
[Z]
 Aadithya,
K.V.

SAMURAI: An Accurate Method for Modeling and Simulating NonStationary Random Telegraph Noise in SRAMs
[p. 1113]
 Abadir,
M.S.

Multidimensional Parametric Test Set Optimization of Wafer Probe Data for Predicting in Field Failures and
Setting Tighter Test Limits
[p. 794]
 Abdallah,
R.A.

Timing Error Statistics for EnergyEfficient Robust DSP Systems
[p. 285]
 Abelmann,
L.

Buffering Implications for the Design Space of Streaming MEMS Storage
[p. 253]
 Aboulhamid,
E.M.

MultiGranularity Thermal Evaluation of 3D MPSoC Architectures
[p. 575]
 Acquaviva,
A.

An Efficient OnLine Task Allocation Algorithm for QoS and Energy Efficiency in Multicore Multimedia
Platforms
[p. 100]

System Level Techniques to Improve Reliability in High Power Microcontrollers for Automotive
Applications
[p. 1123]
 Adir,
A.

A Unified Methodology for PreSilicon Verification and PostSilicon Validation
[p. 1590]
 Adve,
S.V.

Architectures for Online Error Detection and Recovery in Multicore Processors
[p. 533]
 AfzaliKusha,
A.

Timing VariationAware Custom Instruction Extension Technique
[p. 1517]
 Agarwal,
Y.

Understanding the Role of Buildings in a Smart Microgrid
[p. 1224]
 Agyekum,
M.Y.

A DelayInsensitive BusInvert Code and Hardware Support for Robust Asynchronous Global
Communication
[p. 1370]
 Ahmadian,
S.N.

Soft Error Rate Estimation of Digital Circuits in the Presence of Multiple Event Transients (METs)
[p. 70]
 Ahmed,
W.

MinorityGameBased Resource Allocation for RunTime Reconfigurable MultiCore Processors
[p. 1261]

mRTS: RunTime System for Reconfigurable Processors with MultiGrained InstructionSet Extensions
[p. 1554]
 Ahn,
J.H.

A Quantitative Analysis of Performance Benefits of 3D Die Stacking on Mobile and Embedded SoC
[p. 1333]
 Aitken,
R.

Correlating Models and Silicon for Improved Parametric Yield
[p. 1159]
 Analytical Model for SRAM
Dynamic WriteAbility Degradation Due to Gate Oxide Breakdown [p. 1172]
 Aitken,
R.C.

Dynamic Write Limited Minimum Operating Voltage for Nanoscale SRAMs
[p. 467]
 Akesson,
B.

Architectures and Modeling of Predictable Memory Controllers for Improved System Integration
[p. 851]
 Akin,
A.

A HighPerformance Parallel Implementation of the Chambolle Algorithm
[p. 1436]
 Al Faruque,
M.A.

Dynamic Thermal Management in 3D MultiCore Architecture through RunTime Adaptation
[p. 299]

CARAT: ContextAware Runtime Adaptive Task Migration for Multi Core Architectures
[p. 515]
 Alacoque,
L.

Smart Imagers of the Future
[p. 437]
 AlDujaily,
R.

RunTime Deadlock Detection in NetworksonChip Using Coupled Transitive Closure Networks
[p. 497]
 AlHashimi,
B.M.

SubClock PowerGating Technique for Minimising Leakage Power During Active Mode
[p. 106]

Ultra LowPower Photovoltaic MPPT Technique for Indoor and Outdoor Wireless Sensor Nodes
[p. 905]

Accelerated Simulation of Tunable Vibration Energy Harvesting Systems Using a Linearised StateSpace
Technique
[p. 1267]
 Ali,
S.S.

MultiLevel Attacks: An Emerging Security Concern for Cryptographic Hardware
[p. 1176]
 AlKhayat,
R.

A Flexible High Throughput MultiASIP Architecture for LDPC and Turbo Decoding
[p. 228]
 Almeida,
G.M.

Achieving Composability in NoCBased MPSoCs Through QoS Management at Software Level
[p. 407]
 Alorda,
B.

Stability Optimization of Embedded 8T SRAMs Using WordLine Voltage Modulation
[p. 986]
 Altmeyer,
S.

Precise WCET Calculation in Highly Variant RealTime Systems
[p. 920]
 Amende,
T.

Compiling SyncCharts to Synchronous C
[p. 563]
 Amory,
A.M.

Evaluating Energy Consumption of Homogeneous MPSoCs Using Spare Tiles
[p. 1164]
 Andalam,
S.

Pruning Infeasible Paths for Tight WCRT Analysis of Synchronous Programs
[p. 204]
 Andreou,
A.G.

A HighLevel Analytical Model for Application Specific CMP Design Exploration
[p. 1095]
 Anjam,
F.

Targeting Code Diversity with RunTime Adjustable IssueSlots in a Chip Multiprocessor
[p. 1358]
 Ansaloni,
G.

SlackAware Scheduling on Coarse Grained Reconfigurable Arrays
[p. 1513]
 Apte,
C.

VariabilityAware Duty Cycle Scheduling in Long Running Embedded Sensing Systems
[p. 131]
 Aristizabal,
J.

2D and 3D Integration with Organic and Silicon Electronics
[p. 899]
 Arslan,
B.

Adaptive Test Optimization through Real Time Learning of Test Effectiveness
[p. 1430]
 Asadi,
H.

Soft Error Rate Estimation of Digital Circuits in the Presence of Multiple Event Transients (METs)
[p. 70]

ScTMR: A Scan ChainBased Error Recovery Technique for TMR Systems in SafetyCritical Applications
[p. 289]
 Asadinia,
M.

Supporting NonContiguous Processor Allocation in MeshBased CMPs Using Virtual PointtoPoint Links
[p. 413]
 Asenov,
A.

Statistical Aspects of NBTI/PBTI and Impact on SRAM Yield
[p. 1480]

Modeling Circuit Performance Variations Due to Statistical Variability: Monte Carlo Static Timing Analysis
[p. 1537]
 Asenov,
P.

Modeling Circuit Performance Variations Due to Statistical Variability: Monte Carlo Static Timing Analysis
[p. 1537]
 Aso,
M.

TransitionTimeRelation Based CaptureSafety Checking for AtSpeed Scan Test Generation
[p. 895]
 Atienza,
D.

A RealTime Compressed SensingBased Personal Electrocardiogram Monitoring System
[p. 824]

A HighPerformance Parallel Implementation of the Chambolle Algorithm
[p. 1436]
 Towards ThermallyAware
Design of 3D MPSoCs with InterTier Cooling [p. 1466]
 Avresky,
D.

A faultTolerant DeadlockFree Adaptive Routing for On Chip Interconnects
[p. 909]
 Ayala Garcia,
I.N.

Accelerated Simulation of Tunable Vibration Energy Harvesting Systems Using a Linearised StateSpace
Technique
[p. 1267]
 Azaïs,
F.

An Electrical Test Method for MEMS Convective Accelerometers: Development and Evaluation
[p. 806]
 Bacivarov,
I.

WorstCase Temperature Analysis for RealTime Systems
[p. 631]
 Baghdadi,
A.

A Flexible High Throughput MultiASIP Architecture for LDPC and Turbo Decoding
[p. 228]
 A Low Complexity Stopping
Criterion for Reducing Power Consumption in Turbo Decoders [p. 649]
 Bai,
L.S.

Simplified Programming of Faulty Sensor Networks via Code Transformation and RunTime
Interval Computation
[p. 88]
 Automated Construction of
Fast and Accurate SystemLevel Models for Wireless Sensor Networks [p.
1083]
 Baiocchi,
J.A.

Demand Code Paging for NAND Flash in MMUless Embedded Systems
[p. 527]
 Balani,
R.

VariabilityAware Duty Cycle Scheduling in Long Running Embedded Sensing Systems
[p. 131]
 Balasubramanian,
L.

Circuit and DFT Techniques for Robust and Low Cost Qualification of a MixedSignal SoC with Integrated
Power Management System
[p. 551]
 Ballan,
O.

Fault Grading of SoftwareBased SelfTest Procedures for Dependable Automotive Applications
[p. 513]
 Bampi,
S.

MultiLevel Pipelined Parallel Hardware Architecture for High Throughput Motion and Disparity Estimation
in Multiview Video Coding
[p. 1448]
 Banga,
M.

DesignforTest Methodology for NonScan AtSpeed Testing
[p. 191]
 Barceló,
S.

An Efficient and Scalable STA Tool with Direct Path Estimation and Exhaustive Sensitization Vector
Exploration for Optimal Delay Computation
[p. 1602]
 Bartic,
C.

Systematic Design of a Programmable LowNoise CMOS Neural Interface for Cell Activity Recording
[p. 818]
 Bartolini,
A.

A Distributed and SelfCalibrating ModelPredictive Controller for Energy and Thermal
Management of HighPerformance Multicores
[p. 830]
 Bathen,
L.A.D.

ERoC: Embedded RaidsonChip for Low Power Distributed Dynamically Managed Reliable Memories
[p. 1141]
 Bauer,
L.

MinorityGameBased Resource Allocation for RunTime Reconfigurable MultiCore Processors
[p. 1261]

mRTS: RunTime System for Reconfigurable Processors with MultiGrained InstructionSet Extensions
[p. 1554]
 Becker,
B.

Integration of Orthogonal QBF Solving Techniques
[p. 149]

HyperGraph Based Partitioning to Reduce DFT Cost for PreBond 3DIC Testing
[p. 1424]
 Becker,
J.

Fast Startup for Spartan6 FPGAs Using Dynamic Partial Reconfiguration
[p. 1542]
 Beerel,
P.A.

An AreaEfficient MultiLevel SingleTrack Pipeline Template
[p. 1509]
 Behrend,
J.

Scalable Hybrid Verification for Embedded Software
[p. 179]
 Bekooij,
M.J.G.

Parallelization of While Loops in Nested Loop Programs for SharedMemory Multiprocessor Systems
[p. 697]

Resynchronization of CycloStatic Dataflow Graphs
[p. 1315]
 Beltrame,
G.

MultiGranularity Thermal Evaluation of 3D MPSoC Architectures
[p. 575]

A MultiObjective DecisionTheoretic Exploration Algorithm for PlatformBased Design
[p. 1192]
 Benini,
L.

An Efficient OnLine Task Allocation Algorithm for QoS and Energy Efficiency in Multicore Multimedia
Platforms
[p. 100]

Design Space Exploration for 3DStacked DRAMs [p. 389]

A FullySynthesizable SingleCycle Interconnection Network for SharedL1 Processor Clusters
[p. 491]

ReliNoC: A Reliable Network for PriorityBased OnChip Communication
[p. 667]

A Distributed and SelfCalibrating ModelPredictive Controller for Energy and Thermal
Management of HighPerformance Multicores
[p. 830]

An Effective MultiSource Energy Harvester for Low Power Applications
[p. 836]
 Beretta,
I.

A HighPerformance Parallel Implementation of the Chambolle Algorithm
[p. 1436]
 Berger,
C.

Formal Specification and Systematic ModelDriven Testing of Embedded Automotive Systems
[p. 118]
 Bergman,
K.

VANDAL: A Tool for the Design Specification of Nanophotonic Networks
[p. 782]
 Berkelaar,
M.

Pseudo Circuit Model for Representing Uncertainty in Waveforms
[p. 1521]
 Bernard,
C.

A LowPower VLIW Processor for 3GPPLTE Complex Numbers Processing
[p. 234]
 Bernardi,
P.

Fault Grading of SoftwareBased SelfTest Procedures for Dependable Automotive Applications
[p. 513]
 Bernicot,
C.

Mathematical Approach Based on a "Design of Experiment" to Simulate Process Variations
[p. 1486]
 Bertacco,
V.

ReliNoC: A Reliable Network for PriorityBased OnChip Communication
[p. 667]
 Bertels,
K.

Loop Distribution for KLoops on Reconfigurable Architectures
[p. 1548]
 Bertozzi,
D.

Exploiting NetworkonChip Structural Redundancy for a Cooperative and Scalable BuiltIn SelfTest Architecture
[p. 661]
 Beserra,
G.S.

SystemLevel Modeling of a MixedSignal System on Chip for Wireless Sensor Networks
[p. 1501]
 Beutel,
J.

XSENSE: Sensing in Extreme Environments
[p. 1460]
 Beyne,
E.

An Analytical Compact Model for Estimation of Stress in Multiple ThroughSilicon Via Configurations
[p. 505]
 Beyranvand Nejad,
A.

An FPGA Bridge Preserving Traffic Quality of Service for OnChip NetworkBased Systems
[p. 425]
 Bhattacharya,
B.B.

WasteAware Dilution and Mixing of Biochemical Samples with Digital Microfluidic Biochips
[p. 1059]
 Bhunia,
S.

HighTemperature (>500°C) Reconfigurable Computing Using Silicon Carbide NEMS Switches
[p. 1065]

MultiLevel Attacks: An Emerging Security Concern for Cryptographic Hardware
[p. 1176]
 Bi,
Y.

Fast Statistical Analysis of RC Nets Subject to Manufacturing Variabilities
[p. 32]
 Bijlsma,
T.

Parallelization of While Loops in Nested Loop Programs for SharedMemory Multiprocessor Systems
[p. 697]
 Bilgic,
A.

Low Power Smart Industrial Control
[p. 595]
 Biswas,
A.

Architectures for Online Error Detection and Recovery in Multicore Processors
[p. 533]
 Blaauw,
D.

Low Power Interconnects for SIMD Computers
[p. 600]

A ConfidenceDriven Model for ErrorResilient Computing
[p. 1608]
 Bocca,
A.

Energy Analysis Methods and Tools For Modelling and Optimizing Tyre Systems
[p. 1121]
 Bock,
S.

Impact of Process Variation on Endurance Algorithms for WearProne Memories
[p. 962]
 Boero,
C.

An Integrated Platform for Advanced Diagnostics
[p. 1454]
 Bogdan,
P.

Sustainability through Massively Integrated Computing: Are We Ready to Break the Energy Efficiency Wall
for SingleChip Platforms?
[p. 1656]
 Boghrati,
B.

A Scaled Random Walk Solver for Fast Power Grid Analysis
[p. 38]
 Bois,
G.

Optical Ring NetworkonChip (ORNoC): Architecture and Design Methodology
[p. 788]
 Bonanno,
A.

Energy Analysis Methods and Tools For Modelling and Optimizing Tyre Systems
[p. 1121]
 Bonhomme,
Y.

Error Prediction Based on Concurrent SelfTest and Reduced Slack Time
[p. 1626]
 Bonnoit,
T.

Eliminating Speed Penalty in ECC Protected Memories
[p. 1614]
 Boos,
V.

Strategies for Initial Sizing and Operating Point Analysis of Analog Circuits
[p. 1672]
 Borhani,
N.

Towards ThermallyAware Design of 3D MPSoCs with InterTier Cooling
[p. 1466]
 Bota,
S.

Stability Optimization of Embedded 8T SRAMs Using WordLine Voltage Modulation
[p. 986]

An Efficient and Scalable STA Tool with Direct Path Estimation and Exhaustive Sensitization Vector
Exploration for Optimal Delay Computation
[p. 1602]
 Brady,
B.A.

CounterexampleGuided SMTDriven Optimal Buffer Sizing
[p. 329]
 Braun,
L.

Fast Startup for Spartan6 FPGAs Using Dynamic Partial Reconfiguration
[p. 1542]
 Bringmann,
O.

Fast and Accurate Resource Conflict Simulation for Performance Analysis of MultiCore Systems
[p. 210]
 Brown,
A.R.

Statistical Aspects of NBTI/PBTI and Impact on SRAM Yield
[p. 1480]
 Brown,
J.

Power Management Trends in Portable Consumer Applications
[p. 1048]
 Brunelli,
D.

An Effective MultiSource Energy Harvester for Low Power Applications
[p. 836]
 Bruns,
F.

Low Power Smart Industrial Control
[p. 595]
 Brunschwiler,
T.

Towards ThermallyAware Design of 3D MPSoCs with InterTier Cooling
[p. 1466]
 Bruschi,
F.

An Efficient QuantumDot Cellular Automata Adder
[p. 1220]
 Buchli,
B.

XSENSE: Sensing in Extreme Environments
[p. 1460]
 Buckl,
C.

A Workflow for Runtime Adaptive Task Allocation on Heterogeneous MPSoCs
[p. 1129]
 Burger,
T.

A Circuit Technology Platform for Medical Data Acquisition and Communication
[p. 1472]
 Buttrick,
M.

On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs
[p. 1418]
 Cabodi,
G.

Interpolation Sequences Revisited
[p. 317]

Optimized Model Checking of Multiple Properties
[p. 543]
 Cacciari,
M.

A Distributed and SelfCalibrating ModelPredictive Controller for Energy and Thermal
Management of HighPerformance Multicores
[p. 830]
 Calhoun,
B.

Reducing the Cost of Redundant Execution in SafetyCritical Systems Using Relaxed Dedication
[p. 1249]
 Calhoun,
B.H.

Dynamic Write Limited Minimum Operating Voltage for Nanoscale SRAMs
[p. 467]
 Calimera,
A.

Partitioned Cache Architectures for Reduced NBTIInduced Aging
[p. 938]
 Moving to Green ICT: From
StandAlone PowerAware IC Design to an Integrated Approach to Energy
Efficient Design of Heterogeneous Electronic Systems [p. 1127]
 Camargo da Costa,
J.

SystemLevel Modeling of a MixedSignal System on Chip for Wireless Sensor Networks
[p. 1501]
 Caprara,
A.

An Efficient OnLine Task Allocation Algorithm for QoS and Energy Efficiency in Multicore Multimedia
Platforms
[p. 100]
 Carara,
E.

Achieving Composability in NoCBased MPSoCs Through QoS Management at Software Level
[p. 407]
 Carli,
D.

An Effective MultiSource Energy Harvester for Low Power Applications
[p. 836]
 Carloni,
L.P.

VANDAL: A Tool for the Design Specification of Nanophotonic Networks
[p. 782]
 Carlsson,
G.

Design Automation for IEEE P1687
[p. 1412]
 Carrara, S.
 An Integrated Platform for
Advanced Diagnostics [p. 1454]
 Carro,
L.

A New Reconfigurable ClockGating Technique for Low Power SRAMBased FPGAs
[p. 752]
 Cassidy,
A.

A HighLevel Analytical Model for Application Specific CMP Design Exploration
[p. 1095]
 Chaix,
F.

A faultTolerant DeadlockFree Adaptive Routing for On Chip Interconnects
[p. 909]
 Chakrabarty,
K.

WasteAware Dilution and Mixing of Biochemical Samples with Digital Microfluidic Biochips
[p. 1059]
 Chakraborty,
K.

Topologically Homogeneous PowerPerformance Heterogeneous Multicore Systems
[p. 125]
 Chakraborty,
R.S.

MultiLevel Attacks: An Emerging Security Concern for Cryptographic Hardware
[p. 1176]
 Chakraborty,
S.

FlexRay Switch Scheduling  A Networking Concept for Electric Vehicles
[p. 76]

ReEngineering CyberPhysical Control Applications for Hybrid Communication Protocols
[p. 914]
 Chan,
J.

VANDAL: A Tool for the Design Specification of Nanophotonic Networks
[p. 782]
 Chan,
T.B.

On the Efficacy of NBTI Mitigation Techniques
[p. 932]
 Chandra,
V.

Dynamic Write Limited Minimum Operating Voltage for Nanoscale SRAMs
[p. 467]

Analytical Model for SRAM Dynamic WriteAbility Degradation Due to Gate Oxide Breakdown
[p. 1172]
 Chang,
C.W.

Formal Reset Recovery Slack Calculation at the Register Transfer Level
[p. 571]
 Chang,
H.M.

An AllDigital BuiltIn SelfTest Technique for Transfer Function Characterization of RF PLLs
[p. 359]
 Chang,
K.H.

Formal Reset Recovery Slack Calculation at the Register Transfer Level
[p. 571]
 Chang,
N.

BatterySupercapacitor Hybrid System for HighRate Pulsed Load Applications
[p. 875]
 Chang,
S.C.

ThermalAware OnLine Task Allocation for 3D MultiCore Processor Throughput Optimization
[p. 8]
 Chang,
X.

Optimization of Stateful Hardware Acceleration in Hybrid Architectures
[p. 567]
 Chen,
C.H.

A ConfidenceDriven Model for ErrorResilient Computing
[p. 1608]
 Chen,
C.I.

Architectural Exploration of 3D FPGAs towards a Better Balance between Area and Delay
[p. 587]
 Chen,
D.

Powering and Communicating with mmsize Implants
[p. 722]
 Chen,
H.M.

On Routing Fixed Escaped Boundary Pins for High Speed Boards
[p. 461]
 Chen,
H.T.

A New Architecture for Power Network in 3D IC
[p. 401]
 Chen,
J.J.

WorstCase Temperature Analysis for RealTime Systems
[p. 631]

BlackBox Leakage Power Modeling for Cell Library and SRAM Compiler
[p. 637]
 Chen,
L.C.

CycleCountAccurate Processor Modeling for Fast and Accurate SystemLevel Simulation
[p. 341]
 Chen,
M.

Decision Ordering Based Property Decomposition for Functional Test Generation
[p. 167]

Diagnosing Scan Chain Timing Faults through Statistical Feature Analysis of Scan Images
[p. 185]
 Chen,
T.

Empirical Design Bugs Prediction for Verification
[p. 161]
 Chen,
X.

Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing
[p. 455]

Evaluating the Potential of Graphics Processors for High Performance Embedded Computing
[p. 709]

Virtual Manycore Platforms: Moving Towards 100+ Processor Cores
[p. 715]
 Chen,
Y.

Empirical Design Bugs Prediction for Verification
[p. 161]

3DICML: A 3D Bipolar ReRAM Design with Interleaved Complementary Memory Layers
[p. 583]

Integrated Circuit White Space Redistribution for Temperature Optimization
[p. 613]
 Chen,
Y.C.

3DICML: A 3D Bipolar ReRAM Design with Interleaved Complementary Memory Layers
[p. 583]
 Chen,
Z.

DataOriented Performance Analysis of SHA3 Candidates on FPGA Accelerated Computers
[p. 1650]
 Chen,
Z.W.

ObstacleAware MultipleSource Rectilinear Steiner Tree with Electromigration and IRDrop Avoidance
[p. 449]

TimingConstrained I/O Buffer Placement for FlipChip Designs
[p. 619]
 Cheng,
B.

Statistical Aspects of NBTI/PBTI and Impact on SRAM Yield
[p. 1480]
 Cheng,
C.K.

A BlockDiagonal Structured Model Reduction Scheme for Power Grid Networks
[p. 44]
 Cheng,
K.T.

An AllDigital BuiltIn SelfTest Technique for Transfer Function Characterization of RF PLLs
[p. 359]
 Chevobbe,
S.

Error Prediction Based on Concurrent SelfTest and Reduced Slack Time
[p. 1626]
 Chiang,
P.

An EnergyEfficient 64QAM MIMO Detector for Emerging Wireless Standards
[p. 246]
 Childers,
B.
 Impact of Process Variation
on Endurance Algorithms for WearProne Memories [p. 962]
 Childers,
B.R.

Demand Code Paging for NAND Flash in MMUless Embedded Systems
[p. 527]
 Chin,
C.Y.

On Routing Fixed Escaped Boundary Pins for High Speed Boards
[p. 461]
 Chinea,
A.

A Parallel Hamiltonian Eigensolver for Passivity Characterization and Enforcement of Large Interconnect
Macromodels
[p. 26]
 Chippa,
V.K.

Design of VoltageScalable Meta Functions for Approximate Computing
[p. 950]
 Chiu,
Y.S.

Pipeline Schedule Synthesis for RealTime Streaming Tasks with Inter/IntraInstance Precedence Constraints
[p. 1321]
 Cho,
D.

I^{2}CRF: Incremental Interconnect Customization for Embedded Reconfigurable Fabrics
[p. 1346]
 Cho,
J.

An Analytical Compact Model for Estimation of Stress in Multiple ThroughSilicon Via Configurations
[p. 505]
 Choi,
M.

An Analytical Compact Model for Estimation of Stress in Multiple ThroughSilicon Via Configurations
[p. 505]
 Chou,
C.L.

FARM: FaultAware Resource Management in NoCBased Multiprocessor Platforms
[p. 673]
 Chou,
P.

Automated Construction of Fast and Accurate SystemLevel Models for Wireless Sensor Networks
[p. 1083]
 Chou,
P.H.

Simplified Programming of Faulty Sensor Networks via Code Transformation and RunTime Interval Computation
[p. 88]
 Choudhury,
M.R.

Reliabilitydriven Don't Care Assignment for Logic Synthesis
[p. 1560]
 Chrysanthou,
N.

Parallel Accelerators for GlimmerHMM Bioinformatics Algorithm
[p. 94]
 Chrysos,
G.

Parallel Accelerators for GlimmerHMM Bioinformatics Algorithm
[p. 94]
 Chung,
C.N.

Formal Reset Recovery Slack Calculation at the Register Transfer Level
[p. 571]
 Chuo,
Y.

2D and 3D Integration with Organic and Silicon Electronics
[p. 899]
 Ciais,
P.

An AntennaFilter CoDesign for Cardiac Implants
[p. 728]
 Ciesielski,
M.

A New Distributed EventDriven GateLevel HDL Simulation by Accurate Prediction
[p. 547]

Temporal Parallel Simulation: A Fast GateLevel HDL Simulation Using Higher Level Models
[p. 1584]
 Cilardo,
A.

The Potential of Reconfigurable Hardware for HPC Cryptanalytic of SHA1
[p. 998]
 Clermidy,
F.

A LowPower VLIW Processor for 3GPPLTE Complex Numbers Processing
[p. 234]

A Low Complexity Stopping Criterion for Reducing Power Consumption in Turbo Decoders
[p. 649]

3D Embedded MultiCore: Some Perspectives
[p. 1327]

Sustainability through Massively Integrated Computing: Are We Ready to Break the Energy Efficiency Wall
for SingleChip Platforms?
[p. 1656]
 Constantinides,
G.

Optimization of Mutually Exclusive Arithmetic SumofProducts
[p. 1388]
 Constantino,
N.

Characterization of an Intelligent Power Switch for LED Driving with Control of Wiring Parasitics Effects
[p. 1119]
 Copty,
S.

A Unified Methodology for PreSilicon Verification and PostSilicon Validation
[p. 1590]
 Corporaal,
H.

Parallelization of While Loops in Nested Loop Programs for SharedMemory Multiprocessor Systems
[p. 697]

A 0.964mW Digital Hearing Aid System
[p. 883]

Resynchronization of CycloStatic Dataflow Graphs
[p. 1315]
 Crop,
J.

An EnergyEfficient 64QAM MIMO Detector for Emerging Wireless Standards
[p. 246]
 D'Abramo,
P.

Characterization of an Intelligent Power Switch for LED Driving with Control of Wiring Parasitics Effects
[p. 1119]
 D'Orazio,
L.

Sensor Networks on the Car: State of the Art and Future Challenges
[p. 1030]
 Damm,
W.

Using ContractBased Component Specifications for Virtual Integration Testing and Architecture Design
[p. 1023]
 Danger,
J.L.

Enhancement of Simple ElectroMagnetic Attacks by PreCharacterization in Frequency Domain and
Demodulation Techniques
[p. 1004]
 Danowitz,
A.

Intermediate Representations for Controllers in Chip Generators
[p. 1394]
 Dantara,
D.

SHARC: A Streaming Model for FPGA Accelerators and its Application to Saliency
[p. 1237]
 Darin,
M.

Sensor Networks on the Car: State of the Art and Future Challenges
[p. 1030]
 Darringer,
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Early Chip Planning Cockpit
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3D Embedded MultiCore: Some Perspectives
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 Dash,
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Circuit and DFT Techniques for Robust and Low Cost Qualification of a MixedSignal SoC with Integrated
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[p. 551]
 David,
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An AntennaFilter CoDesign for Cardiac Implants
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 Davis,
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An EnergyEfficient 64QAM MIMO Detector for Emerging Wireless Standards
[p. 246]
 Davoodi,
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PowerDriven Global Routing for MultiSupply Voltage Domains
[p. 443]
 de Foucauld,
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An AntennaFilter CoDesign for Cardiac Implants
[p. 728]
 de Lamotte,
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Dynamic Applications on Reconfigurable Systems: From UML Model Design to FPGAs Implementation
[p. 1208]
 de Medeiros,
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SystemLevel Modeling of a MixedSignal System on Chip for Wireless Sensor Networks
[p. 1501]
 De Meyer,
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An Analytical Compact Model for Estimation of Stress in Multiple ThroughSilicon Via Configurations
[p. 505]
 De Micheli,
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Logic synthesis and Physical Design: Quo Vadis [p. 51]

Analytical Heat Transfer Model for Thermal ThroughSilicon Vias
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An Integrated Platform for Advanced Diagnostics
[p. 1454]
 De Wit,
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Analog Circuit Reliability in Sub32 Nanometer CMOS: Analysis and Mitigation
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 Dehollain,
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A Circuit Technology Platform for Medical Data Acquisition and Communication
[p. 1472]
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Power Optimization in Heterogenous Datapaths
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 Delaveaud,
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An AntennaFilter CoDesign for Cardiac Implants
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 Demir,
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SAMURAI: An Accurate Method for Modeling and Simulating NonStationary Random Telegraph Noise in SRAMs
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 Deng,
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EnergyEfficient Scheduling of RealTime Tasks on ClusterBased Multicores
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 Deng,
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Evaluating the Potential of Graphics Processors for High Performance Embedded Computing
[p. 709]
 Deng,
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Scalable Packet Classification via GPU Metaprogramming
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 Desoli,
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An Efficient OnLine Task Allocation Algorithm for QoS and Energy Efficiency in Multicore Multimedia
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[p. 100]
 Dey,
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VESPA: Variability Emulation for SystemonChip Performance Analysis
[p. 2]
 Dick,
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Simplified Programming of Faulty Sensor Networks via Code Transformation and RunTime
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[p. 88]

Integrated Circuit White Space Redistribution for Temperature Optimization
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Automated Construction of Fast and Accurate SystemLevel Models for Wireless Sensor Networks
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 Diguet,
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Dynamic Applications on Reconfigurable Systems: From UML Model Design to FPGAs Implementation
[p. 1208]
 Dinda,
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Simplified Programming of Faulty Sensor Networks via Code Transformation and RunTime
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[p. 88]
 Automated Construction of
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A Symbolic Technique for Automated Characterization of the Uniqueness and Similarity of Analog Circuit
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[p. 1212]
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Variability Aware Modeling for Yield Enhancement of SRAM and Logic
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An EnergyEfficient 3D CMP Design with FineGrained Voltage Scaling
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Design Implications of MemristorBased RRAM CrossPoint Structures
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Fast and Accurate TransactionLevel Model of a Wormhole NetworkonChip with Priority Preemptive
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 Dragomir,
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Loop Distribution for KLoops on Reconfigurable Architectures
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Optimization of Mutually Exclusive Arithmetic SumofProducts
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Verifying Dynamic Aspects of UML Models
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Determining the Minimal Number of Lines for Large Reversible Circuits
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AsRobustAsPossible Test Generation in the Presence of Small Delay Defects Using PseudoBoolean
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Low Power Interconnects for SIMD Computers
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Challenges in Designing High Speed Memory Subsystem for Mobile Applications
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STABLE: A New QFBV SMT Solver for Hard Verification Problems combining Boolean Reasoning with Computer Algebra
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Multidimensional Parametric Test Set Optimization of Wafer Probe Data for Predicting in Field Failures and
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An Electrical Test Method for MEMS Convective Accelerometers: Development and Evaluation
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Smart Imagers of the Future
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3D Embedded MultiCore: Some Perspectives
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SlackAware Scheduling on Coarse Grained Reconfigurable Arrays
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ERoC: Embedded RaidsonChip for Low Power Distributed Dynamically Managed Reliable Memories
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Systematic Design of a Programmable LowNoise CMOS Neural Interface for Cell Activity Recording
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ScTMR: A Scan ChainBased Error Recovery Technique for TMR Systems in SafetyCritical Applications
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Virtual Manycore Platforms: Moving Towards 100+ Processor Cores
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AsRobustAsPossible Test Generation in the Presence of Small Delay Defects Using PseudoBoolean
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A Reconfigurable, Pipelined, Conflict Directed Jumping Search SAT Solver
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An Analytical Compact Model for Estimation of Stress in Multiple ThroughSilicon Via Configurations
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Energy Parsimonious Circuit Design through Probabilistic Pruning
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A Method for Fast Jitter Tolerance Analysis of HighSpeed PLLs
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An FPGA Bridge Preserving Traffic Quality of Service for OnChip NetworkBased Systems
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Error Prediction Based on Concurrent SelfTest and Reduced Slack Time
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A New Reconfigurable ClockGating Technique for Low Power SRAMBased FPGAs
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A RuleBased Static Dataflow Clustering Algorithm for Efficient Embedded Software Synthesis
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Solid State Photodetectors for Nuclear Medical Imaging Applications
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Lowcost Fault Detection Method for ECC Using Montgomery Powering Ladder
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BlackBox Leakage Power Modeling for Cell Library and SRAM Compiler
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A Sensor Fusion Algorithm for an Integrated Angular Position Estimation with Inertial
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Characterization of an Intelligent Power Switch for LED Driving with Control of Wiring Parasitics Effects
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Exploiting NetworkonChip Structural Redundancy for a Cooperative and Scalable BuiltIn SelfTest Architecture
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Soft Error Rate Estimation of Digital Circuits in the Presence of Multiple Event Transients (METs)
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A Symbolic Technique for Automated Characterization of the Uniqueness and Similarity of Analog Circuit
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Fast Statistical Analysis of RC Nets Subject to Manufacturing Variabilities
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XSENSE: Sensing in Extreme Environments
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 Entering the Path towards
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Guaranteed Service Virtual Channel Allocation in NoCs for RunTime Task Scheduling
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Solid State Photodetectors for Nuclear Medical Imaging Applications
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Robustness Analysis of 6T SRAMs in Memory Retention Mode under PVT Variations
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Enhancement of Simple ElectroMagnetic Attacks by PreCharacterization in Frequency Domain and
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SubClock PowerGating Technique for Minimising Leakage Power During Active Mode
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Correlating Models and Silicon for Improved Parametric Yield
[p. 1159]
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A True Power Detector for RF PA BuiltIn Calibration and Testing
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MultiGranularity Thermal Evaluation of 3D MPSoC Architectures
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Speedingup SIMD Instructions Dynamic Binary Translation in Embedded Processor Simulation
[p. 277]
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Optimization of Stateful Hardware Acceleration in Hybrid Architectures
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A SharedVariableBased Synchronization Approach to Efficient Cache Coherence Simulation for MultiCore
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[p. 347]
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An Algorithm to Improve Accuracy of Criticality in Statistical Static Timing Analysis
[p. 1529]
 Funchal,
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jTLM: An Experimentation Framework for the Simulation of TransactionLevel Models of SystemsonChip
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BiologicallyInspired MassivelyParallel Architectures
 Computing Beyond A Million Processors
[p. 1]

Modeling Circuit Performance Variations Due to Statistical Variability: Monte Carlo Static Timing Analysis
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TransitionTimeRelation Based CaptureSafety Checking for AtSpeed Scan Test Generation
[p. 895]
 Gangemi,
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Moving to Green ICT: From StandAlone PowerAware IC Design to an Integrated Approach to Energy
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 Ganguly,
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Sustainability through Massively Integrated Computing: Are We Ready to Break the Energy Efficiency Wall
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 Gao,
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Eliminating Data Invalidation in Debugging MultipleClock Chips
[p. 691]
 Garg,
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Statistical Thermal Evaluation and Mitigation Techniques for 3D ChipMultiprocessors in the Presence of
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[p. 383]
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Reducing the Cost of Redundant Execution in SafetyCritical Systems Using Relaxed Dedication
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 Gerding,
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Low Power Smart Industrial Control
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 German,
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Formal Specification and Systematic ModelDriven Testing of Embedded Automotive Systems
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 Gerstlauer,
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HostCompiled Multicore RTOS Simulator for Embedded RealTime Software Development
[p. 222]

Controlled TimingError Acceptance for Low Energy IDCT Design
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 Geuns,
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Parallelization of While Loops in Nested Loop Programs for SharedMemory Multiprocessor Systems
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SoC Infrastructures for Predictable System Integration
[p. 857]
 Ghasemazar,
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Variation Aware Dynamic Power Management for Chip Multiprocessor Architectures
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 Gherman,
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Error Prediction Based on Concurrent SelfTest and Reduced Slack Time
[p. 1626]
 Ghoreishizadeh,
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An Integrated Platform for Advanced Diagnostics
[p. 1454]
 Gielen,
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Systematic Design of a Programmable LowNoise CMOS Neural Interface for Cell Activity Recording
[p. 818]

Global Optimization of Integrated Transformers for High Frequency Microwave Circuits Using a Gaussian
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[p. 1101]

Stochastic Circuit Reliability Analysis
[p. 1285]

Analog Circuit Reliability in Sub32 Nanometer CMOS: Analysis and Mitigation
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 Gil,
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Fast Startup for Spartan6 FPGAs Using Dynamic Partial Reconfiguration
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Scratchpad Memory Optimizations for Digital Signal Processing Applications
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An Efficient and Scalable STA Tool with Direct Path Estimation and Exhaustive Sensitization Vector
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[p. 1602]
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Improving the Efficiency of a Hardware Transactional Memory on an NoCbased MPSoC
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 Girault,
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Pruning Infeasible Paths for Tight WCRT Analysis of Synchronous Programs
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 Gizopoulos, D.
 Architectures for Online
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 Gobbato,
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A Parallel Hamiltonian Eigensolver for Passivity Characterization and Enforcement of Large Interconnect
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 Gogniat,
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Dynamic Applications on Reconfigurable Systems: From UML Model Design to FPGAs Implementation
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 Golani,
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An AreaEfficient MultiLevel SingleTrack Pipeline Template
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Exploiting NetworkonChip Structural Redundancy for a Cooperative and Scalable BuiltIn SelfTest Architecture
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M.E.

Exploiting NetworkonChip Structural Redundancy for a Cooperative and Scalable BuiltIn SelfTest Architecture
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An FPGA Bridge Preserving Traffic Quality of Service for OnChip NetworkBased Systems
[p. 425]

Architectures and Modeling of Predictable Memory Controllers for Improved System Integration
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Optimal Scheduling of Switched FlexRay Networks
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ReEngineering CyberPhysical Control Applications for Hybrid Communication Protocols
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Powering and Communicating with mmsize Implants
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Efficient RC Power Grid Verification Using Node Elimination
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 Grammatikakis,
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SystemLevel Power Estimation Methodology Using Cycle and BitAccurate TLM
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Generator Based Approach for Analog Circuit and Layout Design and Optimization
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 Gray,
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Two Methods for 24 Gbps Test Signal Synthesis
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NoCMPU: A Secure Architecture for Flexible CoHosting on Shared Memory MPSoCs
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 Greuel,
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STABLE: A New QFBV SMT Solver for Hard Verification Problems combining Boolean Reasoning with Computer Algebra
[p. 155]
 Grimm,
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RealTime Wireless Communication in Automotive Applications
[p. 1036]

Wireless Communication and Energy Harvesting in Automobiles
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Simulation Based Tuning of System Specification
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 Grimm,
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Strategies for Initial Sizing and Operating Point Analysis of Analog Circuits
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 GrivetTalocia,
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A Parallel Hamiltonian Eigensolver for Passivity Characterization and Enforcement of Large Interconnect
Macromodels
[p. 26]
 Grosso,
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Fault Grading of SoftwareBased SelfTest Procedures for Dependable Automotive Applications
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 Guderian,
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Entering the Path towards Terabit/s Wireless Links
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 Guillet, S.
 Dynamic Applications on
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 Guilley,
S.

Enhancement of Simple ElectroMagnetic Attacks by PreCharacterization in Frequency Domain and
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[p. 1004]
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Empirical Design Bugs Prediction for Verification
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 Guo,
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DataOriented Performance Analysis of SHA3 Candidates on FPGA Accelerated Computers
[p. 1650]
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VariabilityAware Duty Cycle Scheduling in Long Running Embedded Sensing Systems
[p. 131]

On the Efficacy of NBTI Mitigation Techniques
[p. 932]

Case Study: Alleviating Hotspots and Improving Chip Reliability via Carbon Nanotube Thermal Interface
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 Gupta,
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Understanding the Role of Buildings in a Smart Microgrid
[p. 1224]
 Gupta,
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Testing of HighSpeed DACs Using PRBS Generation with "AlternateBitTapping"
[p. 377]
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A New Circuit Simplification Method for Error Tolerant Applications
[p. 1566]
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RealTime Wireless Communication in Automotive Applications
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 Simulation Based Tuning of
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 Hamdioui,
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CostEfficient FaultTolerant Decoder for Hybrid Nanoelectronic Memories
[p. 265]
 Hameed,
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Dynamic Thermal Management in 3D MultiCore Architecture through RunTime Adaptation
[p. 299]
 Han,
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Clause Simplification through Dominator Analysis
[p. 143]
 Han,
Y.

Eliminating Data Invalidation in Debugging MultipleClock Chips
[p. 691]
 FlexMemory: Exploiting and
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 Hanumaiah,
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Reliabilityaware Thermal Management for Hard Realtime Applications on Multicore Processors
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 Hanyu,
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InterconnectFaultResilient DelayInsensitive Asynchronous Communication Link Based on CurrentFlow
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[p. 776]
 Hari,
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Architectures for Online Error Detection and Recovery in Multicore Processors
[p. 533]
 Haron,
N.Z.

CostEfficient FaultTolerant Decoder for Hybrid Nanoelectronic Memories
[p. 265]
 Hashempour,
H.

Test Time Reduction in Analogue/MixedSignal Devices by Defect Oriented Testing: An Industrial Example
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 Haubelt,
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A RuleBased Static Dataflow Clustering Algorithm for Efficient Embedded Software Synthesis
[p. 521]
 Hausmans,
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Resynchronization of CycloStatic Dataflow Graphs
[p. 1315]
 Hayes,
J.P.

Trigonometric Method to Handle Realistic Error Probabilities in Logic Circuits
[p. 64]
 He,
K.

Controlled TimingError Acceptance for Low Energy IDCT Design
[p. 758]
 He,
Y.

Global Optimization of Integrated Transformers for High Frequency Microwave Circuits Using a Gaussian
Process Based Surrogate Model
[p. 1101]
 Healy,
M.B.

A Novel TSV Topology for ManyTier 3D PowerDelivery Networks
[p. 261]
 Heckeler,
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Scalable Hybrid Verification for Embedded Software
[p. 179]
 Hedrich,
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Automated ConstraintDriven Topology Synthesis for Analog Circuits
[p. 1662]
 Heidmann,
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Architecture and FPGAImplementation of a High Throughput K^{+}Best Detector
[p. 240]
 Hemani,
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Predicting Bus Contention Effects on Energy and Performance in MultiProcessor SoCs
[p. 1196]
 Hendry,
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VANDAL: A Tool for the Design Specification of Nanophotonic Networks
[p. 782]
 Henkel,
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Dynamic Thermal Management in 3D MultiCore Architecture through RunTime Adaptation
[p. 299]

CARAT: ContextAware Runtime Adaptive Task Migration for Multi Core Architectures
[p. 515]

MinorityGameBased Resource Allocation for RunTime Reconfigurable MultiCore Processors
[p. 1261]

MultiLevel Pipelined Parallel Hardware Architecture for High Throughput Motion and Disparity Estimation
in Multiview Video Coding
[p. 1448]

mRTS: RunTime System for Reconfigurable Processors with MultiGrained InstructionSet Extensions
[p. 1554]
 Henker,
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Strategies for Initial Sizing and Operating Point Analysis of Analog Circuits
[p. 1672]
 Hennig,
E.

A New Method for Automated Generation of Compensation Networks  The EDA Designer Finger
[p. 1666]
 Herkersdorf,
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An Approach to Improve Accuracy of SourceLevel TLMs of Embedded Software
[p. 216]
 Hermida,
R.

Power Optimization in Heterogenous Datapaths
[p. 1400]
 Herndl,
T.

RealTime Wireless Communication in Automotive Applications
[p. 1036]
 Hielscher,
K.S.

Formal Specification and Systematic ModelDriven Testing of Embedded Automotive Systems
[p. 118]
 Hill,
S.

SubClock PowerGating Technique for Minimising Leakage Power During Active Mode
[p. 106]
 Ho,
Y.L.

ThermalAware OnLine Task Allocation for 3D MultiCore Processor Throughput Optimization
[p. 8]
 Hoffmann,
T.

An Analytical Compact Model for Estimation of Stress in Multiple ThroughSilicon Via Configurations
[p. 505]
 Holcomb,
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CounterexampleGuided SMTDriven Optimal Buffer Sizing
[p. 329]
 Homma,
N.

Enhancement of Simple ElectroMagnetic Attacks by PreCharacterization in Frequency Domain and
Demodulation Techniques
[p. 1004]
 Honkote,
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Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing
[p. 455]
 Höppner,
S.

Strategies for Initial Sizing and Operating Point Analysis of Analog Circuits
[p. 1672]
 Hora,
C.

Test Time Reduction in Analogue/MixedSignal Devices by Defect Oriented Testing: An Industrial Example
[p. 371]
 Horiuchi,
K.

An LOCVBased Static Timing Analysis Considering Spatial Correlations of Power Supply Variations
[p. 559]
 Horowitz,
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Intermediate Representations for Controllers in Chip Generators
[p. 1394]
 Hou,
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Optimization of Stateful Hardware Acceleration in Hybrid Architectures
[p. 567]
 Hsiao,
M.S.

DesignforTest Methodology for NonScan AtSpeed Testing
[p. 191]
 Hsu,
S.J.

Clock Gating Optimization with DelayMatching
[p. 643]
 Hu,
J.

Towards Energy Efficient Hybrid OnChip Scratch Pad Memory with NonVolatile Memory
[p. 746]
 Hu,
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Empirical Design Bugs Prediction for Verification
[p. 161]
 Hu,
X.

A BlockDiagonal Structured Model Reduction Scheme for Power Grid Networks
[p. 44]

A CostEffective SubstantialImpactFilter Based Method to Tolerate Voltage Emergencies
[p. 311]
 Hu,
Y.

CrossLayer Optimized Placement and Routing for FPGA Soft Error Mitigation
[p. 58]

A CostEffective SubstantialImpactFilter Based Method to Tolerate Voltage Emergencies
[p. 311]

On Diagnosis of Multiple Faults Using Compressed Responses
[p. 679]
 Huang,
C.Y.

Speeding up MPSoC Virtual Platform Simulation by Ultra Synchronization Checking Method
[p. 353]
 Huang,
H.

Leakage Aware Energy Minimization for RealTime Systems under the Maximum Temperature Constraint
[p. 479]
 Huang,
J.

Case Study: Alleviating Hotspots and Improving Chip Reliability via Carbon Nanotube Thermal Interface
[p. 1071]

A Workflow for Runtime Adaptive Task Allocation on Heterogeneous MPSoCs
[p. 1129]
 Huang,
J.D.

Architectural Exploration of 3D FPGAs towards a Better Balance between Area and Delay
[p. 587]
 Huang,
K.

CrossLayer Optimized Placement and Routing for FPGA Soft Error Mitigation
[p. 58]
 Huang,
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A Specialized LowCost Vectorized Loop Buffer for Embedded Processors
[p. 1200]
 Huang,
Q.

A Circuit Technology Platform for Medical Data Acquisition and Communication
[p. 1472]
 Huang,
S.Y.

BlackBox Leakage Power Modeling for Cell Library and SRAM Compiler
[p. 637]
 Hübner,
M.

Fast Startup for Spartan6 FPGAs Using Dynamic Partial Reconfiguration
[p. 1542]
 Hung,
S.H.

Pipeline Schedule Synthesis for RealTime Streaming Tasks with Inter/IntraInstance Precedence Constraints
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 Hungar,
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Using ContractBased Component Specifications for Virtual Integration Testing and Architecture Design
[p. 1023]
 Hunter,
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Power Management Verification Experiences in Wireless SoCs
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 Hwang,
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A New Architecture for Power Network in 3D IC
[p. 401]
 Indrusiak,
L.S.

Fast and Accurate TransactionLevel Model of a Wormhole NetworkonChip with Priority Preemptive
Virtual Channel Arbitration
[p. 1089]
 Ingelsson,
U.

Design Automation for IEEE P1687
[p. 1412]
 Ishihara,
T.

Developing an Integrated Verification and Debug Methodology
[p. 503]
 Jahn,
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CARAT: ContextAware Runtime Adaptive Task Migration for Multi Core Architectures
[p. 515]
 Jancke,
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Generator Based Approach for Analog Circuit and Layout Design and Optimization
[p. 1675]
 Jerraya,
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A 3D Reconfigurable Platform for 4G Telecom Applications
[p. 555]
 Jezequel,
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A Flexible High Throughput MultiASIP Architecture for LDPC and Turbo Decoding
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A Low Complexity Stopping Criterion for Reducing Power Consumption in Turbo Decoders
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 Jha,
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When to Stop Verification? Statistical TradeOff between Expected Loss and Simulation Cost
[p. 1309]
 Ji,
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Floorplanning Exploration and Performance Evaluation of a New NetworkonChip
[p. 625]
 Jin,
H.

Clause Simplification through Dominator Analysis
[p. 143]
 Johnson,
C.L.

Early Chip Planning Cockpit
[p. 863]
 Jores,
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Automated ConstraintDriven Topology Synthesis for Analog Circuits
[p. 1662]
 Joseph,
R.

Efficient Parameter Variation Sampling for Architecture Simulations
[p. 1578]
 Josko,
B.

Using ContractBased Component Specifications for Virtual Integration Testing and Architecture Design
[p. 1023]
 Jouppi,
N.P.

Design Implications of MemristorBased RRAM CrossPoint Structures
[p. 734]
 Juan,
D.C.

Statistical Thermal Evaluation and Mitigation Techniques for 3D ChipMultiprocessors in the Presence of
Process Variations
[p. 383]
 Jung,
H.

A Quantitative Analysis of Performance Benefits of 3D Die Stacking on Mobile and Embedded SoC
[p. 1333]
 Jung,
J.

I^{2}CRF: Incremental Interconnect Customization for Embedded Reconfigurable Fabrics
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 Kajihara,
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TransitionTimeRelation Based CaptureSafety Checking for AtSpeed Scan Test Generation
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 Kajitani,
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On Routing Fixed Escaped Boundary Pins for High Speed Boards
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A FullySynthesizable SingleCycle Interconnection Network for SharedL1 Processor Clusters
[p. 491]

ReliNoC: A Reliable Network for PriorityBased OnChip Communication
[p. 667]
 Kamal,
M.

Timing VariationAware Custom Instruction Extension Technique
[p. 1517]
 Kaminska,
B.

2D and 3D Integration with Organic and Silicon Electronics
[p. 899]
 Kang,
K.

Scalable Packet Classification via GPU Metaprogramming
[p. 871]
 Kanoun,
K.

A RealTime Compressed SensingBased Personal Electrocardiogram Monitoring System
[p. 824]
 Kapoor,
B.

Power Management Verification Experiences in Wireless SoCs
[p. 507]
 Karaklajic,
D.

Lowcost Fault Detection Method for ECC Using Montgomery Powering Ladder
[p. 1016]
 Katevenis,
M.

FineGrain OpenMP Runtime Support with Explicit Communication Hardware Primitives
[p. 891]
 Kauppinen,
H.

Wireless Innovations for Smartphones
[p. 606]
 Kavadias,
S.

FineGrain OpenMP Runtime Support with Explicit Communication Hardware Primitives
[p. 891]
 Kazmierski,
T.

Wireless Communication and Energy Harvesting in Automobiles
[p. 1042]
 Kazmierski,
T.J.

Accelerated Simulation of Tunable Vibration Energy Harvesting Systems Using a Linearised StateSpace
Technique
[p. 1267]

An Extension to SystemCA to Support MixedTechnology Systems with Distributed Components
[p. 1279]
 Keezer,
D.C.

Two Methods for 24 Gbps Test Signal Synthesis
[p. 579]
 Keller,
M.

XSENSE: Sensing in Extreme Environments
[p. 1460]
 Kelley,
K.

Intermediate Representations for Controllers in Chip Generators
[p. 1394]
 Keng,
B.

Automated Debugging of SystemVerilog Assertions
[p. 323]
 Kern,
A.

An Automated Data Structure Migration Concept  From CAN to Ethernet/IP in Automotive Embedded
Systems (CANoverIP)
[p. 112]
 Kershaw,
D.

Low Power Interconnects for SIMD Computers
[p. 600]
 Kestur,
S.

SHARC: A Streaming Model for FPGA Accelerators and its Application to Saliency
[p. 1237]
 Keszöcze,
O.

Determining the Minimal Number of Lines for Large Reversible Circuits
[p. 1204]
 Khaled,
N.

A RealTime Compressed SensingBased Personal Electrocardiogram Monitoring System
[p. 824]
 Khan,
G.N.

MultiObjective Tabu Search Based Topology Generation Technique for ApplicationSpecific NetworkonChip Architectures
[p. 485]
 Khatib,
M.G.

Buffering Implications for the Design Space of Streaming MEMS Storage
[p. 253]
 Kim,
D.

A New Distributed EventDriven GateLevel HDL Simulation by Accurate Prediction
[p. 547]

A Quantitative Analysis of Performance Benefits of 3D Die Stacking on Mobile and Embedded SoC
[p. 1333]

Temporal Parallel Simulation: A Fast GateLevel HDL Simulation Using Higher Level Models
[p. 1584]
 Kim,
N.S.

Time Redundant Parity for LowCost Transient Error Detection
[p. 52]

Scratchpad Memory Optimizations for Digital Signal Processing Applications
[p. 974]
 Kim,
Y.

BatterySupercapacitor Hybrid System for HighRate Pulsed Load Applications
[p. 875]

I^{2}CRF: Incremental Interconnect Customization for Embedded Reconfigurable Fabrics
[p. 1346]

A ConfidenceDriven Model for ErrorResilient Computing
[p. 1608]
 Klobedanz,
K.

A Reconfiguration Approach for FaultTolerant FlexRay Networks
[p. 82]
 Knoll,
A.

A Workflow for Runtime Adaptive Task Allocation on Heterogeneous MPSoCs
[p. 1129]
 Priority Division: A
HighSpeed SharedMemory Bus Arbitration with Bounded Latency [p. 1497]
 Kobayashi,
S.

An LOCVBased Static Timing Analysis Considering Spatial Correlations of Power Supply Variations
[p. 559]
 Koch,
A.

MARC II: A Parametrized Speculative MultiPorted Memory Subsystem for Reconfigurable Computers
[p. 1352]
 Kochte,
M.A.

SATBased Fault Coverage Evaluation in the Presence of Unknown Values
[p. 1303]
 Koenig,
A.

A Reconfiguration Approach for FaultTolerant FlexRay Networks
[p. 82]
 Kolpe,
T.

Enabling Improved Power Management in Multicore Processors through Clustered DVFS
[p. 293]
 Kondratyev,
A.

Realistic PerformanceConstrained Pipelining in HighLevel Synthesis
[p. 1382]
 Kong,
F.

EnergyEfficient Scheduling of RealTime Tasks on ClusterBased Multicores
[p. 1135]
 Koushanfar,
F.

HypoEnergy: Hybrid SupercapacitorBattery PowerSupply Optimization for Energy Efficiency
[p. 887]
 Kozhikkottu,
V.

VESPA: Variability Emulation for SystemonChip Performance Analysis
[p. 2]
 Krause,
P.K.

Adaptive Voltage OverScaling for Resilient Applications
[p. 944]
 Krausse,
D.

A New Method for Automated Generation of Compensation Networks  The EDA Designer Finger
[p. 1666]

Strategies for Initial Sizing and Operating Point Analysis of Analog Circuits
[p. 1672]
 Krishna,
A.

HighTemperature (>500°C) Reconfigurable Computing Using Silicon Carbide NEMS Switches
[p. 1065]
 Krone,
S.

Entering the Path towards Terabit/s Wireless Links
[p. 431]
 Kropf,
T.

Scalable Hybrid Verification for Embedded Software
[p. 179]
 Kruseman,
B.

Test Time Reduction in Analogue/MixedSignal Devices by Defect Oriented Testing: An Industrial Example
[p. 371]
 Kuan,
C.Y.

On Routing Fixed Escaped Boundary Pins for High Speed Boards
[p. 461]
 Kudari,
A.D.

Circuit and DFT Techniques for Robust and Low Cost Qualification of a MixedSignal SoC with Integrated
Power Management System
[p. 551]
 Kuehlmann,
A.

An Approach for Dynamic Selection of Synthesis Transformations Based on Markov Decision Processes
[p. 1533]
 Kumar,
A.

HyperGraph Based Partitioning to Reduce DFT Cost for PreBond 3DIC Testing
[p. 1424]
 Kumar,
R.

On the Efficacy of NBTI Mitigation Techniques
[p. 932]
 Kundu,
S.

On Design of Test Structures for Lithographic Process Corner Identification
[p. 800]

Modeling Manufacturing Process Variation for Design and Test
[p. 1147]

On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs
[p. 1418]

Physically Unclonable Functions for Embedded Security Based on Lithographic Variation
[p. 1632]
 Kunz, L.
 Improving the Efficiency of
a Hardware Transactional Memory on an NoCbased MPSoC [p. 1168]
 Kunz,
W.

STABLE: A New QFBV SMT Solver for Hard Verification Problems combining Boolean Reasoning with Computer Algebra
[p. 155]
 Kuo,
S.Y.

Formal Reset Recovery Slack Calculation at the Register Transfer Level
[p. 571]
 Kupp,
N.

Correlating Inline Data with Final Test Outcomes in Analog/RF Devices
[p. 812]
 Kwai,
D.M.

ThermalAware OnLine Task Allocation for 3D MultiCore Processor Throughput Optimization
[p. 8]
 Kyrkou,
C.

DepthDirected Hardware Object Detection
[p. 1442]
 Lach,
J.

Reducing the Cost of Redundant Execution in SafetyCritical Systems Using Relaxed Dedication
[p. 1249]
 Lafi,
W.

A 3D Reconfigurable Platform for 4G Telecom Applications
[p. 555]

3D Embedded MultiCore: Some Perspectives
[p. 1327]
 Lampka,
K.

Composing Heterogeneous Components for SystemWide Performance Analysis
[p. 842]
 Landa,
S.

A Unified Methodology for PreSilicon Verification and PostSilicon Validation
[p. 1590]
 Landrock,
C.K.

2D and 3D Integration with Organic and Silicon Electronics
[p. 899]
 Lange,
H.

MARC II: A Parametrized Speculative MultiPorted Memory Subsystem for Reconfigurable Computers
[p. 1352]
 Langmead,
C.J.

When to Stop Verification? Statistical TradeOff between Expected Loss and Simulation Cost
[p. 1309]
 Larsson,
E.

Design Automation for IEEE P1687
[p. 1412]
 Lattard,
D.

A 3D Reconfigurable Platform for 4G Telecom Applications
[p. 555]
 Lavagno,
L.

Realistic PerformanceConstrained Pipelining in HighLevel Synthesis
[p. 1382]
 Le Beux,
S.

Optical Ring NetworkonChip (ORNoC): Architecture and Design Methodology
[p. 788]
 Leblebici,
Y.

Towards ThermallyAware Design of 3D MPSoCs with InterTier Cooling
[p. 1466]
 Lee,
B.C.

Architectural Exploration of 3D FPGAs towards a Better Balance between Area and Delay
[p. 587]
 Lee,
E.A.

ComponentBased Design for the Future
[p. 1029]
 Lee,
J.

I^{2}CRF: Incremental Interconnect Customization for Embedded Reconfigurable Fabrics
[p. 1346]
 Lee,
R.J.

On Routing Fixed Escaped Boundary Pins for High Speed Boards
[p. 461]
 Lee,
S.

A Novel Tag Access Scheme for Low Power L2 Cache
[p. 655]

A Quantitative Analysis of Performance Benefits of 3D Die Stacking on Mobile and Embedded SoC
[p. 1333]
 Lee,
T.H.

HighTemperature (>500°C) Reconfigurable Computing Using Silicon Carbide NEMS Switches
[p. 1065]
 Lee,
Y.H.

Timing Error Statistics for EnergyEfficient Robust DSP Systems
[p. 285]
 Lettnin,
D.

Scalable Hybrid Verification for Embedded Software
[p. 179]
 Leupers,
R.

Virtual Manycore Platforms: Moving Towards 100+ Processor Cores
[p. 715]
 Li,
D.

Evaluating the Potential of Graphics Processors for High Performance Embedded Computing
[p. 709]
 Li,
H.

3DICML: A 3D Bipolar ReRAM Design with Interleaved Complementary Memory Layers
[p. 583]

FlexMemory: Exploiting and Managing Abundant OffChip Optical Bandwidth
[p. 968]
 Li,
L.

Proactive Recovery for BTI in HighK SRAM Cells
[p. 992]
 Li,
M.

Register Allocation for Simultaneous Reduction of Energy and Peak Temperature on Registers
[p. 20]

Challenges in Designing High Speed Memory Subsystem for Mobile Applications
[p. 509]
 Li,
X.

CrossLayer Optimized Placement and Routing for FPGA Soft Error Mitigation
[p. 58]

A CostEffective SubstantialImpactFilter Based Method to Tolerate Voltage Emergencies
[p. 311]

On Diagnosis of Multiple Faults Using Compressed Responses
[p. 679]

Eliminating Data Invalidation in Debugging MultipleClock Chips
[p. 691]

FlexMemory: Exploiting and Managing Abundant OffChip Optical Bandwidth
[p. 968]
 Li,
Y.

Redressing Timing Issues for SpeedIndependent Circuits in Deep Submicron Age
[p. 1376]
 Lim,
S.K.

A Novel TSV Topology for ManyTier 3D PowerDelivery Networks
[p. 261]
 Lin,
H.C.

Speeding up MPSoC Virtual Platform Simulation by Ultra Synchronization Checking Method
[p. 353]
 Lin,
H.L.

A New Architecture for Power Network in 3D IC
[p. 401]
 Lin,
R.B.

Clock Gating Optimization with DelayMatching
[p. 643]
 Linderoth,
J.T.

PowerDriven Global Routing for MultiSupply Voltage Domains
[p. 443]
 Lindwer,
M.

A 0.964mW Digital Hearing Aid System
[p. 883]
 Lingamneni,
A.

Energy Parsimonious Circuit Design through Probabilistic Pruning
[p. 764]
 Lipasti,
M.H.

Time Redundant Parity for LowCost Transient Error Detection
[p. 52]
 Liu,
B.

Global Optimization of Integrated Transformers for High Frequency Microwave Circuits Using a Gaussian
Process Based Surrogate Model
[p. 1101]
 Liu,
C.

A ClockGating Based Capture Power Droop Reduction Methodology for AtSpeed Scan Testing
[p. 197]

A Specialized LowCost Vectorized Loop Buffer for Embedded Processors
[p. 1200]
 Liu,
D.

An EnduranceEnhanced Flash Translation Layer via Reuse for NAND Flash Memory Storage Systems
[p. 14]
 Liu,
F.

An Efficient Mask Optimization Method Based on Homotopy Continuation Technique
[p. 1053]
 Liu,
L.

Towards Coverage Closure: Using Goldmine Assertions for Generating Design Validation Stimulus
[p. 173]

Efficient Validation Input Generation in RTL by Hybridized Source Code Analysis
[p. 1596]
 Liu,
M.

Evaluating the Potential of Graphics Processors for High Performance Embedded Computing
[p. 709]
 Liu,
S.

Efficient Parameter Variation Sampling for Architecture Simulations
[p. 1578]
 Liu,
T.

Register Allocation for Simultaneous Reduction of Energy and Peak Temperature on Registers
[p. 20]
 Liu,
X.

On Multiplexed Signal Tracing for PostSilicon Debug
[p. 685]
 Liu,
Z.

Modeling Circuit Performance Variations Due to Statistical Variability: Monte Carlo Static Timing Analysis
[p. 1537]
 Lo,
C.K.

CycleCountAccurate Processor Modeling for Fast and Accurate SystemLevel Simulation
[p. 341]
 Loghi,
M.

Partitioned Cache Architectures for Reduced NBTIInduced Aging
[p. 938]
 Loi,
I.

Design Space Exploration for 3DStacked DRAMs [p. 389]

A FullySynthesizable SingleCycle Interconnection Network for SharedL1 Processor Clusters
[p. 491]
 López,
C.M.

Systematic Design of a Programmable LowNoise CMOS Neural Interface for Cell Activity Recording
[p. 818]
 Lu,
C.

Stage Number Optimization for Switched Capacitor Power Converters in MicroScale Energy Harvesting
[p. 770]
 Lu,
F.

Efficient Parameter Variation Sampling for Architecture Simulations
[p. 1578]
 Lu,
H.

A Specialized LowCost Vectorized Loop Buffer for Embedded Processors
[p. 1200]
 Lu,
J.

Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing
[p. 455]
 Lu,
K.

An Approach to Improve Accuracy of SourceLevel TLMs of Embedded Software
[p. 216]
 Lu,
S.L.

Distributed Hardware Matcher Framework for SoC Survivability
[p. 305]
 Lubaszewski,
M.S.

Evaluating Energy Consumption of Homogeneous MPSoCs Using Spare Tiles
[p. 1164]
 Ludovici,
D.

Exploiting NetworkonChip Structural Redundancy for a Cooperative and Scalable BuiltIn SelfTest Architecture
[p. 661]
 Luk,
W.S.

An Efficient Algorithm for MultiDomain Clock Skew Scheduling
[p. 1364]
 Lukasiewycz,
M.

FlexRay Switch Scheduling  A Networking Concept for Electric Vehicles
[p. 76]
 Lung,
C.L.

ThermalAware OnLine Task Allocation for 3D MultiCore Processor Throughput Optimization
[p. 8]
 Luo,
G.

Early Chip Planning Cockpit
[p. 863]
 Luo,
H.

Gemma in April: A MatrixLike Parallel Programming Architecture on OpenCL
[p. 703]
 Ma,
K.

LOEDAR: A Low Cost Error Detection and Recovery Scheme for ECC
[p. 1010]
 Ma,
Y.

Optimization of Stateful Hardware Acceleration in Hybrid Architectures
[p. 567]
 Machado da Silva,
J.

A True Power Detector for RF PA BuiltIn Calibration and Testing
[p. 365]
 Macii,
A.

Moving to Green ICT: From StandAlone PowerAware IC Design to an Integrated Approach to Energy
Efficient Design of Heterogeneous Electronic Systems
[p. 1127]
 Macii,
E.

Partitioned Cache Architectures for Reduced NBTIInduced Aging
[p. 938]
 Mahlknecht,
S.

Wireless Communication and Energy Harvesting in Automobiles
[p. 1042]
 Mailly,
F.

An Electrical Test Method for MEMS Convective Accelerometers: Development and Evaluation
[p. 806]
 Mak,
T.

RunTime Deadlock Detection in NetworksonChip Using Coupled Transitive Closure Networks
[p. 497]

Redressing Timing Issues for SpeedIndependent Circuits in Deep Submicron Age
[p. 1376]
 Makris,
Y.

Correlating Inline Data with Final Test Outcomes in Analog/RF Devices
[p. 812]
 Mamaghanian,
H.

A RealTime Compressed SensingBased Personal Electrocardiogram Monitoring System
[p. 824]
 Mangard,
S.

Arithmetic Logic Units with High Error Detection Rates to Counteract Fault Attacks
[p. 1644]
 Manian,
S.

Circuit and DFT Techniques for Robust and Low Cost Qualification of a MixedSignal SoC with Integrated
Power Management System
[p. 551]
 Mansouri,
I.

Sustainability through Massively Integrated Computing: Are We Ready to Break the Energy Efficiency Wall
for SingleChip Platforms?
[p. 1656]
 Marcon,
C.A.M.

Evaluating Energy Consumption of Homogeneous MPSoCs Using Spare Tiles
[p. 1164]
 Marculescu,
D.

Statistical Thermal Evaluation and Mitigation Techniques for 3D ChipMultiprocessors in the Presence of
Process Variations
[p. 383]

AgingAware Timing Analysis and Optimization Considering Path Sensitization
[p. 1572]
 Marculescu,
R.

FARM: FaultAware Resource Management in NoCBased Multiprocessor Platforms
[p. 673]

Sustainability through Massively Integrated Computing: Are We Ready to Break the Energy Efficiency Wall
for SingleChip Platforms?
[p. 1656]
 Maricau,
E.

Stochastic Circuit Reliability Analysis
[p. 1285]

Analog Circuit Reliability in Sub32 Nanometer CMOS: Analysis and Mitigation
[p. 1474]
 Mark,
M.

Powering and Communicating with mmsize Implants
[p. 722]
 Martin,
G.

Virtual Manycore Platforms: Moving Towards 100+ Processor Cores
[p. 715]
 Massas,
J.

Error Prediction Based on Concurrent SelfTest and Reduced Slack Time
[p. 1626]
 Matischek,
R.

RealTime Wireless Communication in Automotive Applications
[p. 1036]
 Matos,
D.

A New Reconfigurable ClockGating Technique for Low Power SRAMBased FPGAs
[p. 752]
 Matsuda,
A.

Developing an Integrated Verification and Debug Methodology
[p. 503]
 Matsumoto,
A.

InterconnectFaultResilient DelayInsensitive Asynchronous Communication Link Based on CurrentFlow
Monitoring
[p. 776]
 Mazzillo,
M.

Solid State Photodetectors for Nuclear Medical Imaging Applications
[p. 511]
 Medwed,
M.

Arithmetic Logic Units with High Error Detection Rates to Counteract Fault Attacks
[p. 1644]
 Mehregany,
M.

HighTemperature (>500°C) Reconfigurable Computing Using Silicon Carbide NEMS Switches
[p. 1065]
 Meissner,
C.

A Unified Methodology for PreSilicon Verification and PostSilicon Validation
[p. 1590]
 Meissner,
M.

Automated ConstraintDriven Topology Synthesis for Analog Circuits
[p. 1662]
 Meixner,
A.

Architectures for Online Error Detection and Recovery in Multicore Processors
[p. 533]
 Melhem,
R.

Impact of Process Variation on Endurance Algorithms for WearProne Memories
[p. 962]
 Memik,
S.O.

Power Optimization in Heterogenous Datapaths
[p. 1400]
 Mendias,
J.M.

Power Optimization in Heterogenous Datapaths
[p. 1400]
 Mercha,
A.

An Analytical Compact Model for Estimation of Stress in Multiple ThroughSilicon Via Configurations
[p. 505]
 Merrett,
G.V.

Ultra LowPower Photovoltaic MPPT Technique for Indoor and Outdoor Wireless Sensor Nodes
[p. 905]
 Accelerated Simulation of
Tunable Vibration Energy Harvesting Systems Using a Linearised
StateSpace Technique [p. 1267]
 Merrett, M.
 Modeling Circuit Performance
Variations Due to Statistical Variability: Monte Carlo Static Timing
Analysis [p. 1537]
 Messina,
A.

Solid State Photodetectors for Nuclear Medical Imaging Applications
[p. 511]
 Metra,
C.

Error Correcting Code Analysis for Cache Memory High Reliability and Performance
[p. 1620]
 Meyer,
B.H.

Reducing the Cost of Redundant Execution in SafetyCritical Systems Using Relaxed Dedication
[p. 1249]
 Meyer,
J.

Fast Startup for Spartan6 FPGAs Using Dynamic Partial Reconfiguration
[p. 1542]
 Meyer,
M.

Realistic PerformanceConstrained Pipelining in HighLevel Synthesis
[p. 1382]
 Meynard, O.
 Enhancement of Simple
ElectroMagnetic Attacks by PreCharacterization in Frequency Domain and
Demodulation Techniques [p. 1004]
 Michel, B.
 Towards ThermallyAware
Design of 3D MPSoCs with InterTier Cooling [p. 1466]
 Michel, L.
 Speedingup SIMD
Instructions Dynamic Binary Translation in Embedded Processor Simulation
[p. 277]
 Milbredt, P.
 FlexRay Switch Scheduling 
A Networking Concept for Electric Vehicles [p. 76]
 Millar, C.
 Modeling Circuit Performance
Variations Due to Statistical Variability: Monte Carlo Static Timing
Analysis [p. 1537]
 Milojevic, D.
 An Analytical Compact Model
for Estimation of Stress in Multiple ThroughSilicon Via Configurations
[p. 505]
 Mina, R.
 Mathematical Approach Based
on a "Design of Experiment" to Simulate Process Variations [p. 1486]
 Miranda, M.
 Variability Aware Modeling
for Yield Enhancement of SRAM and Logic [p. 1153]
 Miremadi, S.G.
 Soft Error Rate Estimation
of Digital Circuits in the Presence of Multiple Event Transients (METs)
[p. 70]
 ScTMR: A Scan ChainBased
Error Recovery Technique for TMR Systems in SafetyCritical Applications
[p. 289]
 Mirhoseini, A.
 HypoEnergy: Hybrid
SupercapacitorBattery PowerSupply Optimization for Energy Efficiency
[p. 887]
 Mishra, P.
 Decision Ordering Based
Property Decomposition for Functional Test Generation [p. 167]
 Mistry, J.N.
 SubClock PowerGating
Technique for Minimising Leakage Power During Active Mode [p. 106]
 Mitea,
O.

Automated ConstraintDriven Topology Synthesis for Analog Circuits
[p. 1662]
 Mittal, R.K.
 Circuit and DFT Techniques
for Robust and Low Cost Qualification of a MixedSignal SoC with
Integrated Power Management System [p. 551]
 Miyase, K.
 TransitionTimeRelation
Based CaptureSafety Checking for AtSpeed Scan Test Generation [p. 895]
 Modarressi, M.
 Supporting NonContiguous
Processor Allocation in MeshBased CMPs Using Virtual PointtoPoint
Links [p. 413]
 MoezziMadani, N.
 An EnergyEfficient 64QAM
MIMO Detector for Emerging Wireless Standards [p. 246]
 Mohalik, S.
 When to Stop Verification?
Statistical TradeOff between Expected Loss and Simulation Cost [p.
1309]
 Mohanram, K.
 Robust 6T Si Tunneling
Transistor SRAM Design [p. 740]

Reliabilitydriven Don't Care Assignment for Logic Synthesis
[p. 1560]
 Mohapatra, D.
 Design of VoltageScalable
Meta Functions for Approximate Computing [p. 950]
 Molina, M.C.
 Power Optimization in
Heterogenous Datapaths [p. 1400]
 Montag, P.
 Precise WCET Calculation in
Highly Variant RealTime Systems [p. 920]
 Moraes, F.G.
 Achieving Composability in
NoCBased MPSoCs Through QoS Management at Software Level [p. 407]
 Evaluating Energy
Consumption of Homogeneous MPSoCs Using Spare Tiles [p. 1164]
 Moroz, V.
 An Analytical Compact Model
for Estimation of Stress in Multiple ThroughSilicon Via Configurations
[p. 505]
 Mossé, D.
 Impact of Process Variation
on Endurance Algorithms for WearProne Memories [p. 962]
 Moy, M.
 jTLM: An Experimentation
Framework for the Simulation of TransactionLevel Models of
SystemsonChip [p. 1184]
 Mu, S.
 Evaluating the Potential of
Graphics Processors for High Performance Embedded Computing [p. 709]
 Mudge, T.
 Low Power Interconnects for
SIMD Computers [p. 600]
 Mueller, W.
 A Reconfiguration Approach
for FaultTolerant FlexRay Networks [p. 82]
 Mukhopadhyay, D.
 MultiLevel Attacks: An
Emerging Security Concern for Cryptographic Hardware [p. 1176]
 Theoretical Modeling of the
ItohTsujii Inversion Algorithm for Enhanced Performance on kLUT Based
FPGAs [p. 1231]
 Murugappa, P.
 A Flexible High Throughput
MultiASIP Architecture for LDPC and Turbo Decoding [p. 228]
 Musa, S.
 Systematic Design of a
Programmable LowNoise CMOS Neural Interface for Cell Activity Recording
[p. 818]
 Nacci, A.A.
 A HighPerformance Parallel
Implementation of the Chambolle Algorithm [p. 1436]
 Nadeem, M.
 Targeting Code Diversity
with RunTime Adjustable IssueSlots in a Chip Multiprocessor [p. 1358]
 Naeimi,
H.

A ConfidenceDriven Model for ErrorResilient Computing
[p. 1608]
 Nagel, J.L.
 Energy Parsimonious Circuit
Design through Probabilistic Pruning [p. 764]
 Nahir,
A.

A Unified Methodology for PreSilicon Verification and PostSilicon Validation
[p. 1590]
 Najm, F.N.
 Efficient RC Power Grid
Verification Using Node Elimination [p. 257]
 Nalam, S.
 Dynamic Write Limited
Minimum Operating Voltage for Nanoscale SRAMs [p. 467]
 Narasimhan, S.
 HighTemperature
(>500°C) Reconfigurable Computing Using Silicon Carbide NEMS
Switches [p. 1065]
 Narayanan, P.
 Circuit and DFT Techniques
for Robust and Low Cost Qualification of a MixedSignal SoC with
Integrated Power Management System [p. 551]
 Narayanan, R.
 Ensuring Correctness of
Analog Circuits in Presence of Noise and Process Variations Using
Pattern Matching [p. 1188]
 Narayanan, V.
 SHARC: A Streaming Model for
FPGA Accelerators and its Application to Saliency [p. 1237]
 Narayanasamy, S.
 MLP Aware Heterogeneous
Memory System [p. 956]
 Nelms, T.
 Optimization of Stateful
Hardware Acceleration in Hybrid Architectures [p. 567]
 Nercessian, E.
 Mathematical Approach Based
on a "Design of Experiment" to Simulate Process Variations [p. 1486]
 Neuendorffer, S.
 Building Realtime HDTV
Applications in FPGAs Using Processors, AXI Interfaces and High Level
Synthesis Tools [p. 848]
 Nicolaidis, M.
 A faultTolerant
DeadlockFree Adaptive Routing for On Chip Interconnects [p. 909]

Eliminating Speed Penalty in ECC Protected Memories
[p. 1614]
 Nicolescu, G.
 MultiGranularity Thermal
Evaluation of 3D MPSoC Architectures [p. 575]
 Optical Ring NetworkonChip
(ORNoC): Architecture and Design Methodology [p. 788]
 A MultiObjective
DecisionTheoretic Exploration Algorithm for Platformbased Design [p.
1192]
 Nigam, A.
 Pseudo Circuit Model for
Representing Uncertainty in Waveforms [p. 1521]
 Nikiforos, G.
 FineGrain OpenMP Runtime
Support with Explicit Communication Hardware Primitives [p. 891]
 Nikolopoulos, D.S.
 FineGrain OpenMP Runtime
Support with Explicit Communication Hardware Primitives [p. 891]
 Niu, L.
 SystemLevel
EnergyEfficient Scheduling for Hard RealTime Embedded Systems [p. 281]
 Nocco, S.
 Interpolation Sequences
Revisited [p. 317]
 Optimized Model Checking of
Multiple Properties [p. 543]
 Noguera, J.
 Building Realtime HDTV
Applications in FPGAs Using Processors, AXI Interfaces and High Level
Synthesis Tools [p. 848]

Fast Startup for Spartan6 FPGAs Using Dynamic Partial Reconfiguration
[p. 1542]
 Nouet, P.
 An Electrical Test Method
for MEMS Convective Accelerometers: Development and Evaluation [p. 806]
 Nowak,
J.

Strategies for Initial Sizing and Operating Point Analysis of Analog Circuits
[p. 1672]
 Nowick, S.M.
 A DelayInsensitive
BusInvert Code and Hardware Support for Robust Asynchronous Global
Communication [p. 1370]
 O'Connor, I.
 MultiGranularity Thermal
Evaluation of 3D MPSoC Architectures [p. 575]
 Optical Ring NetworkonChip
(ORNoC): Architecture and Design Methodology [p. 788]
 Omrane, B.
 2D and 3D Integration with
Organic and Silicon Electronics [p. 899]
 Onizawa, N.
 InterconnectFaultResilient
DelayInsensitive Asynchronous Communication Link Based on CurrentFlow
Monitoring [p. 776]
 Orailoglu, A.
 Register Allocation for
Simultaneous Reduction of Energy and Peak Temperature on Registers [p.
20]
 Diagnosing Scan Chain Timing
Faults through Statistical Feature Analysis of Scan Images [p. 185]
 Frugal but Flexible
Multicore Topologies in Support of Resource VariationDriven Adaptivity
[p. 1255]
 Adaptive Test Optimization
through Real Time Learning of Test Effectiveness [p. 1430]
 Orshansky, M.
 Controlled TimingError
Acceptance for Low Energy IDCT Design [p. 758]
 Ost, L.C.
 Evaluating Energy
Consumption of Homogeneous MPSoCs Using Spare Tiles [p. 1164]
 Ottavi, M.
 Feedback Based Droop
Mitigation [p. 879]
 Ottella, M.
 System Level Techniques to
Improve Reliability in High Power Microcontrollers for Automotive
Applications [p. 1123]
 Paek, Y.
 I^{2}CRF:
Incremental Interconnect Customization for Embedded Reconfigurable
Fabrics [p. 1346]
 Palem, K.
 Energy Parsimonious Circuit
Design through Probabilistic Pruning [p. 764]
 Palesi, M.
 RunTime Deadlock Detection
in NetworksonChip Using Coupled Transitive Closure Networks [p. 497]
 Palframan, D.J.
 Time Redundant Parity for
LowCost Transient Error Detection [p. 52]
 Pan, S.
 A CostEffective
SubstantialImpactFilter Based Method to Tolerate Voltage Emergencies
[p. 311]
 Pande,
P.

Sustainability through Massively Integrated Computing: Are We Ready to Break the Energy Efficiency Wall
for SingleChip Platforms?
[p. 1656]
 Pangrle, B.
 Beyond UPF & CPF:
LowPower Design and Verification [p. 252]
 Papa, C.
 Smart Systems at ST [p.
1230]
 Papadas, C.
 SystemLevel Power
Estimation Methodology Using Cycle and BitAccurate TLM [p. 1125]
 Papaefstathiou, I.
 Parallel Accelerators for
GlimmerHMM Bioinformatics Algorithm [p. 94]
 Papaefstathiou, V.
 FineGrain OpenMP Runtime
Support with Explicit Communication Hardware Primitives [p. 891]
 Papariello, F.
 An Efficient OnLine Task
Allocation Algorithm for QoS and Energy Efficiency in Multicore
Multimedia Platforms [p. 100]
 Park, H.
 A Novel Tag Access Scheme
for Low Power L2 Cache [p. 655]
 Park, S.
 I^{2}CRF:
Incremental Interconnect Customization for Embedded Reconfigurable
Fabrics [p. 1346]
 Park, S.P.
 Stage Number Optimization
for Switched Capacitor Power Converters in MicroScale Energy Harvesting
[p. 770]
 Parthasarathy, H.
 Circuit and DFT Techniques
for Robust and Low Cost Qualification of a MixedSignal SoC with
Integrated Power Management System [p. 551]
 Pasetti, G.
 Characterization of an
Intelligent Power Switch for LED Driving with Control of Wiring
Parasitics Effects [p. 1119]
 Patel, H.D.
 Abstract State Machines as
an Intermediate Representation for HighLevel Synthesis [p. 1406]
 Paterna, F.
 An Efficient OnLine Task
Allocation Algorithm for QoS and Energy Efficiency in Multicore
Multimedia Platforms [p. 100]
 Paul, S.
 Architecture and
FPGAImplementation of a High Throughput K^{+}Best Detector [p.
240]
 Paulin, P.
 Optical Ring NetworkonChip
(ORNoC): Architecture and Design Methodology [p. 788]
 Pavlenko, E.
 STABLE: A New QFBV SMT
Solver for Hard Verification Problems combining Boolean Reasoning with
Computer Algebra [p. 155]
 Pavlidis, V.F.
 Analytical Heat Transfer
Model for Thermal ThroughSilicon Vias [p. 395]
 Pedram, M.
 Variation Aware Dynamic
Power Management for Chip Multiprocessor Architectures [p. 473]
 BatterySupercapacitor
Hybrid System for HighRate Pulsed Load Applications [p. 875]
 Timing VariationAware
Custom Instruction Extension Technique [p. 1517]
 Peikenkamp, T.
 Using ContractBased
Component Specifications for Virtual Integration Testing and
Architecture Design [p. 1023]
 Peizerat, A.
 Smart Imagers of the Future
[p. 437]
 Penolazzi, S.
 Predicting Bus Contention
Effects on Energy and Performance in MultiProcessor SoCs [p. 1196]
 Perathoner, S.
 Composing Heterogeneous
Components for SystemWide Performance Analysis [p. 842]
 Perini, F.
 An Efficient QuantumDot
Cellular Automata Adder [p. 1220]
 Pétrot, F.
 Speedingup SIMD
Instructions Dynamic Binary Translation in Embedded Processor Simulation
[p. 277]
 Phadke, S.
 MLP Aware Heterogeneous
Memory System [p. 956]
 Pichot, V.
 Low Power Smart Industrial
Control [p. 595]
 Pigorsch, F.
 Integration of Orthogonal
QBF Solving Techniques [p. 149]
 Piguet, C.
 Energy Parsimonious Circuit
Design through Probabilistic Pruning [p. 764]
 Pino, R.E.
 3DICML: A 3D Bipolar ReRAM
Design with Interleaved Complementary Memory Layers [p. 583]
 Polarouthu, S.
 Circuit and DFT Techniques
for Robust and Low Cost Qualification of a MixedSignal SoC with
Integrated Power Management System [p. 551]
 Polian, I.
 Adaptive Voltage
OverScaling for Resilient Applications [p. 944]
 Politis, S.
 SystemLevel Power
Estimation Methodology Using Cycle and BitAccurate TLM [p. 1125]
 Pomeranz, I.
 BuiltIn Generation of
Functional Broadside Tests [p. 1297]
 HyperGraph Based
Partitioning to Reduce DFT Cost for PreBond 3DIC Testing [p. 1424]
 Poncino, M.
 Partitioned Cache
Architectures for Reduced NBTIInduced Aging [p. 938]
 System Level Techniques to
Improve Reliability in High Power Microcontrollers for Automotive
Applications [p. 1123]
 Moving to Green ICT: From
StandAlone PowerAware IC Design to an Integrated Approach to Energy
Efficient Design of Heterogeneous Electronic Systems [p. 1127]
 Pontarelli, S.
 Feedback Based Droop
Mitigation [p. 879]
 Porquet, J.
 NoCMPU: A Secure
Architecture for Flexible CoHosting on Shared Memory MPSoCs [p. 591]
 Pozzi, L.
 SlackAware Scheduling on
Coarse Grained Reconfigurable Arrays [p. 1513]
 Pribyl, W.
 A Method for Fast Jitter
Tolerance Analysis of HighSpeed PLLs [p. 1107]
 Psarakis, M.
 Architectures for Online
Error Detection and Recovery in Multicore Processors [p. 533]
 Puers, R.
 Systematic Design of a
Programmable LowNoise CMOS Neural Interface for Cell Activity Recording
[p. 818]
 Puschini,
D.

Sustainability through Massively Integrated Computing: Are We Ready to Break the Energy Efficiency Wall
for SingleChip Platforms?
[p. 1656]
 Qiao, P.
 A 0.964mW Digital Hearing
Aid System [p. 883]
 Qin, Z.
 An EnduranceEnhanced Flash
Translation Layer via Reuse for NAND Flash Memory Storage Systems [p.
14]
 Quan, G.
 Leakage Aware Energy
Minimization for RealTime Systems under the Maximum Temperature
Constraint [p. 479]
 Quer, S.
 Interpolation Sequences
Revisited [p. 317]
 Raabe, A.
 A Workflow for Runtime
Adaptive Task Allocation on Heterogeneous MPSoCs [p. 1129]
 Priority Division: A
HighSpeed SharedMemory Bus Arbitration with Bounded Latency [p. 1497]
 Rabaey, J.M.
 Powering and Communicating
with mmsize Implants [p. 722]
 Raghunathan, A.
 VESPA: Variability Emulation
for SystemonChip Performance Analysis [p. 2]
 Design of VoltageScalable
Meta Functions for Approximate Computing [p. 950]
 Raghunathan, V.
 Stage Number Optimization
for Switched Capacitor Power Converters in MicroScale Energy Harvesting
[p. 770]
 Rahagude, N.
 DesignforTest Methodology
for NonScan AtSpeed Testing [p. 191]
 Rahimi, A.
 A FullySynthesizable
SingleCycle Interconnection Network for SharedL1 Processor Clusters
[p. 491]
 Rahman, M.
 Power Reduction via
NearOptimal LibraryBased CellSize Selection [p. 867]
 Rai, D.
 WorstCase Temperature
Analysis for RealTime Systems [p. 631]
 Rajgopal, S.
 HighTemperature
(>500°C) Reconfigurable Computing Using Silicon Carbide NEMS
Switches [p. 1065]
 Ramachandran, P.
 Architectures for Online
Error Detection and Recovery in Multicore Processors [p. 533]
 Ramesh, S.
 When to Stop Verification?
Statistical TradeOff between Expected Loss and Simulation Cost [p.
1309]
 Rana, V.
 An Efficient QuantumDot
Cellular Automata Adder [p. 1220]
 A HighPerformance Parallel
Implementation of the Chambolle Algorithm [p. 1436]
 Ranganathan, N.
 A New Reversible Design of
BCD Adder [p. 1180]
 Razaghi, P.
 HostCompiled Multicore RTOS
Simulator for Embedded RealTime Software Development [p. 222]
 Réal, D.
 Enhancement of Simple
ElectroMagnetic Attacks by PreCharacterization in Frequency Domain and
Demodulation Techniques [p. 1004]
 Rebeiro, C.
 Theoretical Modeling of the
ItohTsujii Inversion Algorithm for Enhanced Performance on kLUT Based
FPGAs [p. 1231]
 Reddy, P.
 A Low Complexity Stopping
Criterion for Reducing Power Consumption in Turbo Decoders [p. 649]
 Reddy, S.M.
 HyperGraph Based
Partitioning to Reduce DFT Cost for PreBond 3DIC Testing [p. 1424]
 Reid, D.
 Modeling Circuit Performance
Variations Due to Statistical Variability: Monte Carlo Static Timing
Analysis [p. 1537]
 Reimer, S.
 Integration of Orthogonal
QBF Solving Techniques [p. 149]
 Rekik, A.A.
 An Electrical Test Method
for MEMS Convective Accelerometers: Development and Evaluation [p. 806]
 Rémond, E.
 Mathematical Approach Based
on a "Design of Experiment" to Simulate Process Variations [p. 1486]
 Reynaert, P.
 Global Optimization of
Integrated Transformers for High Frequency Microwave Circuits Using a
Gaussian Process Based Surrogate Model [p. 1101]
 Richardson, S.
 Intermediate Representations
for Controllers in Chip Generators [p. 1394]
 Rinaudo, S.
 Moving to Green ICT: From
StandAlone PowerAware IC Design to an Integrated Approach to Energy
Efficient Design of Heterogeneous Electronic Systems [p. 1127]
 Rocchi, A.
 A Sensor Fusion Algorithm
for an Integrated Angular Position Estimation with Inertial Measurement
Units [p. 273]
 Romeo, M.
 Solid State Photodetectors
for Nuclear Medical Imaging Applications [p. 511]
 Roop, P.S.
 Pruning Infeasible Paths for
Tight WCRT Analysis of Synchronous Programs [p. 204]
 Rosenstiel, W.
 Scalable Hybrid Verification
for Embedded Software [p. 179]
 Fast and Accurate Resource
Conflict Simulation for Performance Analysis of MultiCore Systems [p.
210]
 Rossi,
D.

Error Correcting Code Analysis for Cache Memory High Reliability and Performance
[p. 1620]
 Roussel, P.
 Variability Aware Modeling
for Yield Enhancement of SRAM and Logic [p. 1153]
 Roy, K.
 Stage Number Optimization
for Switched Capacitor Power Converters in MicroScale Energy Harvesting
[p. 770]
 Design of VoltageScalable
Meta Functions for Approximate Computing [p. 950]
 Roy, S.
 Topologically Homogeneous
PowerPerformance Heterogeneous Multicore Systems [p. 125]
 WasteAware Dilution and
Mixing of Biochemical Samples with Digital Microfluidic Biochips [p.
1059]
 Modeling Circuit Performance
Variations Due to Statistical Variability: Monte Carlo Static Timing
Analysis [p. 1537]
 Roy, S.S.
 Theoretical Modeling of the
ItohTsujii Inversion Algorithm for Enhanced Performance on kLUT Based
FPGAs [p. 1231]
 Roychowdhury, J.
 SAMURAI: An Accurate Method
for Modeling and Simulating NonStationary Random Telegraph Noise in
SRAMs [p. 1113]
 Ruf, J.
 Scalable Hybrid Verification
for Embedded Software [p. 179]
 Ruggeri, M.
 An Effective MultiSource
Energy Harvester for Low Power Applications [p. 836]
 Sabatelli, S.
 A Sensor Fusion Algorithm
for an Integrated Angular Position Estimation with Inertial Measurement
Units [p. 273]
 Sabatini, M.
 Energy Analysis Methods and
Tools For Modelling and Optimizing Tyre Systems [p. 1121]
 Sabbarwal, P.
 Circuit and DFT Techniques
for Robust and Low Cost Qualification of a MixedSignal SoC with
Integrated Power Management System [p. 551]
 Sabry, M.M.
 Towards ThermallyAware
Design of 3D MPSoCs with InterTier Cooling [p. 1466]
 Safar, M.
 A Reconfigurable, Pipelined,
Conflict Directed Jumping Search SAT Solver [p. 1243]
 Safarpour, S.
 Automated Debugging of
SystemVerilog Assertions [p. 323]
 Sakare, M.
 Testing of HighSpeed DACs
Using PRBS Generation with "AlternateBitTapping" [p. 377]
 Salcic, Z.
 DynOAA  Dynamic
Offset Adaptation Algorithm for Improving Response Times of CAN Systems
[p. 269]
 Salem, A.
 A Reconfigurable, Pipelined,
Conflict Directed Jumping Search SAT Solver [p. 1243]
 Salsano, A.
 Feedback Based Droop
Mitigation [p. 879]
 Sampaio, A.M.
 SystemLevel Modeling of a
MixedSignal System on Chip for Wireless Sensor Networks [p. 1501]
 Sanchez, E.
 Fault Grading of
SoftwareBased SelfTest Procedures for Dependable Automotive
Applications [p. 513]
 Sander, I.
 Predicting Bus Contention
Effects on Energy and Performance in MultiProcessor SoCs [p. 1196]
 Sander,
O.

Fast Startup for Spartan6 FPGAs Using Dynamic Partial Reconfiguration
[p. 1542]
 Sandhu,
S.

A ConfidenceDriven Model for ErrorResilient Computing
[p. 1608]
 Sanghani, A.
 A ClockGating Based Capture
Power Droop Reduction Methodology for AtSpeed Scan Testing [p. 197]
 SangiovanniVincentelli, A.
 ComponentBased Design for
the Future [p. 1029]
 Santambrogio, M.D.
 A HighPerformance Parallel
Implementation of the Chambolle Algorithm [p. 1436]
 Sapatnekar, S.
 A Scaled Random Walk Solver
for Fast Power Grid Analysis [p. 38]
 Sapatnekar, S.S.
 Enabling Improved Power
Management in Multicore Processors through Clustered DVFS [p. 293]
 Saponara, S.
 Characterization of an
Intelligent Power Switch for LED Driving with Control of Wiring
Parasitics Effects [p. 1119]
 Sarangi, S.
 A ClockGating Based Capture
Power Droop Reduction Methodology for AtSpeed Scan Testing [p. 197]
 SarbaziAzad, H.
 Supporting NonContiguous
Processor Allocation in MeshBased CMPs Using Virtual PointtoPoint
Links [p. 413]
 Sartori, J.
 On the Efficacy of NBTI
Mitigation Techniques [p. 932]
 Sassateli, G.
 Achieving Composability in
NoCBased MPSoCs Through QoS Management at Software Level [p. 407]
 Satpathy, S.
 Low Power Interconnects for
SIMD Computers [p. 600]
 Schaefer,
E.

A New Method for Automated Generation of Compensation Networks  The EDA Designer Finger
[p. 1666]
 Schaumont,
P.

DataOriented Performance Analysis of SHA3 Candidates on FPGA Accelerated Computers
[p. 1650]
 Schenkelaars, T.
 Optimal Scheduling of
Switched FlexRay Networks [p. 926]
 Schirrmeister, F.
 Virtual Manycore Platforms:
Moving Towards 100+ Processor Cores [p. 715]
 Schmidt, J.M.
 Lowcost Fault Detection
Method for ECC Using Montgomery Powering Ladder [p. 1016]
 Schneider, R.
 ReEngineering
CyberPhysical Control Applications for Hybrid Communication Protocols
[p. 914]
 Schoellkopf, J.P.
 SystemLevel Power
Estimation Methodology Using Cycle and BitAccurate TLM [p. 1125]
 Scholl, C.
 Integration of Orthogonal
QBF Solving Techniques [p. 149]
 Schulte, M.
 Scratchpad Memory
Optimizations for Digital Signal Processing Applications [p. 974]
 Schumann,
J.

A Unified Methodology for PreSilicon Verification and PostSilicon Validation
[p. 1590]
 Schwarz, C.
 NoCMPU: A Secure
Architecture for Flexible CoHosting on Shared Memory MPSoCs [p. 591]
 Sciolla, M.
 System Level Techniques to
Improve Reliability in High Power Microcontrollers for Automotive
Applications [p. 1123]
 Sciuto, D.
 An Efficient QuantumDot
Cellular Automata Adder [p. 1220]
 Sechen, C.
 Power Reduction via
NearOptimal LibraryBased CellSize Selection [p. 867]
 Sechi, F.
 A Sensor Fusion Algorithm
for an Integrated Angular Position Estimation with Inertial Measurement
Units [p. 273]
 Seelisch, F.
 STABLE: A New QFBV SMT
Solver for Hard Verification Problems combining Boolean Reasoning with
Computer Algebra [p. 155]
 Segura, J.
 Stability Optimization of
Embedded 8T SRAMs Using WordLine Voltage Modulation [p. 986]

An Efficient and Scalable STA Tool with Direct Path Estimation and Exhaustive Sensitization Vector
Exploration for Optimal Delay Computation
[p. 1602]
 Sekanina, L.
 A Global Postsynthesis
Optimization Method for Combinational Circuits [p. 1525]
 Seo, J.
 BatterySupercapacitor
Hybrid System for HighRate Pulsed Load Applications [p. 875]
 Serventi, R.
 Characterization of an
Intelligent Power Switch for LED Driving with Control of Wiring
Parasitics Effects [p. 1119]
 Seshia, S.A.
 CounterexampleGuided
SMTDriven Optimal Buffer Sizing [p. 329]
 Sha, E.H.M.
 Towards Energy Efficient
Hybrid OnChip Scratch Pad Memory with NonVolatile Memory [p. 746]
 Shafique, M.
 MinorityGameBased Resource
Allocation for RunTime Reconfigurable MultiCore Processors [p. 1261]
 MultiLevel Pipelined
Parallel Hardware Architecture for High Throughput Motion and Disparity
Estimation in Multiview Video Coding [p. 1448]

mRTS: RunTime System for Reconfigurable Processors with MultiGrained InstructionSet Extensions
[p. 1554]
 Shah, H.
 Priority Division: A
HighSpeed SharedMemory Bus Arbitration with Bounded Latency [p. 1497]
 Shalan, M.
 A Reconfigurable, Pipelined,
Conflict Directed Jumping Search SAT Solver [p. 1243]
 Shanbhag, N.
 SystemAssisted Analog
MixedSignal Design [p. 1491]
 Shanbhag, N.R.
 Timing Error Statistics for
EnergyEfficient Robust DSP Systems [p. 285]
 Shao, Z.
 An EnduranceEnhanced Flash
Translation Layer via Reuse for NAND Flash Memory Storage Systems [p.
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 Shen, H.
 Empirical Design Bugs
Prediction for Verification [p. 161]
 Shen, L.
 A Specialized LowCost
Vectorized Loop Buffer for Embedded Processors [p. 1200]
 Sheridan, D.
 Towards Coverage Closure:
Using Goldmine Assertions for Generating Design Validation Stimulus [p.
173]
 Shi, X.
 An Efficient Mask
Optimization Method Based on Homotopy Continuation Technique [p. 1053]
 Shih, C.S.
 Pipeline Schedule Synthesis
for RealTime Streaming Tasks with Inter/IntraInstance Precedence
Constraints [p. 1321]
 Shim,
K.

Temporal Parallel Simulation: A Fast GateLevel HDL Simulation Using Higher Level Models
[p. 1584]
 Shin, D.
 BatterySupercapacitor
Hybrid System for HighRate Pulsed Load Applications [p. 875]

A New Circuit Simplification Method for Error Tolerant Applications
[p. 1566]
 Shin, J.
 Early Chip Planning Cockpit
[p. 863]
 Shurek,
G.

A Unified Methodology for PreSilicon Verification and PostSilicon Validation
[p. 1590]
 Siegl, S.

Formal Specification and
Systematic ModelDriven Testing of Embedded Automotive Systems [p. 118]
 Sifakis, J
 Methods and Tools for
ComponentBased System Design [p. 1022]
 Silveira, L.M.
 Fast Statistical Analysis of
RC Nets Subject to Manufacturing Variabilities [p. 32]
 Singer, A.
 SystemAssisted Analog
MixedSignal Design [p. 1491]
 Singh, M.
 Testing of HighSpeed DACs
Using PRBS Generation with "AlternateBitTapping" [p. 377]
 Sinha,
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DataOriented Performance Analysis of SHA3 Candidates on FPGA Accelerated Computers
[p. 1650]
 Sinha, R.
 Abstract State Machines as
an Intermediate Representation for HighLevel Synthesis [p. 1406]
 Skadron, K.
 Reducing the Cost of
Redundant Execution in SafetyCritical Systems Using Relaxed Dedication
[p. 1249]
 Slamani, M.
 Correlating Inline Data with
Final Test Outcomes in Analog/RF Devices [p. 812]
 Soeken, M.
 Verifying Dynamic Aspects of
UML Models [p. 1077]
 Somenzi, F.
 Clause Simplification
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 Sommer,
R.

A New Method for Automated Generation of Compensation Networks  The EDA Designer Finger
[p. 1666]

Strategies for Initial Sizing and Operating Point Analysis of Analog Circuits
[p. 1672]
 Sorin, D.
 Architectures for Online
Error Detection and Recovery in Multicore Processors [p. 533]
 Sotiriades, E.
 Parallel Accelerators for
GlimmerHMM Bioinformatics Algorithm [p. 94]
 Spica,
M.

Error Correcting Code Analysis for Cache Memory High Reliability and Performance
[p. 1620]
 Sporrer,
C.

A New Method for Automated Generation of Compensation Networks  The EDA Designer Finger
[p. 1666]
 Sreedhar, A.
 On Design of Test Structures
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 Modeling Manufacturing
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Physically Unclonable Functions for Embedded Security Based on Lithographic Variation
[p. 1632]
 Sridhar, A.
 Towards ThermallyAware
Design of 3D MPSoCs with InterTier Cooling [p. 1466]
 Srivastava, M.
 VariabilityAware Duty Cycle
Scheduling in Long Running Embedded Sensing Systems [p. 131]
 Stattelmann, S.
 Fast and Accurate Resource
Conflict Simulation for Performance Analysis of MultiCore Systems [p.
210]
 Sterpone, L.
 A New Reconfigurable
ClockGating Technique for Low Power SRAMBased FPGAs [p. 752]
 Stevenson, P.
 Intermediate Representations
for Controllers in Chip Generators [p. 1394]
 Stewart,
R.

Fast Startup for Spartan6 FPGAs Using Dynamic Partial Reconfiguration
[p. 1542]
 Stierand, I.
 Using ContractBased
Component Specifications for Virtual Integration Testing and
Architecture Design [p. 1023]
 Stoffel, D.
 STABLE: A New QFBV SMT
Solver for Hard Verification Problems combining Boolean Reasoning with
Computer Algebra [p. 155]
 Strano, A.
 Exploiting NetworkonChip
Structural Redundancy for a Cooperative and Scalable BuiltIn SelfTest
Architecture [p. 661]
 Streichert, T.
 An Automated Data Structure
Migration Concept  From CAN to Ethernet/IP in Automotive Embedded
Systems (CANoverIP) [p. 112]
 Struzyna, M.
 Flowbased Partitioning and
Position Constraints in VLSI Placement [p. 607]
 Sumikawa, N.
 Multidimensional Parametric
Test Set Optimization of Wafer Probe Data for Predicting in Field
Failures and Setting Tighter Test Limits [p. 794]
 Sun, Z.
 A UML 2Based
Hardware/Software CoDesign Framework for Body Sensor Network
Applications [p. 1505]
 Sutardja, C.
 Powering and Communicating
with mmsize Implants [p. 722]
 Sylvester, D.
 Low Power Interconnects for
SIMD Computers [p. 600]

A ConfidenceDriven Model for ErrorResilient Computing
[p. 1608]
 Sylvester,
M.

Strategies for Initial Sizing and Operating Point Analysis of Analog Circuits
[p. 1672]
 Szczukiewicz, S.
 Towards ThermallyAware
Design of 3D MPSoCs with InterTier Cooling [p. 1466]
 Tahar, S.
 Ensuring Correctness of
Analog Circuits in Presence of Noise and Process Variations Using
Pattern Matching [p. 1188]
 Tahoori, M.B.
 Soft Error Rate Estimation
of Digital Circuits in the Presence of Multiple Event Transients (METs)
[p. 70]
 Tang, C.
 Powering and Communicating
with mmsize Implants [p. 722]
 Tang, Q.
 Pseudo Circuit Model for
Representing Uncertainty in Waveforms [p. 1521]
 Tanimura, K.
 SlackAware Scheduling on
Coarse Grained Reconfigurable Arrays [p. 1513]
 Tasic, B.
 Test Time Reduction in
Analogue/MixedSignal Devices by Defect Oriented Testing: An Industrial
Example [p. 371]
 Taskin, B.
 Steiner Tree Based Rotary
Clock Routing with Bounded Skew and Capacitive Load Balancing [p. 455]
 Tavakkol, A.
 Supporting NonContiguous
Processor Allocation in MeshBased CMPs Using Virtual PointtoPoint
Links [p. 413]
 Tchagaspanian, M.
 Smart Imagers of the Future
[p. 437]
 Tehranipoor,
M.

RON: An OnChip Ring Oscillator Network for Hardware Trojan Detection
[p. 1638]
 Teich, J.

An Automated Data Structure
Migration Concept  From CAN to Ethernet/IP in Automotive Embedded
Systems (CANoverIP) [p. 112]
 DynOAA  Dynamic Offset
Adaptation Algorithm for Improving Response Times of CAN Systems [p.
269]
 A RuleBased Static Dataflow
Clustering Algorithm for Efficient Embedded Software Synthesis [p. 521]
 Temiz, Y.
 Towards ThermallyAware
Design of 3D MPSoCs with InterTier Cooling [p. 1466]
 Tendulkar, P.
 FineGrain OpenMP Runtime
Support with Explicit Communication Hardware Primitives [p. 891]
 Tennakoon, H.
 Power Reduction via
NearOptimal LibraryBased CellSize Selection [p. 867]
 Thapliyal, H.
 A New Reversible Design of
BCD Adder [p. 1180]
 Theocharides, T.
 DepthDirected Hardware
Object Detection [p. 1442]
 Thiele, L.
 WorstCase Temperature
Analysis for RealTime Systems [p. 631]
 Composing Heterogeneous
Components for SystemWide Performance Analysis [p. 842]
 XSENSE: Sensing in Extreme
Environments [p. 1460]
 Thome, J.R.
 Towards ThermallyAware
Design of 3D MPSoCs with InterTier Cooling [p. 1466]
 Thorolfsson, T.
 An EnergyEfficient 64QAM
MIMO Detector for Emerging Wireless Standards [p. 246]
 Tilli, A.
 A Distributed and
SelfCalibrating ModelPredictive Controller for Energy and Thermal
Management of HighPerformance Multicores [p. 830]
 Timoncini,
N.

Error Correcting Code Analysis for Cache Memory High Reliability and Performance
[p. 1620]
 Tinfena, F.
 Characterization of an
Intelligent Power Switch for LED Driving with Control of Wiring
Parasitics Effects [p. 1119]
 Tino, A.
 MultiObjective Tabu Search
Based Topology Generation Technique for ApplicationSpecific
NetworkonChip Architectures [p. 485]
 Tiwari, P.
 Power Management
Verification Experiences in Wireless SoCs [p. 507]
 Topham, N.
 Virtual Manycore Platforms:
Moving Towards 100+ Processor Cores [p. 715]
 Torrens, G.
 Stability Optimization of
Embedded 8T SRAMs Using WordLine Voltage Modulation [p. 986]
 Trajcevski,
G.

Efficient Parameter Variation Sampling for Architecture Simulations
[p. 1578]
 Trajkovic, J.
 Optical Ring NetworkonChip
(ORNoC): Architecture and Design Methodology [p. 788]
 Traulsen, C.
 Compiling SyncCharts to
Synchronous C [p. 563]
 Tsai, T.Y.
 On Routing Fixed Escaped
Boundary Pins for High Speed Boards [p. 461]
 Tsay, R.S.
 DOM: A
DataDependencyOriented Modeling Approach for Efficient Simulation of
OS Preemptive Scheduling [p. 335]
 CycleCountAccurate
Processor Modeling for Fast and Accurate SystemLevel Simulation [p.
341]
 A SharedVariableBased
Synchronization Approach to Efficient Cache Coherence Simulation for
MultiCore Systems [p. 347]
 Tseng, C.K.
 BlackBox Leakage Power
Modeling for Cell Library and SRAM Compiler [p. 637]
 Tseng, W.C.
 Towards Energy Efficient
Hybrid OnChip Scratch Pad Memory with NonVolatile Memory [p. 746]
 Tsukiyama, S.
 An Algorithm to Improve
Accuracy of Criticality in Statistical Static Timing Analysis [p. 1529]
 Ttofis, C.
 DepthDirected Hardware
Object Detection [p. 1442]
 Tuohy, W.
 Towards Coverage Closure:
Using Goldmine Assertions for Generating Design Validation Stimulus [p.
173]
 Turkewadikar, S.
 Circuit and DFT Techniques
for Robust and Low Cost Qualification of a MixedSignal SoC with
Integrated Power Management System [p. 551]
 Valgimigli, F.
 An Integrated Platform for
Advanced Diagnostics [p. 1454]
 van Beurden, M.
 Test Time Reduction in
Analogue/MixedSignal Devices by Defect Oriented Testing: An Industrial
Example [p. 371]
 van der Kolk, K.J.
 Fast Statistical Analysis of
RC Nets Subject to Manufacturing Variabilities [p. 32]
 van der Meijs, N.
 Fast Statistical Analysis of
RC Nets Subject to Manufacturing Variabilities [p. 32]
 Pseudo Circuit Model for
Representing Uncertainty in Waveforms [p. 1521]
 Van der Plas, G.
 An Analytical Compact Model
for Estimation of Stress in Multiple ThroughSilicon Via Configurations
[p. 505]
 van der Wolf, P.
 SoC Infrastructures for
Predictable System Integration [p. 857]
 Vasicek, Z.
 A Global Postsynthesis
Optimization Method for Combinational Circuits [p. 1525]
 Vasudevan, S.
 Towards Coverage Closure:
Using Goldmine Assertions for Generating Design Validation Stimulus [p.
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Efficient Validation Input Generation in RTL by Hybridized Source Code Analysis
[p. 1596]
 Vatajelu, E.I.
 Robustness Analysis of 6T
SRAMs in Memory Retention Mode under PVT Variations [p. 980]
 Veneris, A.
 Automated Debugging of
SystemVerilog Assertions [p. 323]
 Venkatesan, R.
 VESPA: Variability Emulation
for SystemonChip Performance Analysis [p. 2]
 Venugopalan, S.
 SAMURAI: An Accurate Method
for Modeling and Simulating NonStationary Random Telegraph Noise in
SRAMs [p. 1113]
 Vera, X.
 Architectures for Online
Error Detection and Recovery in Multicore Processors [p. 533]
 Verbauwhede, I.
 Lowcost Fault Detection
Method for ECC Using Montgomery Powering Ladder [p. 1016]
 Verdant, A.
 Smart Imagers of the Future
[p. 437]
 Vermeulen, B.
 Optimal Scheduling of
Switched FlexRay Networks [p. 926]
 Vidal, J.
 Dynamic Applications on
Reconfigurable Systems: From UML Model Design to FPGAs Implementation
[p. 1208]
 Vijayaraghavan, R.C.
 Circuit and DFT Techniques
for Robust and Low Cost Qualification of a MixedSignal SoC with
Integrated Power Management System [p. 551]
 Visintainer, F.
 Sensor Networks on the Car:
State of the Art and Future Challenges [p. 1030]
 Vissers, K.
 Building Realtime HDTV
Applications in FPGAs Using Processors, AXI Interfaces and High Level
Synthesis Tools [p. 848]
 Vivet, P.
 3D Embedded MultiCore:
Some Perspectives [p. 1327]
 von Hanxleden, R.
 Compiling SyncCharts to
Synchronous C [p. 563]
 Vrudhula, S.
 Reliabilityaware Thermal
Management for Hard Realtime Applications on Multicore Processors [p.
137]
 Wachs, M.
 Intermediate Representations
for Controllers in Chip Generators [p. 1394]
 Wagner, F.R.
 Improving the Efficiency of
a Hardware Transactional Memory on an NoCbased MPSoC [p. 1168]
 Wagner, I.
 Distributed Hardware Matcher
Framework for SoC Survivability [p. 305]
 Wagner, M.
 Powering and Communicating
with mmsize Implants [p. 722]
 Wang, C.
 Evaluating the Potential of
Graphics Processors for High Performance Embedded Computing [p. 709]
 Wang, G.
 Coordinate StripMining and
Kernel Fusion to Lower Power Consumption on GPU [p. 1216]
 Wang, K.
 Optimization of Stateful
Hardware Acceleration in Hybrid Architectures [p. 567]
 Wang, L.
 Wireless Communication and
Energy Harvesting in Automobiles [p. 1042]
 Accelerated Simulation of
Tunable Vibration Energy Harvesting Systems Using a Linearised
StateSpace Technique [p. 1267]
 Wang, L.C.
 Multidimensional Parametric
Test Set Optimization of Wafer Probe Data for Predicting in Field
Failures and Setting Tighter Test Limits [p. 794]
 Wang, P.C.
 DOM: A
DataDependencyOriented Modeling Approach for Efficient Simulation of
OS Preemptive Scheduling [p. 335]
 Wang, P.Y.
 An AllDigital BuiltIn
SelfTest Technique for Transfer Function Characterization of RF PLLs
[p. 359]
 Wang, X.
 HighTemperature
(>500°C) Reconfigurable Computing Using Silicon Carbide NEMS
Switches [p. 1065]
 Wang, Y.
 An EnduranceEnhanced Flash
Translation Layer via Reuse for NAND Flash Memory Storage Systems [p.
14]
 Gemma in April: A
MatrixLike Parallel Programming Architecture on OpenCL [p. 703]
 BatterySupercapacitor
Hybrid System for HighRate Pulsed Load Applications [p. 875]
 FlexMemory: Exploiting and
Managing Abundant OffChip Optical Bandwidth [p. 968]
 Modeling Circuit Performance
Variations Due to Statistical Variability: Monte Carlo Static Timing
Analysis [p. 1537]
 Wang, Z.
 An Approach to Improve
Accuracy of SourceLevel TLMs of Embedded Software [p. 216]
 A Specialized LowCost
Vectorized Loop Buffer for Embedded Processors [p. 1200]
 Wang, Z.C.
 A New Architecture for Power
Network in 3D IC [p. 401]
 Wanner, L.
 VariabilityAware Duty Cycle
Scheduling in Long Running Embedded Sensing Systems [p. 131]
 Watanabe, Y.
 Realistic
PerformanceConstrained Pipelining in HighLevel Synthesis [p. 1382]
 Weddell, A.S.
 Ultra LowPower Photovoltaic
MPPT Technique for Indoor and Outdoor Wireless Sensor Nodes [p. 905]
 Accelerated Simulation of
Tunable Vibration Energy Harvesting Systems Using a Linearised
StateSpace Technique [p. 1267]
 Wedler, M.
 STABLE: A New QFBV SMT
Solver for Hard Verification Problems combining Boolean Reasoning with
Computer Algebra [p. 155]
 Weger, A.J.
 Early Chip Planning Cockpit
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 Wehn, N.
 Design Space Exploration for
3DStacked DRAMs [p. 389]
 Weis, C.
 Design Space Exploration for
3DStacked DRAMs [p. 389]
 Welp, T.
 An Approach for Dynamic
Selection of Synthesis Transformations Based on Markov Decision
Processes [p. 1533]
 Wen, X.
 TransitionTimeRelation
Based CaptureSafety Checking for AtSpeed Scan Test Generation [p. 895]
 Weng, C.C.
 BlackBox Leakage Power
Modeling for Cell Library and SRAM Compiler [p. 637]
 Weng, T.
 Understanding the Role of
Buildings in a Smart Microgrid [p. 1224]
 Werthimer, D.
 Powering and Communicating
with mmsize Implants [p. 722]
 Wiegand, T.
 Architecture and
FPGAImplementation of a High Throughput K^{+}Best Detector [p.
240]
 Wille, R.
 Verifying Dynamic Aspects of
UML Models [p. 1077]
 Determining the Minimal
Number of Lines for Large Reversible Circuits [p. 1204]
 Winemberg, L.
 Multidimensional Parametric
Test Set Optimization of Wafer Probe Data for Predicting in Field
Failures and Setting Tighter Test Limits [p. 794]
 Wink, T.
 MARC II: A Parametrized
Speculative MultiPorted Memory Subsystem for Reconfigurable Computers
[p. 1352]
 Winter, M.
 Guaranteed Service Virtual
Channel Allocation in NoCs for RunTime Task Scheduling [p. 419]
 Winterholer, M.
 Embedded Software Debug and
Test  Needs and Requirements for Innovations in Debugging [p. 721]
 Wittmann,
R.

Generator Based Approach for Analog Circuit and Layout Design and Optimization
[p. 1675]
 Woh, M.
 Low Power Interconnects for
SIMD Computers [p. 600]
 Wolff, F.G.
 HighTemperature
(>500°C) Reconfigurable Computing Using Silicon Carbide NEMS
Switches [p. 1065]
 Wong, N.
 A BlockDiagonal Structured
Model Reduction Scheme for Power Grid Networks [p. 44]
 Wong, S.
 A New Reconfigurable
ClockGating Technique for Low Power SRAMBased FPGAs [p. 752]
 Targeting Code Diversity
with RunTime Adjustable IssueSlots in a Chip Multiprocessor [p. 1358]
 Wong, W.F.
 A UML 2Based
Hardware/Software CoDesign Framework for Body Sensor Network
Applications [p. 1505]
 Wright,
P.K.
 What Does the Power Industry
Need from the EDA Industry and What Is the EDA Industry Doing About It?
[p. 1541]
 Wu, C.A.
 Speeding up MPSoC Virtual
Platform Simulation by Ultra Synchronization Checking Method [p. 353]
 Wu, D.
 Gemma in April: A
MatrixLike Parallel Programming Architecture on OpenCL [p. 703]
 Wu, K.
 LOEDAR: A Low Cost Error
Detection and Recovery Scheme for ECC [p. 1010]
 Wu,
K.C.

AgingAware Timing Analysis and Optimization Considering Path Sensitization
[p. 1572]
 Wu, M.H.
 DOM: A
DataDependencyOriented Modeling Approach for Efficient Simulation of
OS Preemptive Scheduling [p. 335]
 CycleCountAccurate
Processor Modeling for Fast and Accurate SystemLevel Simulation [p.
341]
 A SharedVariableBased
Synchronization Approach to Efficient Cache Coherence Simulation for
MultiCore Systems [p. 347]
 Wu, T.
 Gemma in April: A
MatrixLike Parallel Programming Architecture on OpenCL [p. 703]
 Wu, T.H.
 PowerDriven Global Routing
for MultiSupply Voltage Domains [p. 443]
 Wu, Y.
 Empirical Design Bugs
Prediction for Verification [p. 161]
 Wunderlich, H.J.
 SATBased Fault Coverage
Evaluation in the Presence of Unknown Values [p. 1303]
 Xia, F.
 RunTime Deadlock Detection
in NetworksonChip Using Coupled Transitive Closure Networks [p. 497]
 Xiao, N.
 A Specialized LowCost
Vectorized Loop Buffer for Embedded Processors [p. 1200]
 Xie, X.
 Evaluating the Potential of
Graphics Processors for High Performance Embedded Computing [p. 709]
 Xie, Y.
 An EnergyEfficient 3D CMP
Design with FineGrained Voltage Scaling [p. 539]
 Design Implications of
MemristorBased RRAM CrossPoint Structures [p. 734]
 Xing, Y.
 Test Time Reduction in
Analogue/MixedSignal Devices by Defect Oriented Testing: An Industrial
Example [p. 371]
 Xu, C.
 Design Implications of
MemristorBased RRAM CrossPoint Structures [p. 734]
 Xu, H.
 Analytical Heat Transfer
Model for Thermal ThroughSilicon Vias [p. 395]
 Xu, N.
 Gemma in April: A
MatrixLike Parallel Programming Architecture on OpenCL [p. 703]
 Xu, Q.
 On Multiplexed Signal
Tracing for PostSilicon Debug [p. 685]
 Xue, C.J.
 Register Allocation for
Simultaneous Reduction of Energy and Peak Temperature on Registers [p.
20]
 Towards Energy Efficient
Hybrid OnChip Scratch Pad Memory with NonVolatile Memory [p. 746]
 Xue, L.
 Floorplanning Exploration
and Performance Evaluation of a New NetworkonChip [p. 625]
 Yakovlev, A.
 RunTime Deadlock Detection
in NetworksonChip Using Coupled Transitive Closure Networks [p. 497]
 EnergyModulated Computing
[p. 1340]
 Redressing Timing Issues for
SpeedIndependent Circuits in Deep Submicron Age [p. 1376]
 Yamato, Y.
 TransitionTimeRelation
Based CaptureSafety Checking for AtSpeed Scan Test Generation [p. 895]
 Yan, C.
 An Efficient Algorithm for
MultiDomain Clock Skew Scheduling [p. 1364]
 Yan, J.T.
 ObstacleAware
MultipleSource Rectilinear Steiner Tree with Electromigration and
IRDrop Avoidance [p. 449]
 TimingConstrained I/O
Buffer Placement for FlipChip Designs [p. 619]
 Yang, B.
 A ClockGating Based Capture
Power Droop Reduction Methodology for AtSpeed Scan Testing [p. 197]
 Yang, C.
 Frugal but Flexible
Multicore Topologies in Support of Resource VariationDriven Adaptivity
[p. 1255]
 Yang, H.
 WorstCase Temperature
Analysis for RealTime Systems [p. 631]
 Gemma in April: A
MatrixLike Parallel Programming Architecture on OpenCL [p. 703]
 Yang, J.
 Proactive Recovery for BTI
in HighK SRAM Cells [p. 992]
 Yang, S.
 A New Distributed
EventDriven GateLevel HDL Simulation by Accurate Prediction [p. 547]
 Case Study: Alleviating
Hotspots and Improving Chip Reliability via Carbon Nanotube Thermal
Interface [p. 1071]

Temporal Parallel Simulation: A Fast GateLevel HDL Simulation Using Higher Level Models
[p. 1584]
 Yang, X.
 Robust 6T Si Tunneling
Transistor SRAM Design [p. 740]
 Ye, J.
 On Diagnosis of Multiple
Faults Using Compressed Responses [p. 679]
 Yeh, C.T.
 A UML 2Based
Hardware/Software CoDesign Framework for Body Sensor Network
Applications [p. 1505]
 Yeh, Y.F.
 Speeding up MPSoC Virtual
Platform Simulation by Ultra Synchronization Checking Method [p. 353]
 Yeric, G.
 Correlating Models and
Silicon for Improved Parametric Yield [p. 1159]
 Yeung, P.
 Challenges in Designing High
Speed Memory Subsystem for Mobile Applications [p. 509]
 Yi, W.
 EnergyEfficient Scheduling
of RealTime Tasks on ClusterBased Multicores [p. 1135]
 Yip, T.G.
 Challenges in Designing High
Speed Memory Subsystem for Mobile Applications [p. 509]
 Yoo, S.
 A Novel Tag Access Scheme
for Low Power L2 Cache [p. 655]
 A Quantitative Analysis of
Performance Benefits of 3D Die Stacking on Mobile and Embedded SoC [p.
1333]
 Yoon, J.W.
 I^{2}CRF:
Incremental Interconnect Customization for Embedded Reconfigurable
Fabrics [p. 1346]
 Yu, C.C.
 Trigonometric Method to
Handle Realistic Error Probabilities in Logic Circuits [p. 64]
 Yu, H.
 Optimization of Stateful
Hardware Acceleration in Hybrid Architectures [p. 567]
 Yu, K.
 A HighLevel Analytical
Model for Application Specific CMP Design Exploration [p. 1095]
 Zadegan, F.G.
 Design Automation for IEEE
P1687 [p. 1412]
 Zafalon, R.
 Solid State Photodetectors
for Nuclear Medical Imaging Applications [p. 511]
 Zahedi, S.
 VariabilityAware Duty Cycle
Scheduling in Long Running Embedded Sensing Systems [p. 131]
 Zaidi, Y.
 Simulation Based Tuning of
System Specification [p. 1273]
 Zaki, M.H.
 Ensuring Correctness of
Analog Circuits in Presence of Noise and Process Variations Using
Pattern Matching [p. 1188]
 Zarrineh, K.
 Feedback Based Droop
Mitigation [p. 879]
 Zatt, B.
 MultiLevel Pipelined
Parallel Hardware Architecture for High Throughput Motion and Disparity
Estimation in Multiview Video Coding [p. 1448]
 Zebelein, C.
 A RuleBased Static Dataflow
Clustering Algorithm for Efficient Embedded Software Synthesis [p. 521]
 Zeng, X.
 An Efficient Algorithm for
MultiDomain Clock Skew Scheduling [p. 1364]
 Zergainoh, N.E.
 A faultTolerant
DeadlockFree Adaptive Routing for On Chip Interconnects [p. 909]

Eliminating Speed Penalty in ECC Protected Memories
[p. 1614]
 Zhai, A.
 Enabling Improved Power
Management in Multicore Processors through Clustered DVFS [p. 293]
 Zhang, L.
 FlexMemory: Exploiting and
Managing Abundant OffChip Optical Bandwidth [p. 968]
 Zhang, W.
 Case Study: Alleviating
Hotspots and Improving Chip Reliability via Carbon Nanotube Thermal
Interface [p. 1071]
 Zhang, X.
 Gemma in April: A
MatrixLike Parallel Programming Architecture on OpenCL [p. 703]

RON: An OnChip Ring Oscillator Network for Hardware Trojan Detection
[p. 1638]
 Zhang, Y.
 Floorplanning Exploration
and Performance Evaluation of a New NetworkonChip [p. 625]
 Proactive Recovery for BTI
in HighK SRAM Cells [p. 992]
 Zhang, Z.
 A BlockDiagonal Structured
Model Reduction Scheme for Power Grid Networks [p. 44]

A ConfidenceDriven Model for ErrorResilient Computing
[p. 1608]
 Zhao, C.
 An Extension to SystemCA to
Support MixedTechnology Systems with Distributed Components [p. 1279]
 Zhao, J.
 An EnergyEfficient 3D CMP
Design with FineGrained Voltage Scaling [p. 539]
 Zhi, Y.
 An Efficient Algorithm for
MultiDomain Clock Skew Scheduling [p. 1364]
 Zhou, H.
 A HighLevel Analytical
Model for Application Specific CMP Design Exploration [p. 1095]
 An Efficient Algorithm for
MultiDomain Clock Skew Scheduling [p. 1364]
 Zhou, H.
 Integrated Circuit White
Space Redistribution for Temperature Optimization [p. 613]
 Zhu, H.
 An Efficient Algorithm for
MultiDomain Clock Skew Scheduling [p. 1364]
 Zhu, M.
 Evaluating the Potential of
Graphics Processors for High Performance Embedded Computing [p. 709]
 Zhuge, Q.
 Towards Energy Efficient
Hybrid OnChip Scratch Pad Memory with NonVolatile Memory [p. 746]
 Ziermann, T.
 DynOAA  Dynamic
Offset Adaptation Algorithm for Improving Response Times of CAN Systems
[p. 269]
 Zimmerling, M.
 XSENSE: Sensing in Extreme
Environments [p. 1460]
 Ziv,
A.

A Unified Methodology for PreSilicon Verification and PostSilicon Validation
[p. 1590]
 Zjajo, A.
 Pseudo Circuit Model for
Representing Uncertainty in Waveforms [p. 1521]
 Zuber, P.
 Variability Aware Modeling
for Yield Enhancement of SRAM and Logic [p. 1153]
 Zukoski,
A.

Reliabilitydriven Don't Care Assignment for Logic Synthesis
[p. 1560]
 Zuo, Q.
 Floorplanning Exploration
and Performance Evaluation of a New NetworkonChip [p. 625]
 Zwolinski, M.
 Modeling Circuit Performance
Variations Due to Statistical Variability: Monte Carlo Static Timing
Analysis [p. 1537]