DATE 2011, AUTHOR INDEX

DATE 2011 AUTHOR INDEX

[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [V] [W] [X] [Y] [Z]

Aadithya, K.V.: SAMURAI: An Accurate Method for Modeling and Simulating Non-Stationary Random Telegraph Noise in SRAMs [p. 1113]
Abadir, M.S.: Multidimensional Parametric Test Set Optimization of Wafer Probe Data for Predicting in Field Failures and Setting Tighter Test Limits [p. 794]
Abdallah, R.A.: Timing Error Statistics for Energy-Efficient Robust DSP Systems [p. 285]
Abelmann, L.: Buffering Implications for the Design Space of Streaming MEMS Storage [p. 253]
Aboulhamid, E.M.: Multi-Granularity Thermal Evaluation of 3D MPSoC Architectures [p. 575]
Acquaviva, A.: An Efficient On-Line Task Allocation Algorithm for QoS and Energy Efficiency in Multicore Multimedia Platforms [p. 100]; System Level Techniques to Improve Reliability in High Power Microcontrollers for Automotive Applications [p. 1123]
Adir, A.: A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation [p. 1590]
Adve, S.V.: Architectures for Online Error Detection and Recovery in Multicore Processors [p. 533]
Afzali-Kusha, A.: Timing Variation-Aware Custom Instruction Extension Technique [p. 1517]
Agarwal, Y.: Understanding the Role of Buildings in a Smart Microgrid [p. 1224]
Agyekum, M.Y.: A Delay-Insensitive Bus-Invert Code and Hardware Support for Robust Asynchronous Global Communication [p. 1370]
Ahmadian, S.N.: Soft Error Rate Estimation of Digital Circuits in the Presence of Multiple Event Transients (METs) [p. 70]
Ahmed, W.: Minority-Game-Based Resource Allocation for Run-Time Reconfigurable Multi-Core Processors [p. 1261]; mRTS: Run-Time System for Reconfigurable Processors with Multi-Grained Instruction-Set Extensions [p. 1554]
Ahn, J.H.: A Quantitative Analysis of Performance Benefits of 3D Die Stacking on Mobile and Embedded SoC [p. 1333]
Aitken, R.: Correlating Models and Silicon for Improved Parametric Yield [p. 1159]; Analytical Model for SRAM Dynamic Write-Ability Degradation Due to Gate Oxide Breakdown [p. 1172]
Aitken, R.C.: Dynamic Write Limited Minimum Operating Voltage for Nanoscale SRAMs [p. 467]
Akesson, B.: Architectures and Modeling of Predictable Memory Controllers for Improved System Integration [p. 851]
Akin, A.: A High-Performance Parallel Implementation of the Chambolle Algorithm [p. 1436]
Al Faruque, M.A.: Dynamic Thermal Management in 3D Multi-Core Architecture through Run-Time Adaptation [p. 299]; CARAT: Context-Aware Runtime Adaptive Task Migration for Multi Core Architectures [p. 515]
Alacoque, L.: Smart Imagers of the Future [p. 437]
Al-Dujaily, R.: Run-Time Deadlock Detection in Networks-on-Chip Using Coupled Transitive Closure Networks [p. 497]
Al-Hashimi, B.M.: Sub-Clock Power-Gating Technique for Minimising Leakage Power During Active Mode [p. 106]; Ultra Low-Power Photovoltaic MPPT Technique for Indoor and Outdoor Wireless Sensor Nodes [p. 905]; Accelerated Simulation of Tunable Vibration Energy Harvesting Systems Using a Linearised State-Space Technique [p. 1267]
Ali, S.S.: Multi-Level Attacks: An Emerging Security Concern for Cryptographic Hardware [p. 1176]
Al-Khayat, R.: A Flexible High Throughput Multi-ASIP Architecture for LDPC and Turbo Decoding [p. 228]
Almeida, G.M.: Achieving Composability in NoC-Based MPSoCs Through QoS Management at Software Level [p. 407]
Alorda, B.: Stability Optimization of Embedded 8T SRAMs Using Word-Line Voltage Modulation [p. 986]
Altmeyer, S.: Precise WCET Calculation in Highly Variant Real-Time Systems [p. 920]
Amende, T.: Compiling SyncCharts to Synchronous C [p. 563]
Amory, A.M.: Evaluating Energy Consumption of Homogeneous MPSoCs Using Spare Tiles [p. 1164]
Andalam, S.: Pruning Infeasible Paths for Tight WCRT Analysis of Synchronous Programs [p. 204]
Andreou, A.G.: A High-Level Analytical Model for Application Specific CMP Design Exploration [p. 1095]
Anjam, F.: Targeting Code Diversity with Run-Time Adjustable Issue-Slots in a Chip Multiprocessor [p. 1358]
Ansaloni, G.: Slack-Aware Scheduling on Coarse Grained Reconfigurable Arrays [p. 1513]
Apte, C.: Variability-Aware Duty Cycle Scheduling in Long Running Embedded Sensing Systems [p. 131]
Aristizabal, J.: 2D and 3D Integration with Organic and Silicon Electronics [p. 899]
Arslan, B.: Adaptive Test Optimization through Real Time Learning of Test Effectiveness [p. 1430]
Asadi, H.: Soft Error Rate Estimation of Digital Circuits in the Presence of Multiple Event Transients (METs) [p. 70]; ScTMR: A Scan Chain-Based Error Recovery Technique for TMR Systems in Safety-Critical Applications [p. 289]
Asadinia, M.: Supporting Non-Contiguous Processor Allocation in Mesh-Based CMPs Using Virtual Point-to-Point Links [p. 413]
Asenov, A.: Statistical Aspects of NBTI/PBTI and Impact on SRAM Yield [p. 1480]; Modeling Circuit Performance Variations Due to Statistical Variability: Monte Carlo Static Timing Analysis [p. 1537]
Asenov, P.: Modeling Circuit Performance Variations Due to Statistical Variability: Monte Carlo Static Timing Analysis [p. 1537]
Aso, M.: Transition-Time-Relation Based Capture-Safety Checking for At-Speed Scan Test Generation [p. 895]
Atienza, D.: A Real-Time Compressed Sensing-Based Personal Electrocardiogram Monitoring System [p. 824]; A High-Performance Parallel Implementation of the Chambolle Algorithm [p. 1436]; Towards Thermally-Aware Design of 3D MPSoCs with Inter-Tier Cooling [p. 1466]
Avresky, D.: A fault-Tolerant Deadlock-Free Adaptive Routing for On Chip Interconnects [p. 909]
Ayala Garcia, I.N.: Accelerated Simulation of Tunable Vibration Energy Harvesting Systems Using a Linearised State-Space Technique [p. 1267]
Azaïs, F.: An Electrical Test Method for MEMS Convective Accelerometers: Development and Evaluation [p. 806]

Bacivarov, I.: Worst-Case Temperature Analysis for Real-Time Systems [p. 631]
Baghdadi, A.: A Flexible High Throughput Multi-ASIP Architecture for LDPC and Turbo Decoding [p. 228]; A Low Complexity Stopping Criterion for Reducing Power Consumption in Turbo Decoders [p. 649]
Bai, L.S.: Simplified Programming of Faulty Sensor Networks via Code Transformation and Run-Time Interval Computation [p. 88]; Automated Construction of Fast and Accurate System-Level Models for Wireless Sensor Networks [p. 1083]
Baiocchi, J.A.: Demand Code Paging for NAND Flash in MMU-less Embedded Systems [p. 527]
Balani, R.: Variability-Aware Duty Cycle Scheduling in Long Running Embedded Sensing Systems [p. 131]
Balasubramanian, L.: Circuit and DFT Techniques for Robust and Low Cost Qualification of a Mixed-Signal SoC with Integrated Power Management System [p. 551]
Ballan, O.: Fault Grading of Software-Based Self-Test Procedures for Dependable Automotive Applications [p. 513]
Bampi, S.: Multi-Level Pipelined Parallel Hardware Architecture for High Throughput Motion and Disparity Estimation in Multiview Video Coding [p. 1448]
Banga, M.: Design-for-Test Methodology for Non-Scan At-Speed Testing [p. 191]
Barceló, S.: An Efficient and Scalable STA Tool with Direct Path Estimation and Exhaustive Sensitization Vector Exploration for Optimal Delay Computation [p. 1602]
Bartic, C.: Systematic Design of a Programmable Low-Noise CMOS Neural Interface for Cell Activity Recording [p. 818]
Bartolini, A.: A Distributed and Self-Calibrating Model-Predictive Controller for Energy and Thermal Management of High-Performance Multicores [p. 830]
Bathen, L.A.D.: E-RoC: Embedded Raids-on-Chip for Low Power Distributed Dynamically Managed Reliable Memories [p. 1141]
Bauer, L.: Minority-Game-Based Resource Allocation for Run-Time Reconfigurable Multi-Core Processors [p. 1261]; mRTS: Run-Time System for Reconfigurable Processors with Multi-Grained Instruction-Set Extensions [p. 1554]
Becker, B.: Integration of Orthogonal QBF Solving Techniques [p. 149]; Hyper-Graph Based Partitioning to Reduce DFT Cost for Pre-Bond 3D-IC Testing [p. 1424]
Becker, J.: Fast Startup for Spartan-6 FPGAs Using Dynamic Partial Reconfiguration [p. 1542]
Beerel, P.A.: An Area-Efficient Multi-Level Single-Track Pipeline Template [p. 1509]
Behrend, J.: Scalable Hybrid Verification for Embedded Software [p. 179]
Bekooij, M.J.G.: Parallelization of While Loops in Nested Loop Programs for Shared-Memory Multiprocessor Systems [p. 697]; Resynchronization of Cyclo-Static Dataflow Graphs [p. 1315]
Beltrame, G.: Multi-Granularity Thermal Evaluation of 3D MPSoC Architectures [p. 575]; A Multi-Objective Decision-Theoretic Exploration Algorithm for Platform-Based Design [p. 1192]
Benini, L.: An Efficient On-Line Task Allocation Algorithm for QoS and Energy Efficiency in Multicore Multimedia Platforms [p. 100]; Design Space Exploration for 3D-Stacked DRAMs [p. 389]; A Fully-Synthesizable Single-Cycle Interconnection Network for Shared-L1 Processor Clusters [p. 491]; ReliNoC: A Reliable Network for Priority-Based On-Chip Communication [p. 667]; A Distributed and Self-Calibrating Model-Predictive Controller for Energy and Thermal Management of High-Performance Multicores [p. 830]; An Effective Multi-Source Energy Harvester for Low Power Applications [p. 836]
Beretta, I.: A High-Performance Parallel Implementation of the Chambolle Algorithm [p. 1436]
Berger, C.: Formal Specification and Systematic Model-Driven Testing of Embedded Automotive Systems [p. 118]
Bergman, K.: VANDAL: A Tool for the Design Specification of Nanophotonic Networks [p. 782]
Berkelaar, M.: Pseudo Circuit Model for Representing Uncertainty in Waveforms [p. 1521]
Bernard, C.: A Low-Power VLIW Processor for 3GPP-LTE Complex Numbers Processing [p. 234]
Bernardi, P.: Fault Grading of Software-Based Self-Test Procedures for Dependable Automotive Applications [p. 513]
Bernicot, C.: Mathematical Approach Based on a "Design of Experiment" to Simulate Process Variations [p. 1486]
Bertacco, V.: ReliNoC: A Reliable Network for Priority-Based On-Chip Communication [p. 667]
Bertels, K.: Loop Distribution for K-Loops on Reconfigurable Architectures [p. 1548]
Bertozzi, D.: Exploiting Network-on-Chip Structural Redundancy for a Cooperative and Scalable Built-In Self-Test Architecture [p. 661]
Beserra, G.S.: System-Level Modeling of a Mixed-Signal System on Chip for Wireless Sensor Networks [p. 1501]
Beutel, J.: X-SENSE: Sensing in Extreme Environments [p. 1460]
Beyne, E.: An Analytical Compact Model for Estimation of Stress in Multiple Through-Silicon Via Configurations [p. 505]
Beyranvand Nejad, A.: An FPGA Bridge Preserving Traffic Quality of Service for On-Chip Network-Based Systems [p. 425]
Bhattacharya, B.B.: Waste-Aware Dilution and Mixing of Biochemical Samples with Digital Microfluidic Biochips [p. 1059]
Bhunia, S.: High-Temperature (>500°C) Reconfigurable Computing Using Silicon Carbide NEMS Switches [p. 1065]; Multi-Level Attacks: An Emerging Security Concern for Cryptographic Hardware [p. 1176]
Bi, Y.: Fast Statistical Analysis of RC Nets Subject to Manufacturing Variabilities [p. 32]
Bijlsma, T.: Parallelization of While Loops in Nested Loop Programs for Shared-Memory Multiprocessor Systems [p. 697]
Bilgic, A.: Low Power Smart Industrial Control [p. 595]
Biswas, A.: Architectures for Online Error Detection and Recovery in Multicore Processors [p. 533]
Blaauw, D.: Low Power Interconnects for SIMD Computers [p. 600]; A Confidence-Driven Model for Error-Resilient Computing [p. 1608]
Bocca, A.: Energy Analysis Methods and Tools For Modelling and Optimizing Tyre Systems [p. 1121]
Bock, S.: Impact of Process Variation on Endurance Algorithms for Wear-Prone Memories [p. 962]
Boero, C.: An Integrated Platform for Advanced Diagnostics [p. 1454]
Bogdan, P.: Sustainability through Massively Integrated Computing: Are We Ready to Break the Energy Efficiency Wall for Single-Chip Platforms? [p. 1656]
Boghrati, B.: A Scaled Random Walk Solver for Fast Power Grid Analysis [p. 38]
Bois, G.: Optical Ring Network-on-Chip (ORNoC): Architecture and Design Methodology [p. 788]
Bonanno, A.: Energy Analysis Methods and Tools For Modelling and Optimizing Tyre Systems [p. 1121]
Bonhomme, Y.: Error Prediction Based on Concurrent Self-Test and Reduced Slack Time [p. 1626]
Bonnoit, T.: Eliminating Speed Penalty in ECC Protected Memories [p. 1614]
Boos, V.: Strategies for Initial Sizing and Operating Point Analysis of Analog Circuits [p. 1672]
Borhani, N.: Towards Thermally-Aware Design of 3D MPSoCs with Inter-Tier Cooling [p. 1466]
Bota, S.: Stability Optimization of Embedded 8T SRAMs Using Word-Line Voltage Modulation [p. 986]; An Efficient and Scalable STA Tool with Direct Path Estimation and Exhaustive Sensitization Vector Exploration for Optimal Delay Computation [p. 1602]
Brady, B.A.: Counterexample-Guided SMT-Driven Optimal Buffer Sizing [p. 329]
Braun, L.: Fast Startup for Spartan-6 FPGAs Using Dynamic Partial Reconfiguration [p. 1542]
Bringmann, O.: Fast and Accurate Resource Conflict Simulation for Performance Analysis of Multi-Core Systems [p. 210]
Brown, A.R.: Statistical Aspects of NBTI/PBTI and Impact on SRAM Yield [p. 1480]
Brown, J.: Power Management Trends in Portable Consumer Applications [p. 1048]
Brunelli, D.: An Effective Multi-Source Energy Harvester for Low Power Applications [p. 836]
Bruns, F.: Low Power Smart Industrial Control [p. 595]
Brunschwiler, T.: Towards Thermally-Aware Design of 3D MPSoCs with Inter-Tier Cooling [p. 1466]
Bruschi, F.: An Efficient Quantum-Dot Cellular Automata Adder [p. 1220]
Buchli, B.: X-SENSE: Sensing in Extreme Environments [p. 1460]
Buckl, C.: A Workflow for Runtime Adaptive Task Allocation on Heterogeneous MPSoCs [p. 1129]
Burger, T.: A Circuit Technology Platform for Medical Data Acquisition and Communication [p. 1472]
Buttrick, M.: On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs [p. 1418]

Cabodi, G.: Interpolation Sequences Revisited [p. 317]; Optimized Model Checking of Multiple Properties [p. 543]
Cacciari, M.: A Distributed and Self-Calibrating Model-Predictive Controller for Energy and Thermal Management of High-Performance Multicores [p. 830]
Calhoun, B.: Reducing the Cost of Redundant Execution in Safety-Critical Systems Using Relaxed Dedication [p. 1249]
Calhoun, B.H.: Dynamic Write Limited Minimum Operating Voltage for Nanoscale SRAMs [p. 467]
Calimera, A.: Partitioned Cache Architectures for Reduced NBTI-Induced Aging [p. 938]; Moving to Green ICT: From Stand-Alone Power-Aware IC Design to an Integrated Approach to Energy Efficient Design of Heterogeneous Electronic Systems [p. 1127]
Camargo da Costa, J.: System-Level Modeling of a Mixed-Signal System on Chip for Wireless Sensor Networks [p. 1501]
Caprara, A.: An Efficient On-Line Task Allocation Algorithm for QoS and Energy Efficiency in Multicore Multimedia Platforms [p. 100]
Carara, E.: Achieving Composability in NoC-Based MPSoCs Through QoS Management at Software Level [p. 407]
Carli, D.: An Effective Multi-Source Energy Harvester for Low Power Applications [p. 836]
Carloni, L.P.: VANDAL: A Tool for the Design Specification of Nanophotonic Networks [p. 782]
Carlsson, G.: Design Automation for IEEE P1687 [p. 1412]
Carrara, S.: An Integrated Platform for Advanced Diagnostics [p. 1454]
Carro, L.: A New Reconfigurable Clock-Gating Technique for Low Power SRAM-Based FPGAs [p. 752]
Cassidy, A.: A High-Level Analytical Model for Application Specific CMP Design Exploration [p. 1095]
Chaix, F.: A fault-Tolerant Deadlock-Free Adaptive Routing for On Chip Interconnects [p. 909]
Chakrabarty, K.: Waste-Aware Dilution and Mixing of Biochemical Samples with Digital Microfluidic Biochips [p. 1059]
Chakraborty, K.: Topologically Homogeneous Power-Performance Heterogeneous Multicore Systems [p. 125]
Chakraborty, R.S.: Multi-Level Attacks: An Emerging Security Concern for Cryptographic Hardware [p. 1176]
Chakraborty, S.: FlexRay Switch Scheduling - A Networking Concept for Electric Vehicles [p. 76]; Re-Engineering Cyber-Physical Control Applications for Hybrid Communication Protocols [p. 914]
Chan, J.: VANDAL: A Tool for the Design Specification of Nanophotonic Networks [p. 782]
Chan, T.-B.: On the Efficacy of NBTI Mitigation Techniques [p. 932]
Chandra, V.: Dynamic Write Limited Minimum Operating Voltage for Nanoscale SRAMs [p. 467]; Analytical Model for SRAM Dynamic Write-Ability Degradation Due to Gate Oxide Breakdown [p. 1172]
Chang, C.-W.: Formal Reset Recovery Slack Calculation at the Register Transfer Level [p. 571]
Chang, H.-M.: An All-Digital Built-In Self-Test Technique for Transfer Function Characterization of RF PLLs [p. 359]
Chang, K.-H.: Formal Reset Recovery Slack Calculation at the Register Transfer Level [p. 571]
Chang, N.: Battery-Supercapacitor Hybrid System for High-Rate Pulsed Load Applications [p. 875]
Chang, S.-C.: Thermal-Aware On-Line Task Allocation for 3D Multi-Core Processor Throughput Optimization [p. 8]
Chang, X.: Optimization of Stateful Hardware Acceleration in Hybrid Architectures [p. 567]
Chen, C.-H.: A Confidence-Driven Model for Error-Resilient Computing [p. 1608]
Chen, C.-I.: Architectural Exploration of 3D FPGAs towards a Better Balance between Area and Delay [p. 587]
Chen, D.: Powering and Communicating with mm-size Implants [p. 722]
Chen, H.-M.: On Routing Fixed Escaped Boundary Pins for High Speed Boards [p. 461]
Chen, H.-T.: A New Architecture for Power Network in 3D IC [p. 401]
Chen, J.-J.: Worst-Case Temperature Analysis for Real-Time Systems [p. 631]; Black-Box Leakage Power Modeling for Cell Library and SRAM Compiler [p. 637]
Chen, L.-C.: Cycle-Count-Accurate Processor Modeling for Fast and Accurate System-Level Simulation [p. 341]
Chen, M.: Decision Ordering Based Property Decomposition for Functional Test Generation [p. 167]; Diagnosing Scan Chain Timing Faults through Statistical Feature Analysis of Scan Images [p. 185]
Chen, T.: Empirical Design Bugs Prediction for Verification [p. 161]
Chen, X.: Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing [p. 455]; Evaluating the Potential of Graphics Processors for High Performance Embedded Computing [p. 709]; Virtual Manycore Platforms: Moving Towards 100+ Processor Cores [p. 715]
Chen, Y.: Empirical Design Bugs Prediction for Verification [p. 161]; 3D-ICML: A 3D Bipolar ReRAM Design with Interleaved Complementary Memory Layers [p. 583]; Integrated Circuit White Space Redistribution for Temperature Optimization [p. 613]
Chen, Y.-C.: 3D-ICML: A 3D Bipolar ReRAM Design with Interleaved Complementary Memory Layers [p. 583]
Chen, Z.: Data-Oriented Performance Analysis of SHA-3 Candidates on FPGA Accelerated Computers [p. 1650]
Chen, Z.-W.: Obstacle-Aware Multiple-Source Rectilinear Steiner Tree with Electromigration and IR-Drop Avoidance [p. 449]; Timing-Constrained I/O Buffer Placement for Flip-Chip Designs [p. 619]
Cheng, B.: Statistical Aspects of NBTI/PBTI and Impact on SRAM Yield [p. 1480]
Cheng, C.-K.: A Block-Diagonal Structured Model Reduction Scheme for Power Grid Networks [p. 44]
Cheng, K.-T.: An All-Digital Built-In Self-Test Technique for Transfer Function Characterization of RF PLLs [p. 359]
Chevobbe, S.: Error Prediction Based on Concurrent Self-Test and Reduced Slack Time [p. 1626]
Chiang, P.: An Energy-Efficient 64-QAM MIMO Detector for Emerging Wireless Standards [p. 246]
Childers, B.: Impact of Process Variation on Endurance Algorithms for Wear-Prone Memories [p. 962]
Childers, B.R.: Demand Code Paging for NAND Flash in MMU-less Embedded Systems [p. 527]
Chin, C.-Y.: On Routing Fixed Escaped Boundary Pins for High Speed Boards [p. 461]
Chinea, A.: A Parallel Hamiltonian Eigensolver for Passivity Characterization and Enforcement of Large Interconnect Macromodels [p. 26]
Chippa, V.K.: Design of Voltage-Scalable Meta Functions for Approximate Computing [p. 950]
Chiu, Y.-S.: Pipeline Schedule Synthesis for Real-Time Streaming Tasks with Inter/Intra-Instance Precedence Constraints [p. 1321]
Cho, D.: I²CRF: Incremental Interconnect Customization for Embedded Reconfigurable Fabrics [p. 1346]
Cho, J.: An Analytical Compact Model for Estimation of Stress in Multiple Through-Silicon Via Configurations [p. 505]
Choi, M.: An Analytical Compact Model for Estimation of Stress in Multiple Through-Silicon Via Configurations [p. 505]
Chou, C.-L.: FARM: Fault-Aware Resource Management in NoC-Based Multiprocessor Platforms [p. 673]
Chou, P.: Automated Construction of Fast and Accurate System-Level Models for Wireless Sensor Networks [p. 1083]
Chou, P.H.: Simplified Programming of Faulty Sensor Networks via Code Transformation and Run-Time Interval Computation [p. 88]
Choudhury, M.R.: Reliability-driven Don't Care Assignment for Logic Synthesis [p. 1560]
Chrysanthou, N.: Parallel Accelerators for GlimmerHMM Bioinformatics Algorithm [p. 94]
Chrysos, G.: Parallel Accelerators for GlimmerHMM Bioinformatics Algorithm [p. 94]
Chung, C.-N.: Formal Reset Recovery Slack Calculation at the Register Transfer Level [p. 571]
Chuo, Y.: 2D and 3D Integration with Organic and Silicon Electronics [p. 899]
Ciais, P.: An Antenna-Filter Co-Design for Cardiac Implants [p. 728]
Ciesielski, M.: A New Distributed Event-Driven Gate-Level HDL Simulation by Accurate Prediction [p. 547]; Temporal Parallel Simulation: A Fast Gate-Level HDL Simulation Using Higher Level Models [p. 1584]
Cilardo, A.: The Potential of Reconfigurable Hardware for HPC Cryptanalytic of SHA-1 [p. 998]
Clermidy, F.: A Low-Power VLIW Processor for 3GPP-LTE Complex Numbers Processing [p. 234]; A Low Complexity Stopping Criterion for Reducing Power Consumption in Turbo Decoders [p. 649]; 3D Embedded Multi-Core: Some Perspectives [p. 1327]; Sustainability through Massively Integrated Computing: Are We Ready to Break the Energy Efficiency Wall for Single-Chip Platforms? [p. 1656]
Constantinides, G.: Optimization of Mutually Exclusive Arithmetic Sum-of-Products [p. 1388]
Constantino, N.: Characterization of an Intelligent Power Switch for LED Driving with Control of Wiring Parasitics Effects [p. 1119]
Copty, S.: A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation [p. 1590]
Corporaal, H.: Parallelization of While Loops in Nested Loop Programs for Shared-Memory Multiprocessor Systems [p. 697]; A 0.964mW Digital Hearing Aid System [p. 883]; Resynchronization of Cyclo-Static Dataflow Graphs [p. 1315]
Crop, J.: An Energy-Efficient 64-QAM MIMO Detector for Emerging Wireless Standards [p. 246]

D'Abramo, P.: Characterization of an Intelligent Power Switch for LED Driving with Control of Wiring Parasitics Effects [p. 1119]
D'Orazio, L.: Sensor Networks on the Car: State of the Art and Future Challenges [p. 1030]
Damm, W.: Using Contract-Based Component Specifications for Virtual Integration Testing and Architecture Design [p. 1023]
Danger, J.-L.: Enhancement of Simple Electro-Magnetic Attacks by Pre-Characterization in Frequency Domain and Demodulation Techniques [p. 1004]
Danowitz, A.: Intermediate Representations for Controllers in Chip Generators [p. 1394]
Dantara, D.: SHARC: A Streaming Model for FPGA Accelerators and its Application to Saliency [p. 1237]
Darin, M.: Sensor Networks on the Car: State of the Art and Future Challenges [p. 1030]
Darringer, J.A.: Early Chip Planning Cockpit [p. 863]
Darve, F.: 3D Embedded Multi-Core: Some Perspectives [p. 1327]
Dash, R.K.: Circuit and DFT Techniques for Robust and Low Cost Qualification of a Mixed-Signal SoC with Integrated Power Management System [p. 551]
David, J.-B.: An Antenna-Filter Co-Design for Cardiac Implants [p. 728]
Davis, W.R.: An Energy-Efficient 64-QAM MIMO Detector for Emerging Wireless Standards [p. 246]
Davoodi, A.: Power-Driven Global Routing for Multi-Supply Voltage Domains [p. 443]
de Foucauld, E.: An Antenna-Filter Co-Design for Cardiac Implants [p. 728]
de Lamotte, F.: Dynamic Applications on Reconfigurable Systems: From UML Model Design to FPGAs Implementation [p. 1208]
de Medeiros, J.E.G.: System-Level Modeling of a Mixed-Signal System on Chip for Wireless Sensor Networks [p. 1501]
De Meyer, K.: An Analytical Compact Model for Estimation of Stress in Multiple Through-Silicon Via Configurations [p. 505]
De Micheli, G.: Logic synthesis and Physical Design: Quo Vadis [p. 51]; Analytical Heat Transfer Model for Thermal Through-Silicon Vias [p. 395]; An Integrated Platform for Advanced Diagnostics [p. 1454]
De Wit, P.: Analog Circuit Reliability in Sub-32 Nanometer CMOS: Analysis and Mitigation [p. 1474]
Dehollain, C.: A Circuit Technology Platform for Medical Data Acquisition and Communication [p. 1472]
Del Barrio, A.A.: Power Optimization in Heterogenous Datapaths [p. 1400]
Delaveaud, C.: An Antenna-Filter Co-Design for Cardiac Implants [p. 728]
Demir, A.: SAMURAI: An Accurate Method for Modeling and Simulating Non-Stationary Random Telegraph Noise in SRAMs [p. 1113]
Deng, Q.: Energy-Efficient Scheduling of Real-Time Tasks on Cluster-Based Multicores [p. 1135]
Deng, Y.: Evaluating the Potential of Graphics Processors for High Performance Embedded Computing [p. 709]
Deng, Y.S.: Scalable Packet Classification via GPU Metaprogramming [p. 871]
Desoli, G.: An Efficient On-Line Task Allocation Algorithm for QoS and Energy Efficiency in Multicore Multimedia Platforms [p. 100]
Dey, S.: VESPA: Variability Emulation for System-on-Chip Performance Analysis [p. 2]
Dick, R.P.: Simplified Programming of Faulty Sensor Networks via Code Transformation and Run-Time Interval Computation [p. 88]; Integrated Circuit White Space Redistribution for Temperature Optimization [p. 613]; Automated Construction of Fast and Accurate System-Level Models for Wireless Sensor Networks [p. 1083]
Diguet, J.-P.: Dynamic Applications on Reconfigurable Systems: From UML Model Design to FPGAs Implementation [p. 1208]
Dinda, P.A.: Simplified Programming of Faulty Sensor Networks via Code Transformation and Run-Time Interval Computation [p. 88]; Automated Construction of Fast and Accurate System-Level Models for Wireless Sensor Networks [p. 1083]
Doboli, A.: A Symbolic Technique for Automated Characterization of the Uniqueness and Similarity of Analog Circuit Design Features [p. 1212]
Dobrovolný, P.: Variability Aware Modeling for Yield Enhancement of SRAM and Logic [p. 1153]
Dohmen, J.: Test Time Reduction in Analogue/Mixed-Signal Devices by Defect Oriented Testing: An Industrial Example [p. 371]
Dong, X.: An Energy-Efficient 3D CMP Design with Fine-Grained Voltage Scaling [p. 539]; Design Implications of Memristor-Based RRAM Cross-Point Structures [p. 734]
dos Santos, O.M.: Fast and Accurate Transaction-Level Model of a Wormhole Network-on-Chip with Priority Preemptive Virtual Channel Arbitration [p. 1089]
Dragomir, O.S.: Loop Distribution for K-Loops on Reconfigurable Architectures [p. 1548]
Drane, T.: Optimization of Mutually Exclusive Arithmetic Sum-of-Products [p. 1388]
Drechsler, R.: Verifying Dynamic Aspects of UML Models [p. 1077]; Determining the Minimal Number of Lines for Large Reversible Circuits [p. 1204]; As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects Using Pseudo-Boolean Optimization [p. 1291]
Dreslinski, R.G.: Low Power Interconnects for SIMD Computers [p. 600]
Dressler, D.: Challenges in Designing High Speed Memory Subsystem for Mobile Applications [p. 509]
Dreyer, A.: STABLE: A New QF-BV SMT Solver for Hard Verification Problems combining Boolean Reasoning with Computer Algebra [p. 155]
Drmanac, D.: Multidimensional Parametric Test Set Optimization of Wafer Probe Data for Predicting in Field Failures and Setting Tighter Test Limits [p. 794]
Dumas, N.: An Electrical Test Method for MEMS Convective Accelerometers: Development and Evaluation [p. 806]
Dupret, A.: Smart Imagers of the Future [p. 437]
Dutoit, D.: 3D Embedded Multi-Core: Some Perspectives [p. 1327]
Dutt, N.: Slack-Aware Scheduling on Coarse Grained Reconfigurable Arrays [p. 1513]
Dutt, N.D.: E-RoC: Embedded Raids-on-Chip for Low Power Distributed Dynamically Managed Reliable Memories [p. 1141]

Eberle, W.: Systematic Design of a Programmable Low-Noise CMOS Neural Interface for Cell Activity Recording [p. 818]
Ebrahimi, M.: ScTMR: A Scan Chain-Based Error Recovery Technique for TMR Systems in Safety-Critical Applications [p. 289]
Eeckhout, L.: Virtual Manycore Platforms: Moving Towards 100+ Processor Cores [p. 715]
Eggersglüβ, S.: As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects Using Pseudo-Boolean Optimization [p. 1291]
El-Kharashi, M.W.: A Reconfigurable, Pipelined, Conflict Directed Jumping Search SAT Solver [p. 1243]
Eneman, G.: An Analytical Compact Model for Estimation of Stress in Multiple Through-Silicon Via Configurations [p. 505]
Enz, C.: Energy Parsimonious Circuit Design through Probabilistic Pruning [p. 764]; A Circuit Technology Platform for Medical Data Acquisition and Communication [p. 1472]
Erb, S.: A Method for Fast Jitter Tolerance Analysis of High-Speed PLLs [p. 1107]
Escudero Martinez, M.: An FPGA Bridge Preserving Traffic Quality of Service for On-Chip Network-Based Systems [p. 425]
Evain, S.: Error Prediction Based on Concurrent Self-Test and Reduced Slack Time [p. 1626]

Fakhar, F.: A New Reconfigurable Clock-Gating Technique for Low Power SRAM-Based FPGAs [p. 752]
Falk, J.: A Rule-Based Static Dataflow Clustering Algorithm for Efficient Embedded Software Synthesis [p. 521]
Fallica, P.G.: Solid State Photodetectors for Nuclear Medical Imaging Applications [p. 511]
Fan, J.: Low-cost Fault Detection Method for ECC Using Montgomery Powering Ladder [p. 1016]
Fang, S.-C.: Black-Box Leakage Power Modeling for Cell Library and SRAM Compiler [p. 637]
Fanucci, L.: A Sensor Fusion Algorithm for an Integrated Angular Position Estimation with Inertial Measurement Units [p. 273]; Characterization of an Intelligent Power Switch for LED Driving with Control of Wiring Parasitics Effects [p. 1119]
Favalli, M.: Exploiting Network-on-Chip Structural Redundancy for a Cooperative and Scalable Built-In Self-Test Architecture [p. 661]
Fazeli, M.: Soft Error Rate Estimation of Digital Circuits in the Presence of Multiple Event Transients (METs) [p. 70]
Ferent, C.: A Symbolic Technique for Automated Characterization of the Uniqueness and Similarity of Analog Circuit Design Features [p. 1212]
Fernández Villena, J.: Fast Statistical Analysis of RC Nets Subject to Manufacturing Variabilities [p. 32]
Ferrari, F.: X-SENSE: Sensing in Extreme Environments [p. 1460]
Ferreira, A.P.: Impact of Process Variation on Endurance Algorithms for Wear-Prone Memories [p. 962]
Fettweis, G.: Entering the Path towards Terabit/s Wireless Links [p. 431]
Fettweis, G.P.: Guaranteed Service Virtual Channel Allocation in NoCs for Run-Time Task Scheduling [p. 419]
Ficarra, E.: Solid State Photodetectors for Nuclear Medical Imaging Applications [p. 511]
Figueras, J.: Robustness Analysis of 6T SRAMs in Memory Retention Mode under PVT Variations [p. 980]
Flament, F.: Enhancement of Simple Electro-Magnetic Attacks by Pre-Characterization in Frequency Domain and Demodulation Techniques [p. 1004]
Flynn, D.: Sub-Clock Power-Gating Technique for Minimising Leakage Power During Active Mode [p. 106]; Correlating Models and Silicon for Improved Parametric Yield [p. 1159]
Fonseca da Mota, P.: A True Power Detector for RF PA Built-In Calibration and Testing [p. 365]
Fourmigue, A.: Multi-Granularity Thermal Evaluation of 3D MPSoC Architectures [p. 575]
Fournel, N.: Speeding-up SIMD Instructions Dynamic Binary Translation in Embedded Processor Simulation [p. 277]
Franke, H.: Optimization of Stateful Hardware Acceleration in Hybrid Architectures [p. 567]
Fu, C.-Y.: A Shared-Variable-Based Synchronization Approach to Efficient Cache Coherence Simulation for Multi-Core Systems [p. 347]
Fukui, M.: An Algorithm to Improve Accuracy of Criticality in Statistical Static Timing Analysis [p. 1529]
Funchal, G.: jTLM: An Experimentation Framework for the Simulation of Transaction-Level Models of Systems-on-Chip [p. 1184]
Furber, S.: Biologically-Inspired Massively-Parallel Architectures - Computing Beyond A Million Processors [p. 1]; Modeling Circuit Performance Variations Due to Statistical Variability: Monte Carlo Static Timing Analysis [p. 1537]
Furukawa, H.: Transition-Time-Relation Based Capture-Safety Checking for At-Speed Scan Test Generation [p. 895]

Gangemi, G.: Moving to Green ICT: From Stand-Alone Power-Aware IC Design to an Integrated Approach to Energy Efficient Design of Heterogeneous Electronic Systems [p. 1127]
Ganguly, A.: Sustainability through Massively Integrated Computing: Are We Ready to Break the Energy Efficiency Wall for Single-Chip Platforms? [p. 1656]
Gao, J.: Eliminating Data Invalidation in Debugging Multiple-Clock Chips [p. 691]
Garg, S.: Statistical Thermal Evaluation and Mitigation Techniques for 3D Chip-Multiprocessors in the Presence of Process Variations [p. 383]
George, N.: Reducing the Cost of Redundant Execution in Safety-Critical Systems Using Relaxed Dedication [p. 1249]
Gerding, M.: Low Power Smart Industrial Control [p. 595]
German, R.: Formal Specification and Systematic Model-Driven Testing of Embedded Automotive Systems [p. 118]
Gerstlauer, A.: Host-Compiled Multicore RTOS Simulator for Embedded Real-Time Software Development [p. 222]; Controlled Timing-Error Acceptance for Low Energy IDCT Design [p. 758]
Geuns, S.J.: Parallelization of While Loops in Nested Loop Programs for Shared-Memory Multiprocessor Systems [p. 697]
Geuzebroek, J.: SoC Infrastructures for Predictable System Integration [p. 857]
Ghasemazar, M.: Variation Aware Dynamic Power Management for Chip Multiprocessor Architectures [p. 473]
Gherman, V.: Error Prediction Based on Concurrent Self-Test and Reduced Slack Time [p. 1626]
Ghoreishizadeh, S.S.: An Integrated Platform for Advanced Diagnostics [p. 1454]
Gielen, G.: Systematic Design of a Programmable Low-Noise CMOS Neural Interface for Cell Activity Recording [p. 818]; Global Optimization of Integrated Transformers for High Frequency Microwave Circuits Using a Gaussian Process Based Surrogate Model [p. 1101]; Stochastic Circuit Reliability Analysis [p. 1285]; Analog Circuit Reliability in Sub-32 Nanometer CMOS: Analysis and Mitigation [p. 1474]
Gil, R.M.: Fast Startup for Spartan-6 FPGAs Using Dynamic Partial Reconfiguration [p. 1542]
Gilani, S.Z.: Scratchpad Memory Optimizations for Digital Signal Processing Applications [p. 974]
Gili, X.: An Efficient and Scalable STA Tool with Direct Path Estimation and Exhaustive Sensitization Vector Exploration for Optimal Delay Computation [p. 1602]
Girão, G.: Improving the Efficiency of a Hardware Transactional Memory on an NoC-based MPSoC [p. 1168]
Girault, A.: Pruning Infeasible Paths for Tight WCRT Analysis of Synchronous Programs [p. 204]
Gizopoulos, D.: Architectures for Online Error Detection and Recovery in Multicore Processors [p. 533]
Gobbato, L.: A Parallel Hamiltonian Eigensolver for Passivity Characterization and Enforcement of Large Interconnect Macromodels [p. 26]
Gogniat, G.: Dynamic Applications on Reconfigurable Systems: From UML Model Design to FPGAs Implementation [p. 1208]
Golani, P.: An Area-Efficient Multi-Level Single-Track Pipeline Template [p. 1509]
Gomez, C.: Exploiting Network-on-Chip Structural Redundancy for a Cooperative and Scalable Built-In Self-Test Architecture [p. 661]
Gomez, M.E.: Exploiting Network-on-Chip Structural Redundancy for a Cooperative and Scalable Built-In Self-Test Architecture [p. 661]
Goossens, K.: An FPGA Bridge Preserving Traffic Quality of Service for On-Chip Network-Based Systems [p. 425]; Architectures and Modeling of Predictable Memory Controllers for Improved System Integration [p. 851]; Optimal Scheduling of Switched FlexRay Networks [p. 926]
Goswami, D.: Re-Engineering Cyber-Physical Control Applications for Hybrid Communication Protocols [p. 914]
Gowda, S.: Powering and Communicating with mm-size Implants [p. 722]
Goyal, A.: Efficient RC Power Grid Verification Using Node Elimination [p. 257]
Grammatikakis, M.D.: System-Level Power Estimation Methodology Using Cycle- and Bit-Accurate TLM [p. 1125]
Graupner, A.: Generator Based Approach for Analog Circuit and Layout Design and Optimization [p. 1675]
Gray, C.E.: Two Methods for 24 Gbps Test Signal Synthesis [p. 579]
Grenier, A.: NoC-MPU: A Secure Architecture for Flexible Co-Hosting on Shared Memory MPSoCs [p. 591]
Greuel, G.-M.: STABLE: A New QF-BV SMT Solver for Hard Verification Problems combining Boolean Reasoning with Computer Algebra [p. 155]
Grimm, C.: Real-Time Wireless Communication in Automotive Applications [p. 1036]; Wireless Communication and Energy Harvesting in Automobiles [p. 1042]; Simulation Based Tuning of System Specification [p. 1273]
Grimm, H.: Strategies for Initial Sizing and Operating Point Analysis of Analog Circuits [p. 1672]
Grivet-Talocia, S.: A Parallel Hamiltonian Eigensolver for Passivity Characterization and Enforcement of Large Interconnect Macromodels [p. 26]
Grosso, M.: Fault Grading of Software-Based Self-Test Procedures for Dependable Automotive Applications [p. 513]
Guderian, F.: Entering the Path towards Terabit/s Wireless Links [p. 431]
Guillet, S.: Dynamic Applications on Reconfigurable Systems: From UML Model Design to FPGAs Implementation [p. 1208]
Guilley, S.: Enhancement of Simple Electro-Magnetic Attacks by Pre-Characterization in Frequency Domain and Demodulation Techniques [p. 1004]
Guo, Q.: Empirical Design Bugs Prediction for Verification [p. 161]
Guo, X.: Data-Oriented Performance Analysis of SHA-3 Candidates on FPGA Accelerated Computers [p. 1650]
Gupta, P.: Variability-Aware Duty Cycle Scheduling in Long Running Embedded Sensing Systems [p. 131]; On the Efficacy of NBTI Mitigation Techniques [p. 932]; Case Study: Alleviating Hotspots and Improving Chip Reliability via Carbon Nanotube Thermal Interface [p. 1071]
Gupta, R.K.: Understanding the Role of Buildings in a Smart Microgrid [p. 1224]
Gupta, S.: Testing of High-Speed DACs Using PRBS Generation with "Alternate-Bit-Tapping" [p. 377]
Gupta, S.K.: A New Circuit Simplification Method for Error Tolerant Applications [p. 1566]

Haase, J.: Real-Time Wireless Communication in Automotive Applications [p. 1036]; Simulation Based Tuning of System Specification [p. 1273]
Hamdioui, S.: Cost-Efficient Fault-Tolerant Decoder for Hybrid Nanoelectronic Memories [p. 265]
Hameed, F.: Dynamic Thermal Management in 3D Multi-Core Architecture through Run-Time Adaptation [p. 299]
Han, H.: Clause Simplification through Dominator Analysis [p. 143]
Han, Y.: Eliminating Data Invalidation in Debugging Multiple-Clock Chips [p. 691]; FlexMemory: Exploiting and Managing Abundant Off-Chip Optical Bandwidth [p. 968]
Hanumaiah, V.: Reliability-aware Thermal Management for Hard Real-time Applications on Multi-core Processors [p. 137]
Hanyu, T.: Interconnect-Fault-Resilient Delay-Insensitive Asynchronous Communication Link Based on Current-Flow Monitoring [p. 776]
Hari, S.K.S.: Architectures for Online Error Detection and Recovery in Multicore Processors [p. 533]
Haron, N.Z.: Cost-Efficient Fault-Tolerant Decoder for Hybrid Nanoelectronic Memories [p. 265]
Hashempour, H.: Test Time Reduction in Analogue/Mixed-Signal Devices by Defect Oriented Testing: An Industrial Example [p. 371]
Haubelt, C.: A Rule-Based Static Dataflow Clustering Algorithm for Efficient Embedded Software Synthesis [p. 521]
Hausmans, J.P.H.M.: Resynchronization of Cyclo-Static Dataflow Graphs [p. 1315]
Hayes, J.P.: Trigonometric Method to Handle Realistic Error Probabilities in Logic Circuits [p. 64]
He, K.: Controlled Timing-Error Acceptance for Low Energy IDCT Design [p. 758]
He, Y.: Global Optimization of Integrated Transformers for High Frequency Microwave Circuits Using a Gaussian Process Based Surrogate Model [p. 1101]
Healy, M.B.: A Novel TSV Topology for Many-Tier 3D Power-Delivery Networks [p. 261]
Heckeler, P.: Scalable Hybrid Verification for Embedded Software [p. 179]
Hedrich, L.: Automated Constraint-Driven Topology Synthesis for Analog Circuits [p. 1662]
Heidmann, N.: Architecture and FPGA-Implementation of a High Throughput K⁺-Best Detector [p. 240]
Hemani, A.: Predicting Bus Contention Effects on Energy and Performance in Multi-Processor SoCs [p. 1196]
Hendry, G.: VANDAL: A Tool for the Design Specification of Nanophotonic Networks [p. 782]
Henkel, J.: Dynamic Thermal Management in 3D Multi-Core Architecture through Run-Time Adaptation [p. 299]; CARAT: Context-Aware Runtime Adaptive Task Migration for Multi Core Architectures [p. 515]; Minority-Game-Based Resource Allocation for Run-Time Reconfigurable Multi-Core Processors [p. 1261]; Multi-Level Pipelined Parallel Hardware Architecture for High Throughput Motion and Disparity Estimation in Multiview Video Coding [p. 1448]; mRTS: Run-Time System for Reconfigurable Processors with Multi-Grained Instruction-Set Extensions [p. 1554]
Henker, S.: Strategies for Initial Sizing and Operating Point Analysis of Analog Circuits [p. 1672]
Hennig, E.: A New Method for Automated Generation of Compensation Networks - The EDA Designer Finger [p. 1666]
Herkersdorf, A.: An Approach to Improve Accuracy of Source-Level TLMs of Embedded Software [p. 216]
Hermida, R.: Power Optimization in Heterogenous Datapaths [p. 1400]
Herndl, T.: Real-Time Wireless Communication in Automotive Applications [p. 1036]
Hielscher, K.-S.: Formal Specification and Systematic Model-Driven Testing of Embedded Automotive Systems [p. 118]
Hill, S.: Sub-Clock Power-Gating Technique for Minimising Leakage Power During Active Mode [p. 106]
Ho, Y.-L.: Thermal-Aware On-Line Task Allocation for 3D Multi-Core Processor Throughput Optimization [p. 8]
Hoffmann, T.: An Analytical Compact Model for Estimation of Stress in Multiple Through-Silicon Via Configurations [p. 505]
Holcomb, D.: Counterexample-Guided SMT-Driven Optimal Buffer Sizing [p. 329]
Homma, N.: Enhancement of Simple Electro-Magnetic Attacks by Pre-Characterization in Frequency Domain and Demodulation Techniques [p. 1004]
Honkote, V.: Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing [p. 455]
Höppner, S.: Strategies for Initial Sizing and Operating Point Analysis of Analog Circuits [p. 1672]
Hora, C.: Test Time Reduction in Analogue/Mixed-Signal Devices by Defect Oriented Testing: An Industrial Example [p. 371]
Horiuchi, K.: An LOCV-Based Static Timing Analysis Considering Spatial Correlations of Power Supply Variations [p. 559]
Horowitz, M.: Intermediate Representations for Controllers in Chip Generators [p. 1394]
Hou, R.: Optimization of Stateful Hardware Acceleration in Hybrid Architectures [p. 567]
Hsiao, M.S.: Design-for-Test Methodology for Non-Scan At-Speed Testing [p. 191]
Hsu, S.-J.: Clock Gating Optimization with Delay-Matching [p. 643]
Hu, J.: Towards Energy Efficient Hybrid On-Chip Scratch Pad Memory with Non-Volatile Memory [p. 746]
Hu, W.: Empirical Design Bugs Prediction for Verification [p. 161]
Hu, X.: A Block-Diagonal Structured Model Reduction Scheme for Power Grid Networks [p. 44]; A Cost-Effective Substantial-Impact-Filter Based Method to Tolerate Voltage Emergencies [p. 311]
Hu, Y.: Cross-Layer Optimized Placement and Routing for FPGA Soft Error Mitigation [p. 58]; A Cost-Effective Substantial-Impact-Filter Based Method to Tolerate Voltage Emergencies [p. 311]; On Diagnosis of Multiple Faults Using Compressed Responses [p. 679]
Huang, C.-Y.: Speeding up MPSoC Virtual Platform Simulation by Ultra Synchronization Checking Method [p. 353]
Huang, H.: Leakage Aware Energy Minimization for Real-Time Systems under the Maximum Temperature Constraint [p. 479]
Huang, J.: Case Study: Alleviating Hotspots and Improving Chip Reliability via Carbon Nanotube Thermal Interface [p. 1071]; A Workflow for Runtime Adaptive Task Allocation on Heterogeneous MPSoCs [p. 1129]
Huang, J.-D.: Architectural Exploration of 3D FPGAs towards a Better Balance between Area and Delay [p. 587]
Huang, K.: Cross-Layer Optimized Placement and Routing for FPGA Soft Error Mitigation [p. 58]
Huang, L.: A Specialized Low-Cost Vectorized Loop Buffer for Embedded Processors [p. 1200]
Huang, Q.: A Circuit Technology Platform for Medical Data Acquisition and Communication [p. 1472]
Huang, S.-Y.: Black-Box Leakage Power Modeling for Cell Library and SRAM Compiler [p. 637]
Hübner, M.: Fast Startup for Spartan-6 FPGAs Using Dynamic Partial Reconfiguration [p. 1542]
Hung, S.-H.: Pipeline Schedule Synthesis for Real-Time Streaming Tasks with Inter/Intra-Instance Precedence Constraints [p. 1321]
Hungar, H.: Using Contract-Based Component Specifications for Virtual Integration Testing and Architecture Design [p. 1023]
Hunter, A.: Power Management Verification Experiences in Wireless SoCs [p. 507]
Hwang, T.T.: A New Architecture for Power Network in 3D IC [p. 401]

Indrusiak, L.S.: Fast and Accurate Transaction-Level Model of a Wormhole Network-on-Chip with Priority Preemptive Virtual Channel Arbitration [p. 1089]
Ingelsson, U.: Design Automation for IEEE P1687 [p. 1412]
Ishihara, T.: Developing an Integrated Verification and Debug Methodology [p. 503]

Jahn, J.: CARAT: Context-Aware Runtime Adaptive Task Migration for Multi Core Architectures [p. 515]
Jancke, R.: Generator Based Approach for Analog Circuit and Layout Design and Optimization [p. 1675]
Jerraya, A.: A 3D Reconfigurable Platform for 4G Telecom Applications [p. 555]
Jezequel, M.: A Flexible High Throughput Multi-ASIP Architecture for LDPC and Turbo Decoding [p. 228]; A Low Complexity Stopping Criterion for Reducing Power Consumption in Turbo Decoders [p. 649]
Jha, S.K.: When to Stop Verification? Statistical Trade-Off between Expected Loss and Simulation Cost [p. 1309]
Ji, W.: Floorplanning Exploration and Performance Evaluation of a New Network-on-Chip [p. 625]
Jin, H.: Clause Simplification through Dominator Analysis [p. 143]
Johnson, C.L.: Early Chip Planning Cockpit [p. 863]
Jores, P.: Automated Constraint-Driven Topology Synthesis for Analog Circuits [p. 1662]
Joseph, R.: Efficient Parameter Variation Sampling for Architecture Simulations [p. 1578]
Josko, B.: Using Contract-Based Component Specifications for Virtual Integration Testing and Architecture Design [p. 1023]
Jouppi, N.P.: Design Implications of Memristor-Based RRAM Cross-Point Structures [p. 734]
Juan, D.-C.: Statistical Thermal Evaluation and Mitigation Techniques for 3D Chip-Multiprocessors in the Presence of Process Variations [p. 383]
Jung, H.: A Quantitative Analysis of Performance Benefits of 3D Die Stacking on Mobile and Embedded SoC [p. 1333]
Jung, J.: I²CRF: Incremental Interconnect Customization for Embedded Reconfigurable Fabrics [p. 1346]

Kajihara, S.: Transition-Time-Relation Based Capture-Safety Checking for At-Speed Scan Test Generation [p. 895]
Kajitani, Y.: On Routing Fixed Escaped Boundary Pins for High Speed Boards [p. 461]
Kakoee, M.R.: A Fully-Synthesizable Single-Cycle Interconnection Network for Shared-L1 Processor Clusters [p. 491]; ReliNoC: A Reliable Network for Priority-Based On-Chip Communication [p. 667]
Kamal, M.: Timing Variation-Aware Custom Instruction Extension Technique [p. 1517]
Kaminska, B.: 2D and 3D Integration with Organic and Silicon Electronics [p. 899]
Kang, K.: Scalable Packet Classification via GPU Metaprogramming [p. 871]
Kanoun, K.: A Real-Time Compressed Sensing-Based Personal Electrocardiogram Monitoring System [p. 824]
Kapoor, B.: Power Management Verification Experiences in Wireless SoCs [p. 507]
Karaklajic, D.: Low-cost Fault Detection Method for ECC Using Montgomery Powering Ladder [p. 1016]
Katevenis, M.: Fine-Grain OpenMP Runtime Support with Explicit Communication Hardware Primitives [p. 891]
Kauppinen, H.: Wireless Innovations for Smartphones [p. 606]
Kavadias, S.: Fine-Grain OpenMP Runtime Support with Explicit Communication Hardware Primitives [p. 891]
Kazmierski, T.: Wireless Communication and Energy Harvesting in Automobiles [p. 1042]
Kazmierski, T.J.: Accelerated Simulation of Tunable Vibration Energy Harvesting Systems Using a Linearised State-Space Technique [p. 1267]; An Extension to SystemC-A to Support Mixed-Technology Systems with Distributed Components [p. 1279]
Keezer, D.C.: Two Methods for 24 Gbps Test Signal Synthesis [p. 579]
Keller, M.: X-SENSE: Sensing in Extreme Environments [p. 1460]
Kelley, K.: Intermediate Representations for Controllers in Chip Generators [p. 1394]
Keng, B.: Automated Debugging of SystemVerilog Assertions [p. 323]
Kern, A.: An Automated Data Structure Migration Concept - From CAN to Ethernet/IP in Automotive Embedded Systems (CANoverIP) [p. 112]
Kershaw, D.: Low Power Interconnects for SIMD Computers [p. 600]
Kestur, S.: SHARC: A Streaming Model for FPGA Accelerators and its Application to Saliency [p. 1237]
Keszöcze, O.: Determining the Minimal Number of Lines for Large Reversible Circuits [p. 1204]
Khaled, N.: A Real-Time Compressed Sensing-Based Personal Electrocardiogram Monitoring System [p. 824]
Khan, G.N.: Multi-Objective Tabu Search Based Topology Generation Technique for Application-Specific Network-on-Chip Architectures [p. 485]
Khatib, M.G.: Buffering Implications for the Design Space of Streaming MEMS Storage [p. 253]
Kim, D.: A New Distributed Event-Driven Gate-Level HDL Simulation by Accurate Prediction [p. 547]; A Quantitative Analysis of Performance Benefits of 3D Die Stacking on Mobile and Embedded SoC [p. 1333]; Temporal Parallel Simulation: A Fast Gate-Level HDL Simulation Using Higher Level Models [p. 1584]
Kim, N.S.: Time Redundant Parity for Low-Cost Transient Error Detection [p. 52]; Scratchpad Memory Optimizations for Digital Signal Processing Applications [p. 974]
Kim, Y.: Battery-Supercapacitor Hybrid System for High-Rate Pulsed Load Applications [p. 875]; I²CRF: Incremental Interconnect Customization for Embedded Reconfigurable Fabrics [p. 1346]; A Confidence-Driven Model for Error-Resilient Computing [p. 1608]
Klobedanz, K.: A Reconfiguration Approach for Fault-Tolerant FlexRay Networks [p. 82]
Knoll, A.: A Workflow for Runtime Adaptive Task Allocation on Heterogeneous MPSoCs [p. 1129]; Priority Division: A High-Speed Shared-Memory Bus Arbitration with Bounded Latency [p. 1497]
Kobayashi, S.: An LOCV-Based Static Timing Analysis Considering Spatial Correlations of Power Supply Variations [p. 559]
Koch, A.: MARC II: A Parametrized Speculative Multi-Ported Memory Subsystem for Reconfigurable Computers [p. 1352]
Kochte, M.A.: SAT-Based Fault Coverage Evaluation in the Presence of Unknown Values [p. 1303]
Koenig, A.: A Reconfiguration Approach for Fault-Tolerant FlexRay Networks [p. 82]
Kolpe, T.: Enabling Improved Power Management in Multicore Processors through Clustered DVFS [p. 293]
Kondratyev, A.: Realistic Performance-Constrained Pipelining in High-Level Synthesis [p. 1382]
Kong, F.: Energy-Efficient Scheduling of Real-Time Tasks on Cluster-Based Multicores [p. 1135]
Koushanfar, F.: HypoEnergy: Hybrid Supercapacitor-Battery Power-Supply Optimization for Energy Efficiency [p. 887]
Kozhikkottu, V.: VESPA: Variability Emulation for System-on-Chip Performance Analysis [p. 2]
Krause, P.K.: Adaptive Voltage Over-Scaling for Resilient Applications [p. 944]
Krausse, D.: A New Method for Automated Generation of Compensation Networks - The EDA Designer Finger [p. 1666]; Strategies for Initial Sizing and Operating Point Analysis of Analog Circuits [p. 1672]
Krishna, A.: High-Temperature (>500°C) Reconfigurable Computing Using Silicon Carbide NEMS Switches [p. 1065]
Krone, S.: Entering the Path towards Terabit/s Wireless Links [p. 431]
Kropf, T.: Scalable Hybrid Verification for Embedded Software [p. 179]
Kruseman, B.: Test Time Reduction in Analogue/Mixed-Signal Devices by Defect Oriented Testing: An Industrial Example [p. 371]
Kuan, C.-Y.: On Routing Fixed Escaped Boundary Pins for High Speed Boards [p. 461]
Kudari, A.D.: Circuit and DFT Techniques for Robust and Low Cost Qualification of a Mixed-Signal SoC with Integrated Power Management System [p. 551]
Kuehlmann, A.: An Approach for Dynamic Selection of Synthesis Transformations Based on Markov Decision Processes [p. 1533]
Kumar, A.: Hyper-Graph Based Partitioning to Reduce DFT Cost for Pre-Bond 3D-IC Testing [p. 1424]
Kumar, R.: On the Efficacy of NBTI Mitigation Techniques [p. 932]
Kundu, S.: On Design of Test Structures for Lithographic Process Corner Identification [p. 800]; Modeling Manufacturing Process Variation for Design and Test [p. 1147]; On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs [p. 1418]; Physically Unclonable Functions for Embedded Security Based on Lithographic Variation [p. 1632]
Kunz, L.: Improving the Efficiency of a Hardware Transactional Memory on an NoC-based MPSoC [p. 1168]
Kunz, W.: STABLE: A New QF-BV SMT Solver for Hard Verification Problems combining Boolean Reasoning with Computer Algebra [p. 155]
Kuo, S.-Y.: Formal Reset Recovery Slack Calculation at the Register Transfer Level [p. 571]
Kupp, N.: Correlating Inline Data with Final Test Outcomes in Analog/RF Devices [p. 812]
Kwai, D.-M.: Thermal-Aware On-Line Task Allocation for 3D Multi-Core Processor Throughput Optimization [p. 8]
Kyrkou, C.: Depth-Directed Hardware Object Detection [p. 1442]

Lach, J.: Reducing the Cost of Redundant Execution in Safety-Critical Systems Using Relaxed Dedication [p. 1249]
Lafi, W.: A 3D Reconfigurable Platform for 4G Telecom Applications [p. 555]; 3D Embedded Multi-Core: Some Perspectives [p. 1327]
Lampka, K.: Composing Heterogeneous Components for System-Wide Performance Analysis [p. 842]
Landa, S.: A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation [p. 1590]
Landrock, C.K.: 2D and 3D Integration with Organic and Silicon Electronics [p. 899]
Lange, H.: MARC II: A Parametrized Speculative Multi-Ported Memory Subsystem for Reconfigurable Computers [p. 1352]
Langmead, C.J.: When to Stop Verification? Statistical Trade-Off between Expected Loss and Simulation Cost [p. 1309]
Larsson, E.: Design Automation for IEEE P1687 [p. 1412]
Lattard, D.: A 3D Reconfigurable Platform for 4G Telecom Applications [p. 555]
Lavagno, L.: Realistic Performance-Constrained Pipelining in High-Level Synthesis [p. 1382]
Le Beux, S.: Optical Ring Network-on-Chip (ORNoC): Architecture and Design Methodology [p. 788]
Leblebici, Y.: Towards Thermally-Aware Design of 3D MPSoCs with Inter-Tier Cooling [p. 1466]
Lee, B.-C.: Architectural Exploration of 3D FPGAs towards a Better Balance between Area and Delay [p. 587]
Lee, E.-A.: Component-Based Design for the Future [p. 1029]
Lee, J.: I²CRF: Incremental Interconnect Customization for Embedded Reconfigurable Fabrics [p. 1346]
Lee, R.-J.: On Routing Fixed Escaped Boundary Pins for High Speed Boards [p. 461]
Lee, S.: A Novel Tag Access Scheme for Low Power L2 Cache [p. 655]; A Quantitative Analysis of Performance Benefits of 3D Die Stacking on Mobile and Embedded SoC [p. 1333]
Lee, T.-H.: High-Temperature (>500°C) Reconfigurable Computing Using Silicon Carbide NEMS Switches [p. 1065]
Lee, Y.-H.: Timing Error Statistics for Energy-Efficient Robust DSP Systems [p. 285]
Lettnin, D.: Scalable Hybrid Verification for Embedded Software [p. 179]
Leupers, R.: Virtual Manycore Platforms: Moving Towards 100+ Processor Cores [p. 715]
Li, D.: Evaluating the Potential of Graphics Processors for High Performance Embedded Computing [p. 709]
Li, H.: 3D-ICML: A 3D Bipolar ReRAM Design with Interleaved Complementary Memory Layers [p. 583]; FlexMemory: Exploiting and Managing Abundant Off-Chip Optical Bandwidth [p. 968]
Li, L.: Proactive Recovery for BTI in High-K SRAM Cells [p. 992]
Li, M.: Register Allocation for Simultaneous Reduction of Energy and Peak Temperature on Registers [p. 20]; Challenges in Designing High Speed Memory Subsystem for Mobile Applications [p. 509]
Li, X.: Cross-Layer Optimized Placement and Routing for FPGA Soft Error Mitigation [p. 58]; A Cost-Effective Substantial-Impact-Filter Based Method to Tolerate Voltage Emergencies [p. 311]; On Diagnosis of Multiple Faults Using Compressed Responses [p. 679]; Eliminating Data Invalidation in Debugging Multiple-Clock Chips [p. 691]; FlexMemory: Exploiting and Managing Abundant Off-Chip Optical Bandwidth [p. 968]
Li, Y.: Redressing Timing Issues for Speed-Independent Circuits in Deep Submicron Age [p. 1376]
Lim, S.K.: A Novel TSV Topology for Many-Tier 3D Power-Delivery Networks [p. 261]
Lin, H.-C.: Speeding up MPSoC Virtual Platform Simulation by Ultra Synchronization Checking Method [p. 353]
Lin, H.-L.: A New Architecture for Power Network in 3D IC [p. 401]
Lin, R.-B.: Clock Gating Optimization with Delay-Matching [p. 643]
Linderoth, J.T.: Power-Driven Global Routing for Multi-Supply Voltage Domains [p. 443]
Lindwer, M.: A 0.964mW Digital Hearing Aid System [p. 883]
Lingamneni, A.: Energy Parsimonious Circuit Design through Probabilistic Pruning [p. 764]
Lipasti, M.H.: Time Redundant Parity for Low-Cost Transient Error Detection [p. 52]
Liu, B.: Global Optimization of Integrated Transformers for High Frequency Microwave Circuits Using a Gaussian Process Based Surrogate Model [p. 1101]
Liu, C.: A Clock-Gating Based Capture Power Droop Reduction Methodology for At-Speed Scan Testing [p. 197]; A Specialized Low-Cost Vectorized Loop Buffer for Embedded Processors [p. 1200]
Liu, D.: An Endurance-Enhanced Flash Translation Layer via Reuse for NAND Flash Memory Storage Systems [p. 14]
Liu, F.: An Efficient Mask Optimization Method Based on Homotopy Continuation Technique [p. 1053]
Liu, L.: Towards Coverage Closure: Using Goldmine Assertions for Generating Design Validation Stimulus [p. 173]; Efficient Validation Input Generation in RTL by Hybridized Source Code Analysis [p. 1596]
Liu, M.: Evaluating the Potential of Graphics Processors for High Performance Embedded Computing [p. 709]
Liu, S.: Efficient Parameter Variation Sampling for Architecture Simulations [p. 1578]
Liu, T.: Register Allocation for Simultaneous Reduction of Energy and Peak Temperature on Registers [p. 20]
Liu, X.: On Multiplexed Signal Tracing for Post-Silicon Debug [p. 685]
Liu, Z.: Modeling Circuit Performance Variations Due to Statistical Variability: Monte Carlo Static Timing Analysis [p. 1537]
Lo, C.-K.: Cycle-Count-Accurate Processor Modeling for Fast and Accurate System-Level Simulation [p. 341]
Loghi, M.: Partitioned Cache Architectures for Reduced NBTI-Induced Aging [p. 938]
Loi, I.: Design Space Exploration for 3D-Stacked DRAMs [p. 389]; A Fully-Synthesizable Single-Cycle Interconnection Network for Shared-L1 Processor Clusters [p. 491]
López, C.M.: Systematic Design of a Programmable Low-Noise CMOS Neural Interface for Cell Activity Recording [p. 818]
Lu, C.: Stage Number Optimization for Switched Capacitor Power Converters in Micro-Scale Energy Harvesting [p. 770]
Lu, F.: Efficient Parameter Variation Sampling for Architecture Simulations [p. 1578]
Lu, H.: A Specialized Low-Cost Vectorized Loop Buffer for Embedded Processors [p. 1200]
Lu, J.: Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing [p. 455]
Lu, K.: An Approach to Improve Accuracy of Source-Level TLMs of Embedded Software [p. 216]
Lu, S.-L.: Distributed Hardware Matcher Framework for SoC Survivability [p. 305]
Lubaszewski, M.S.: Evaluating Energy Consumption of Homogeneous MPSoCs Using Spare Tiles [p. 1164]
Ludovici, D.: Exploiting Network-on-Chip Structural Redundancy for a Cooperative and Scalable Built-In Self-Test Architecture [p. 661]
Luk, W.-S.: An Efficient Algorithm for Multi-Domain Clock Skew Scheduling [p. 1364]
Lukasiewycz, M.: FlexRay Switch Scheduling - A Networking Concept for Electric Vehicles [p. 76]
Lung, C.-L.: Thermal-Aware On-Line Task Allocation for 3D Multi-Core Processor Throughput Optimization [p. 8]
Luo, G.: Early Chip Planning Cockpit [p. 863]
Luo, H.: Gemma in April: A Matrix-Like Parallel Programming Architecture on OpenCL [p. 703]

Ma, K.: LOEDAR: A Low Cost Error Detection and Recovery Scheme for ECC [p. 1010]
Ma, Y.: Optimization of Stateful Hardware Acceleration in Hybrid Architectures [p. 567]
Machado da Silva, J.: A True Power Detector for RF PA Built-In Calibration and Testing [p. 365]
Macii, A.: Moving to Green ICT: From Stand-Alone Power-Aware IC Design to an Integrated Approach to Energy Efficient Design of Heterogeneous Electronic Systems [p. 1127]
Macii, E.: Partitioned Cache Architectures for Reduced NBTI-Induced Aging [p. 938]
Mahlknecht, S.: Wireless Communication and Energy Harvesting in Automobiles [p. 1042]
Mailly, F.: An Electrical Test Method for MEMS Convective Accelerometers: Development and Evaluation [p. 806]
Mak, T.: Run-Time Deadlock Detection in Networks-on-Chip Using Coupled Transitive Closure Networks [p. 497]; Redressing Timing Issues for Speed-Independent Circuits in Deep Submicron Age [p. 1376]
Makris, Y.: Correlating Inline Data with Final Test Outcomes in Analog/RF Devices [p. 812]
Mamaghanian, H.: A Real-Time Compressed Sensing-Based Personal Electrocardiogram Monitoring System [p. 824]
Mangard, S.: Arithmetic Logic Units with High Error Detection Rates to Counteract Fault Attacks [p. 1644]
Manian, S.: Circuit and DFT Techniques for Robust and Low Cost Qualification of a Mixed-Signal SoC with Integrated Power Management System [p. 551]
Mansouri, I.: Sustainability through Massively Integrated Computing: Are We Ready to Break the Energy Efficiency Wall for Single-Chip Platforms? [p. 1656]
Marcon, C.A.M.: Evaluating Energy Consumption of Homogeneous MPSoCs Using Spare Tiles [p. 1164]
Marculescu, D.: Statistical Thermal Evaluation and Mitigation Techniques for 3D Chip-Multiprocessors in the Presence of Process Variations [p. 383]; Aging-Aware Timing Analysis and Optimization Considering Path Sensitization [p. 1572]
Marculescu, R.: FARM: Fault-Aware Resource Management in NoC-Based Multiprocessor Platforms [p. 673]; Sustainability through Massively Integrated Computing: Are We Ready to Break the Energy Efficiency Wall for Single-Chip Platforms? [p. 1656]
Maricau, E.: Stochastic Circuit Reliability Analysis [p. 1285]; Analog Circuit Reliability in Sub-32 Nanometer CMOS: Analysis and Mitigation [p. 1474]
Mark, M.: Powering and Communicating with mm-size Implants [p. 722]
Martin, G.: Virtual Manycore Platforms: Moving Towards 100+ Processor Cores [p. 715]
Massas, J.: Error Prediction Based on Concurrent Self-Test and Reduced Slack Time [p. 1626]
Matischek, R.: Real-Time Wireless Communication in Automotive Applications [p. 1036]
Matos, D.: A New Reconfigurable Clock-Gating Technique for Low Power SRAM-Based FPGAs [p. 752]
Matsuda, A.: Developing an Integrated Verification and Debug Methodology [p. 503]
Matsumoto, A.: Interconnect-Fault-Resilient Delay-Insensitive Asynchronous Communication Link Based on Current-Flow Monitoring [p. 776]
Mazzillo, M.: Solid State Photodetectors for Nuclear Medical Imaging Applications [p. 511]
Medwed, M.: Arithmetic Logic Units with High Error Detection Rates to Counteract Fault Attacks [p. 1644]
Mehregany, M.: High-Temperature (>500°C) Reconfigurable Computing Using Silicon Carbide NEMS Switches [p. 1065]
Meissner, C.: A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation [p. 1590]
Meissner, M.: Automated Constraint-Driven Topology Synthesis for Analog Circuits [p. 1662]
Meixner, A.: Architectures for Online Error Detection and Recovery in Multicore Processors [p. 533]
Melhem, R.: Impact of Process Variation on Endurance Algorithms for Wear-Prone Memories [p. 962]
Memik, S.O.: Power Optimization in Heterogenous Datapaths [p. 1400]
Mendias, J.M.: Power Optimization in Heterogenous Datapaths [p. 1400]
Mercha, A.: An Analytical Compact Model for Estimation of Stress in Multiple Through-Silicon Via Configurations [p. 505]
Merrett, G.V.: Ultra Low-Power Photovoltaic MPPT Technique for Indoor and Outdoor Wireless Sensor Nodes [p. 905]; Accelerated Simulation of Tunable Vibration Energy Harvesting Systems Using a Linearised State-Space Technique [p. 1267]
Merrett, M.: Modeling Circuit Performance Variations Due to Statistical Variability: Monte Carlo Static Timing Analysis [p. 1537]
Messina, A.: Solid State Photodetectors for Nuclear Medical Imaging Applications [p. 511]
Metra, C.: Error Correcting Code Analysis for Cache Memory High Reliability and Performance [p. 1620]
Meyer, B.H.: Reducing the Cost of Redundant Execution in Safety-Critical Systems Using Relaxed Dedication [p. 1249]
Meyer, J.: Fast Startup for Spartan-6 FPGAs Using Dynamic Partial Reconfiguration [p. 1542]
Meyer, M.: Realistic Performance-Constrained Pipelining in High-Level Synthesis [p. 1382]
Meynard, O.: Enhancement of Simple Electro-Magnetic Attacks by Pre-Characterization in Frequency Domain and Demodulation Techniques [p. 1004]
Michel, B.: Towards Thermally-Aware Design of 3D MPSoCs with Inter-Tier Cooling [p. 1466]
Michel, L.: Speeding-up SIMD Instructions Dynamic Binary Translation in Embedded Processor Simulation [p. 277]
Milbredt, P.: FlexRay Switch Scheduling - A Networking Concept for Electric Vehicles [p. 76]
Millar, C.: Modeling Circuit Performance Variations Due to Statistical Variability: Monte Carlo Static Timing Analysis [p. 1537]
Milojevic, D.: An Analytical Compact Model for Estimation of Stress in Multiple Through-Silicon Via Configurations [p. 505]
Mina, R.: Mathematical Approach Based on a "Design of Experiment" to Simulate Process Variations [p. 1486]
Miranda, M.: Variability Aware Modeling for Yield Enhancement of SRAM and Logic [p. 1153]
Miremadi, S.G.: Soft Error Rate Estimation of Digital Circuits in the Presence of Multiple Event Transients (METs) [p. 70]; ScTMR: A Scan Chain-Based Error Recovery Technique for TMR Systems in Safety-Critical Applications [p. 289]
Mirhoseini, A.: HypoEnergy: Hybrid Supercapacitor-Battery Power-Supply Optimization for Energy Efficiency [p. 887]
Mishra, P.: Decision Ordering Based Property Decomposition for Functional Test Generation [p. 167]
Mistry, J.N.: Sub-Clock Power-Gating Technique for Minimising Leakage Power During Active Mode [p. 106]
Mitea, O.: Automated Constraint-Driven Topology Synthesis for Analog Circuits [p. 1662]
Mittal, R.K.: Circuit and DFT Techniques for Robust and Low Cost Qualification of a Mixed-Signal SoC with Integrated Power Management System [p. 551]
Miyase, K.: Transition-Time-Relation Based Capture-Safety Checking for At-Speed Scan Test Generation [p. 895]
Modarressi, M.: Supporting Non-Contiguous Processor Allocation in Mesh-Based CMPs Using Virtual Point-to-Point Links [p. 413]
Moezzi-Madani, N.: An Energy-Efficient 64-QAM MIMO Detector for Emerging Wireless Standards [p. 246]
Mohalik, S.: When to Stop Verification? Statistical Trade-Off between Expected Loss and Simulation Cost [p. 1309]
Mohanram, K.: Robust 6T Si Tunneling Transistor SRAM Design [p. 740]; Reliability-driven Don't Care Assignment for Logic Synthesis [p. 1560]
Mohapatra, D.: Design of Voltage-Scalable Meta Functions for Approximate Computing [p. 950]
Molina, M.C.: Power Optimization in Heterogenous Datapaths [p. 1400]
Montag, P.: Precise WCET Calculation in Highly Variant Real-Time Systems [p. 920]
Moraes, F.G.: Achieving Composability in NoC-Based MPSoCs Through QoS Management at Software Level [p. 407]; Evaluating Energy Consumption of Homogeneous MPSoCs Using Spare Tiles [p. 1164]
Moroz, V.: An Analytical Compact Model for Estimation of Stress in Multiple Through-Silicon Via Configurations [p. 505]
Mossé, D.: Impact of Process Variation on Endurance Algorithms for Wear-Prone Memories [p. 962]
Moy, M.: jTLM: An Experimentation Framework for the Simulation of Transaction-Level Models of Systems-on-Chip [p. 1184]
Mu, S.: Evaluating the Potential of Graphics Processors for High Performance Embedded Computing [p. 709]
Mudge, T.: Low Power Interconnects for SIMD Computers [p. 600]
Mueller, W.: A Reconfiguration Approach for Fault-Tolerant FlexRay Networks [p. 82]
Mukhopadhyay, D.: Multi-Level Attacks: An Emerging Security Concern for Cryptographic Hardware [p. 1176]; Theoretical Modeling of the Itoh-Tsujii Inversion Algorithm for Enhanced Performance on k-LUT Based FPGAs [p. 1231]
Murugappa, P.: A Flexible High Throughput Multi-ASIP Architecture for LDPC and Turbo Decoding [p. 228]
Musa, S.: Systematic Design of a Programmable Low-Noise CMOS Neural Interface for Cell Activity Recording [p. 818]

Nacci, A.A.: A High-Performance Parallel Implementation of the Chambolle Algorithm [p. 1436]
Nadeem, M.: Targeting Code Diversity with Run-Time Adjustable Issue-Slots in a Chip Multiprocessor [p. 1358]
Naeimi, H.: A Confidence-Driven Model for Error-Resilient Computing [p. 1608]
Nagel, J.-L.: Energy Parsimonious Circuit Design through Probabilistic Pruning [p. 764]
Nahir, A.: A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation [p. 1590]
Najm, F.N.: Efficient RC Power Grid Verification Using Node Elimination [p. 257]
Nalam, S.: Dynamic Write Limited Minimum Operating Voltage for Nanoscale SRAMs [p. 467]
Narasimhan, S.: High-Temperature (>500°C) Reconfigurable Computing Using Silicon Carbide NEMS Switches [p. 1065]
Narayanan, P.: Circuit and DFT Techniques for Robust and Low Cost Qualification of a Mixed-Signal SoC with Integrated Power Management System [p. 551]
Narayanan, R.: Ensuring Correctness of Analog Circuits in Presence of Noise and Process Variations Using Pattern Matching [p. 1188]
Narayanan, V.: SHARC: A Streaming Model for FPGA Accelerators and its Application to Saliency [p. 1237]
Narayanasamy, S.: MLP Aware Heterogeneous Memory System [p. 956]
Nelms, T.: Optimization of Stateful Hardware Acceleration in Hybrid Architectures [p. 567]
Nercessian, E.: Mathematical Approach Based on a "Design of Experiment" to Simulate Process Variations [p. 1486]
Neuendorffer, S.: Building Real-time HDTV Applications in FPGAs Using Processors, AXI Interfaces and High Level Synthesis Tools [p. 848]
Nicolaidis, M.: A fault-Tolerant Deadlock-Free Adaptive Routing for On Chip Interconnects [p. 909]; Eliminating Speed Penalty in ECC Protected Memories [p. 1614]
Nicolescu, G.: Multi-Granularity Thermal Evaluation of 3D MPSoC Architectures [p. 575]; Optical Ring Network-on-Chip (ORNoC): Architecture and Design Methodology [p. 788]; A Multi-Objective Decision-Theoretic Exploration Algorithm for Platform-based Design [p. 1192]
Nigam, A.: Pseudo Circuit Model for Representing Uncertainty in Waveforms [p. 1521]
Nikiforos, G.: Fine-Grain OpenMP Runtime Support with Explicit Communication Hardware Primitives [p. 891]
Nikolopoulos, D.S.: Fine-Grain OpenMP Runtime Support with Explicit Communication Hardware Primitives [p. 891]
Niu, L.: System-Level Energy-Efficient Scheduling for Hard Real-Time Embedded Systems [p. 281]
Nocco, S.: Interpolation Sequences Revisited [p. 317]; Optimized Model Checking of Multiple Properties [p. 543]
Noguera, J.: Building Real-time HDTV Applications in FPGAs Using Processors, AXI Interfaces and High Level Synthesis Tools [p. 848]; Fast Startup for Spartan-6 FPGAs Using Dynamic Partial Reconfiguration [p. 1542]
Nouet, P.: An Electrical Test Method for MEMS Convective Accelerometers: Development and Evaluation [p. 806]
Nowak, J.: Strategies for Initial Sizing and Operating Point Analysis of Analog Circuits [p. 1672]
Nowick, S.M.: A Delay-Insensitive Bus-Invert Code and Hardware Support for Robust Asynchronous Global Communication [p. 1370]

O'Connor, I.: Multi-Granularity Thermal Evaluation of 3D MPSoC Architectures [p. 575]; Optical Ring Network-on-Chip (ORNoC): Architecture and Design Methodology [p. 788]
Omrane, B.: 2D and 3D Integration with Organic and Silicon Electronics [p. 899]
Onizawa, N.: Interconnect-Fault-Resilient Delay-Insensitive Asynchronous Communication Link Based on Current-Flow Monitoring [p. 776]
Orailoglu, A.: Register Allocation for Simultaneous Reduction of Energy and Peak Temperature on Registers [p. 20]; Diagnosing Scan Chain Timing Faults through Statistical Feature Analysis of Scan Images [p. 185]; Frugal but Flexible Multicore Topologies in Support of Resource Variation-Driven Adaptivity [p. 1255]; Adaptive Test Optimization through Real Time Learning of Test Effectiveness [p. 1430]
Orshansky, M.: Controlled Timing-Error Acceptance for Low Energy IDCT Design [p. 758]
Ost, L.C.: Evaluating Energy Consumption of Homogeneous MPSoCs Using Spare Tiles [p. 1164]
Ottavi, M.: Feedback Based Droop Mitigation [p. 879]
Ottella, M.: System Level Techniques to Improve Reliability in High Power Microcontrollers for Automotive Applications [p. 1123]

Paek, Y.: I²CRF: Incremental Interconnect Customization for Embedded Reconfigurable Fabrics [p. 1346]
Palem, K.: Energy Parsimonious Circuit Design through Probabilistic Pruning [p. 764]
Palesi, M.: Run-Time Deadlock Detection in Networks-on-Chip Using Coupled Transitive Closure Networks [p. 497]
Palframan, D.J.: Time Redundant Parity for Low-Cost Transient Error Detection [p. 52]
Pan, S.: A Cost-Effective Substantial-Impact-Filter Based Method to Tolerate Voltage Emergencies [p. 311]
Pande, P.: Sustainability through Massively Integrated Computing: Are We Ready to Break the Energy Efficiency Wall for Single-Chip Platforms? [p. 1656]
Pangrle, B.: Beyond UPF & CPF: Low-Power Design and Verification [p. 252]
Papa, C.: Smart Systems at ST [p. 1230]
Papadas, C.: System-Level Power Estimation Methodology Using Cycle- and Bit-Accurate TLM [p. 1125]
Papaefstathiou, I.: Parallel Accelerators for GlimmerHMM Bioinformatics Algorithm [p. 94]
Papaefstathiou, V.: Fine-Grain OpenMP Runtime Support with Explicit Communication Hardware Primitives [p. 891]
Papariello, F.: An Efficient On-Line Task Allocation Algorithm for QoS and Energy Efficiency in Multicore Multimedia Platforms [p. 100]
Park, H.: A Novel Tag Access Scheme for Low Power L2 Cache [p. 655]
Park, S.: I²CRF: Incremental Interconnect Customization for Embedded Reconfigurable Fabrics [p. 1346]
Park, S.P.: Stage Number Optimization for Switched Capacitor Power Converters in Micro-Scale Energy Harvesting [p. 770]
Parthasarathy, H.: Circuit and DFT Techniques for Robust and Low Cost Qualification of a Mixed-Signal SoC with Integrated Power Management System [p. 551]
Pasetti, G.: Characterization of an Intelligent Power Switch for LED Driving with Control of Wiring Parasitics Effects [p. 1119]
Patel, H.D.: Abstract State Machines as an Intermediate Representation for High-Level Synthesis [p. 1406]
Paterna, F.: An Efficient On-Line Task Allocation Algorithm for QoS and Energy Efficiency in Multicore Multimedia Platforms [p. 100]
Paul, S.: Architecture and FPGA-Implementation of a High Throughput K⁺-Best Detector [p. 240]
Paulin, P.: Optical Ring Network-on-Chip (ORNoC): Architecture and Design Methodology [p. 788]
Pavlenko, E.: STABLE: A New QF-BV SMT Solver for Hard Verification Problems combining Boolean Reasoning with Computer Algebra [p. 155]
Pavlidis, V.F.: Analytical Heat Transfer Model for Thermal Through-Silicon Vias [p. 395]
Pedram, M.: Variation Aware Dynamic Power Management for Chip Multiprocessor Architectures [p. 473]; Battery-Supercapacitor Hybrid System for High-Rate Pulsed Load Applications [p. 875]; Timing Variation-Aware Custom Instruction Extension Technique [p. 1517]
Peikenkamp, T.: Using Contract-Based Component Specifications for Virtual Integration Testing and Architecture Design [p. 1023]
Peizerat, A.: Smart Imagers of the Future [p. 437]
Penolazzi, S.: Predicting Bus Contention Effects on Energy and Performance in Multi-Processor SoCs [p. 1196]
Perathoner, S.: Composing Heterogeneous Components for System-Wide Performance Analysis [p. 842]
Perini, F.: An Efficient Quantum-Dot Cellular Automata Adder [p. 1220]
Pétrot, F.: Speeding-up SIMD Instructions Dynamic Binary Translation in Embedded Processor Simulation [p. 277]
Phadke, S.: MLP Aware Heterogeneous Memory System [p. 956]
Pichot, V.: Low Power Smart Industrial Control [p. 595]
Pigorsch, F.: Integration of Orthogonal QBF Solving Techniques [p. 149]
Piguet, C.: Energy Parsimonious Circuit Design through Probabilistic Pruning [p. 764]
Pino, R.E.: 3D-ICML: A 3D Bipolar ReRAM Design with Interleaved Complementary Memory Layers [p. 583]
Polarouthu, S.: Circuit and DFT Techniques for Robust and Low Cost Qualification of a Mixed-Signal SoC with Integrated Power Management System [p. 551]
Polian, I.: Adaptive Voltage Over-Scaling for Resilient Applications [p. 944]
Politis, S.: System-Level Power Estimation Methodology Using Cycle- and Bit-Accurate TLM [p. 1125]
Pomeranz, I.: Built-In Generation of Functional Broadside Tests [p. 1297]; Hyper-Graph Based Partitioning to Reduce DFT Cost for Pre-Bond 3D-IC Testing [p. 1424]
Poncino, M.: Partitioned Cache Architectures for Reduced NBTI-Induced Aging [p. 938]; System Level Techniques to Improve Reliability in High Power Microcontrollers for Automotive Applications [p. 1123]; Moving to Green ICT: From Stand-Alone Power-Aware IC Design to an Integrated Approach to Energy Efficient Design of Heterogeneous Electronic Systems [p. 1127]
Pontarelli, S.: Feedback Based Droop Mitigation [p. 879]
Porquet, J.: NoC-MPU: A Secure Architecture for Flexible Co-Hosting on Shared Memory MPSoCs [p. 591]
Pozzi, L.: Slack-Aware Scheduling on Coarse Grained Reconfigurable Arrays [p. 1513]
Pribyl, W.: A Method for Fast Jitter Tolerance Analysis of High-Speed PLLs [p. 1107]
Psarakis, M.: Architectures for Online Error Detection and Recovery in Multicore Processors [p. 533]
Puers, R.: Systematic Design of a Programmable Low-Noise CMOS Neural Interface for Cell Activity Recording [p. 818]
Puschini, D.: Sustainability through Massively Integrated Computing: Are We Ready to Break the Energy Efficiency Wall for Single-Chip Platforms? [p. 1656]

Qiao, P.: A 0.964mW Digital Hearing Aid System [p. 883]
Qin, Z.: An Endurance-Enhanced Flash Translation Layer via Reuse for NAND Flash Memory Storage Systems [p. 14]
Quan, G.: Leakage Aware Energy Minimization for Real-Time Systems under the Maximum Temperature Constraint [p. 479]
Quer, S.: Interpolation Sequences Revisited [p. 317]

Raabe, A.: A Workflow for Runtime Adaptive Task Allocation on Heterogeneous MPSoCs [p. 1129]; Priority Division: A High-Speed Shared-Memory Bus Arbitration with Bounded Latency [p. 1497]
Rabaey, J.M.: Powering and Communicating with mm-size Implants [p. 722]
Raghunathan, A.: VESPA: Variability Emulation for System-on-Chip Performance Analysis [p. 2]; Design of Voltage-Scalable Meta Functions for Approximate Computing [p. 950]
Raghunathan, V.: Stage Number Optimization for Switched Capacitor Power Converters in Micro-Scale Energy Harvesting [p. 770]
Rahagude, N.: Design-for-Test Methodology for Non-Scan At-Speed Testing [p. 191]
Rahimi, A.: A Fully-Synthesizable Single-Cycle Interconnection Network for Shared-L1 Processor Clusters [p. 491]
Rahman, M.: Power Reduction via Near-Optimal Library-Based Cell-Size Selection [p. 867]
Rai, D.: Worst-Case Temperature Analysis for Real-Time Systems [p. 631]
Rajgopal, S.: High-Temperature (>500°C) Reconfigurable Computing Using Silicon Carbide NEMS Switches [p. 1065]
Ramachandran, P.: Architectures for Online Error Detection and Recovery in Multicore Processors [p. 533]
Ramesh, S.: When to Stop Verification? Statistical Trade-Off between Expected Loss and Simulation Cost [p. 1309]
Rana, V.: An Efficient Quantum-Dot Cellular Automata Adder [p. 1220]; A High-Performance Parallel Implementation of the Chambolle Algorithm [p. 1436]
Ranganathan, N.: A New Reversible Design of BCD Adder [p. 1180]
Razaghi, P.: Host-Compiled Multicore RTOS Simulator for Embedded Real-Time Software Development [p. 222]
Réal, D.: Enhancement of Simple Electro-Magnetic Attacks by Pre-Characterization in Frequency Domain and Demodulation Techniques [p. 1004]
Rebeiro, C.: Theoretical Modeling of the Itoh-Tsujii Inversion Algorithm for Enhanced Performance on k-LUT Based FPGAs [p. 1231]
Reddy, P.: A Low Complexity Stopping Criterion for Reducing Power Consumption in Turbo Decoders [p. 649]
Reddy, S.M.: Hyper-Graph Based Partitioning to Reduce DFT Cost for Pre-Bond 3D-IC Testing [p. 1424]
Reid, D.: Modeling Circuit Performance Variations Due to Statistical Variability: Monte Carlo Static Timing Analysis [p. 1537]
Reimer, S.: Integration of Orthogonal QBF Solving Techniques [p. 149]
Rekik, A.A.: An Electrical Test Method for MEMS Convective Accelerometers: Development and Evaluation [p. 806]
Rémond, E.: Mathematical Approach Based on a "Design of Experiment" to Simulate Process Variations [p. 1486]
Reynaert, P.: Global Optimization of Integrated Transformers for High Frequency Microwave Circuits Using a Gaussian Process Based Surrogate Model [p. 1101]
Richardson, S.: Intermediate Representations for Controllers in Chip Generators [p. 1394]
Rinaudo, S.: Moving to Green ICT: From Stand-Alone Power-Aware IC Design to an Integrated Approach to Energy Efficient Design of Heterogeneous Electronic Systems [p. 1127]
Rocchi, A.: A Sensor Fusion Algorithm for an Integrated Angular Position Estimation with Inertial Measurement Units [p. 273]
Romeo, M.: Solid State Photodetectors for Nuclear Medical Imaging Applications [p. 511]
Roop, P.S.: Pruning Infeasible Paths for Tight WCRT Analysis of Synchronous Programs [p. 204]
Rosenstiel, W.: Scalable Hybrid Verification for Embedded Software [p. 179]; Fast and Accurate Resource Conflict Simulation for Performance Analysis of Multi-Core Systems [p. 210]
Rossi, D.: Error Correcting Code Analysis for Cache Memory High Reliability and Performance [p. 1620]
Roussel, P.: Variability Aware Modeling for Yield Enhancement of SRAM and Logic [p. 1153]
Roy, K.: Stage Number Optimization for Switched Capacitor Power Converters in Micro-Scale Energy Harvesting [p. 770]; Design of Voltage-Scalable Meta Functions for Approximate Computing [p. 950]
Roy, S.: Topologically Homogeneous Power-Performance Heterogeneous Multicore Systems [p. 125]; Waste-Aware Dilution and Mixing of Biochemical Samples with Digital Microfluidic Biochips [p. 1059]; Modeling Circuit Performance Variations Due to Statistical Variability: Monte Carlo Static Timing Analysis [p. 1537]
Roy, S.S.: Theoretical Modeling of the Itoh-Tsujii Inversion Algorithm for Enhanced Performance on k-LUT Based FPGAs [p. 1231]
Roychowdhury, J.: SAMURAI: An Accurate Method for Modeling and Simulating Non-Stationary Random Telegraph Noise in SRAMs [p. 1113]
Ruf, J.: Scalable Hybrid Verification for Embedded Software [p. 179]
Ruggeri, M.: An Effective Multi-Source Energy Harvester for Low Power Applications [p. 836]

Sabatelli, S.: A Sensor Fusion Algorithm for an Integrated Angular Position Estimation with Inertial Measurement Units [p. 273]
Sabatini, M.: Energy Analysis Methods and Tools For Modelling and Optimizing Tyre Systems [p. 1121]
Sabbarwal, P.: Circuit and DFT Techniques for Robust and Low Cost Qualification of a Mixed-Signal SoC with Integrated Power Management System [p. 551]
Sabry, M.M.: Towards Thermally-Aware Design of 3D MPSoCs with Inter-Tier Cooling [p. 1466]
Safar, M.: A Reconfigurable, Pipelined, Conflict Directed Jumping Search SAT Solver [p. 1243]
Safarpour, S.: Automated Debugging of SystemVerilog Assertions [p. 323]
Sakare, M.: Testing of High-Speed DACs Using PRBS Generation with "Alternate-Bit-Tapping" [p. 377]
Salcic, Z.: DynOAA - Dynamic Offset Adaptation Algorithm for Improving Response Times of CAN Systems [p. 269]
Salem, A.: A Reconfigurable, Pipelined, Conflict Directed Jumping Search SAT Solver [p. 1243]
Salsano, A.: Feedback Based Droop Mitigation [p. 879]
Sampaio, A.M.: System-Level Modeling of a Mixed-Signal System on Chip for Wireless Sensor Networks [p. 1501]
Sanchez, E.: Fault Grading of Software-Based Self-Test Procedures for Dependable Automotive Applications [p. 513]
Sander, I.: Predicting Bus Contention Effects on Energy and Performance in Multi-Processor SoCs [p. 1196]
Sander, O.: Fast Startup for Spartan-6 FPGAs Using Dynamic Partial Reconfiguration [p. 1542]
Sandhu, S.: A Confidence-Driven Model for Error-Resilient Computing [p. 1608]
Sanghani, A.: A Clock-Gating Based Capture Power Droop Reduction Methodology for At-Speed Scan Testing [p. 197]
Sangiovanni-Vincentelli, A.: Component-Based Design for the Future [p. 1029]
Santambrogio, M.D.: A High-Performance Parallel Implementation of the Chambolle Algorithm [p. 1436]
Sapatnekar, S.: A Scaled Random Walk Solver for Fast Power Grid Analysis [p. 38]
Sapatnekar, S.S.: Enabling Improved Power Management in Multicore Processors through Clustered DVFS [p. 293]
Saponara, S.: Characterization of an Intelligent Power Switch for LED Driving with Control of Wiring Parasitics Effects [p. 1119]
Sarangi, S.: A Clock-Gating Based Capture Power Droop Reduction Methodology for At-Speed Scan Testing [p. 197]
Sarbazi-Azad, H.: Supporting Non-Contiguous Processor Allocation in Mesh-Based CMPs Using Virtual Point-to-Point Links [p. 413]
Sartori, J.: On the Efficacy of NBTI Mitigation Techniques [p. 932]
Sassateli, G.: Achieving Composability in NoC-Based MPSoCs Through QoS Management at Software Level [p. 407]
Satpathy, S.: Low Power Interconnects for SIMD Computers [p. 600]
Schaefer, E.: A New Method for Automated Generation of Compensation Networks - The EDA Designer Finger [p. 1666]
Schaumont, P.: Data-Oriented Performance Analysis of SHA-3 Candidates on FPGA Accelerated Computers [p. 1650]
Schenkelaars, T.: Optimal Scheduling of Switched FlexRay Networks [p. 926]
Schirrmeister, F.: Virtual Manycore Platforms: Moving Towards 100+ Processor Cores [p. 715]
Schmidt, J.-M.: Low-cost Fault Detection Method for ECC Using Montgomery Powering Ladder [p. 1016]
Schneider, R.: Re-Engineering Cyber-Physical Control Applications for Hybrid Communication Protocols [p. 914]
Schoellkopf, J.-P.: System-Level Power Estimation Methodology Using Cycle- and Bit-Accurate TLM [p. 1125]
Scholl, C.: Integration of Orthogonal QBF Solving Techniques [p. 149]
Schulte, M.: Scratchpad Memory Optimizations for Digital Signal Processing Applications [p. 974]
Schumann, J.: A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation [p. 1590]
Schwarz, C.: NoC-MPU: A Secure Architecture for Flexible Co-Hosting on Shared Memory MPSoCs [p. 591]
Sciolla, M.: System Level Techniques to Improve Reliability in High Power Microcontrollers for Automotive Applications [p. 1123]
Sciuto, D.: An Efficient Quantum-Dot Cellular Automata Adder [p. 1220]
Sechen, C.: Power Reduction via Near-Optimal Library-Based Cell-Size Selection [p. 867]
Sechi, F.: A Sensor Fusion Algorithm for an Integrated Angular Position Estimation with Inertial Measurement Units [p. 273]
Seelisch, F.: STABLE: A New QF-BV SMT Solver for Hard Verification Problems combining Boolean Reasoning with Computer Algebra [p. 155]
Segura, J.: Stability Optimization of Embedded 8T SRAMs Using Word-Line Voltage Modulation [p. 986]; An Efficient and Scalable STA Tool with Direct Path Estimation and Exhaustive Sensitization Vector Exploration for Optimal Delay Computation [p. 1602]
Sekanina, L.: A Global Postsynthesis Optimization Method for Combinational Circuits [p. 1525]
Seo, J.: Battery-Supercapacitor Hybrid System for High-Rate Pulsed Load Applications [p. 875]
Serventi, R.: Characterization of an Intelligent Power Switch for LED Driving with Control of Wiring Parasitics Effects [p. 1119]
Seshia, S.A.: Counterexample-Guided SMT-Driven Optimal Buffer Sizing [p. 329]
Sha, E.H.-M.: Towards Energy Efficient Hybrid On-Chip Scratch Pad Memory with Non-Volatile Memory [p. 746]
Shafique, M.: Minority-Game-Based Resource Allocation for Run-Time Reconfigurable Multi-Core Processors [p. 1261]; Multi-Level Pipelined Parallel Hardware Architecture for High Throughput Motion and Disparity Estimation in Multiview Video Coding [p. 1448]; mRTS: Run-Time System for Reconfigurable Processors with Multi-Grained Instruction-Set Extensions [p. 1554]
Shah, H.: Priority Division: A High-Speed Shared-Memory Bus Arbitration with Bounded Latency [p. 1497]
Shalan, M.: A Reconfigurable, Pipelined, Conflict Directed Jumping Search SAT Solver [p. 1243]
Shanbhag, N.: System-Assisted Analog Mixed-Signal Design [p. 1491]
Shanbhag, N.R.: Timing Error Statistics for Energy-Efficient Robust DSP Systems [p. 285]
Shao, Z.: An Endurance-Enhanced Flash Translation Layer via Reuse for NAND Flash Memory Storage Systems [p. 14]
Shen, H.: Empirical Design Bugs Prediction for Verification [p. 161]
Shen, L.: A Specialized Low-Cost Vectorized Loop Buffer for Embedded Processors [p. 1200]
Sheridan, D.: Towards Coverage Closure: Using Goldmine Assertions for Generating Design Validation Stimulus [p. 173]
Shi, X.: An Efficient Mask Optimization Method Based on Homotopy Continuation Technique [p. 1053]
Shih, C.-S.: Pipeline Schedule Synthesis for Real-Time Streaming Tasks with Inter/Intra-Instance Precedence Constraints [p. 1321]
Shim, K.: Temporal Parallel Simulation: A Fast Gate-Level HDL Simulation Using Higher Level Models [p. 1584]
Shin, D.: Battery-Supercapacitor Hybrid System for High-Rate Pulsed Load Applications [p. 875]; A New Circuit Simplification Method for Error Tolerant Applications [p. 1566]
Shin, J.: Early Chip Planning Cockpit [p. 863]
Shurek, G.: A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation [p. 1590]
Siegl, S.: Formal Specification and Systematic Model-Driven Testing of Embedded Automotive Systems [p. 118]
Sifakis, J: Methods and Tools for Component-Based System Design [p. 1022]
Silveira, L.M.: Fast Statistical Analysis of RC Nets Subject to Manufacturing Variabilities [p. 32]
Singer, A.: System-Assisted Analog Mixed-Signal Design [p. 1491]
Singh, M.: Testing of High-Speed DACs Using PRBS Generation with "Alternate-Bit-Tapping" [p. 377]
Sinha, A.: Data-Oriented Performance Analysis of SHA-3 Candidates on FPGA Accelerated Computers [p. 1650]
Sinha, R.: Abstract State Machines as an Intermediate Representation for High-Level Synthesis [p. 1406]
Skadron, K.: Reducing the Cost of Redundant Execution in Safety-Critical Systems Using Relaxed Dedication [p. 1249]
Slamani, M.: Correlating Inline Data with Final Test Outcomes in Analog/RF Devices [p. 812]
Soeken, M.: Verifying Dynamic Aspects of UML Models [p. 1077]
Somenzi, F.: Clause Simplification through Dominator Analysis [p. 143]
Sommer, R.: A New Method for Automated Generation of Compensation Networks - The EDA Designer Finger [p. 1666]; Strategies for Initial Sizing and Operating Point Analysis of Analog Circuits [p. 1672]
Sorin, D.: Architectures for Online Error Detection and Recovery in Multicore Processors [p. 533]
Sotiriades, E.: Parallel Accelerators for GlimmerHMM Bioinformatics Algorithm [p. 94]
Spica, M.: Error Correcting Code Analysis for Cache Memory High Reliability and Performance [p. 1620]
Sporrer, C.: A New Method for Automated Generation of Compensation Networks - The EDA Designer Finger [p. 1666]
Sreedhar, A.: On Design of Test Structures for Lithographic Process Corner Identification [p. 800]; Modeling Manufacturing Process Variation for Design and Test [p. 1147]; Physically Unclonable Functions for Embedded Security Based on Lithographic Variation [p. 1632]
Sridhar, A.: Towards Thermally-Aware Design of 3D MPSoCs with Inter-Tier Cooling [p. 1466]
Srivastava, M.: Variability-Aware Duty Cycle Scheduling in Long Running Embedded Sensing Systems [p. 131]
Stattelmann, S.: Fast and Accurate Resource Conflict Simulation for Performance Analysis of Multi-Core Systems [p. 210]
Sterpone, L.: A New Reconfigurable Clock-Gating Technique for Low Power SRAM-Based FPGAs [p. 752]
Stevenson, P.: Intermediate Representations for Controllers in Chip Generators [p. 1394]
Stewart, R.: Fast Startup for Spartan-6 FPGAs Using Dynamic Partial Reconfiguration [p. 1542]
Stierand, I.: Using Contract-Based Component Specifications for Virtual Integration Testing and Architecture Design [p. 1023]
Stoffel, D.: STABLE: A New QF-BV SMT Solver for Hard Verification Problems combining Boolean Reasoning with Computer Algebra [p. 155]
Strano, A.: Exploiting Network-on-Chip Structural Redundancy for a Cooperative and Scalable Built-In Self-Test Architecture [p. 661]
Streichert, T.: An Automated Data Structure Migration Concept - From CAN to Ethernet/IP in Automotive Embedded Systems (CANoverIP) [p. 112]
Struzyna, M.: Flow-based Partitioning and Position Constraints in VLSI Placement [p. 607]
Sumikawa, N.: Multidimensional Parametric Test Set Optimization of Wafer Probe Data for Predicting in Field Failures and Setting Tighter Test Limits [p. 794]
Sun, Z.: A UML 2-Based Hardware/Software Co-Design Framework for Body Sensor Network Applications [p. 1505]
Sutardja, C.: Powering and Communicating with mm-size Implants [p. 722]
Sylvester, D.: Low Power Interconnects for SIMD Computers [p. 600]; A Confidence-Driven Model for Error-Resilient Computing [p. 1608]
Sylvester, M.: Strategies for Initial Sizing and Operating Point Analysis of Analog Circuits [p. 1672]
Szczukiewicz, S.: Towards Thermally-Aware Design of 3D MPSoCs with Inter-Tier Cooling [p. 1466]

Tahar, S.: Ensuring Correctness of Analog Circuits in Presence of Noise and Process Variations Using Pattern Matching [p. 1188]
Tahoori, M.B.: Soft Error Rate Estimation of Digital Circuits in the Presence of Multiple Event Transients (METs) [p. 70]
Tang, C.: Powering and Communicating with mm-size Implants [p. 722]
Tang, Q.: Pseudo Circuit Model for Representing Uncertainty in Waveforms [p. 1521]
Tanimura, K.: Slack-Aware Scheduling on Coarse Grained Reconfigurable Arrays [p. 1513]
Tasic, B.: Test Time Reduction in Analogue/Mixed-Signal Devices by Defect Oriented Testing: An Industrial Example [p. 371]
Taskin, B.: Steiner Tree Based Rotary Clock Routing with Bounded Skew and Capacitive Load Balancing [p. 455]
Tavakkol, A.: Supporting Non-Contiguous Processor Allocation in Mesh-Based CMPs Using Virtual Point-to-Point Links [p. 413]
Tchagaspanian, M.: Smart Imagers of the Future [p. 437]
Tehranipoor, M.: RON: An On-Chip Ring Oscillator Network for Hardware Trojan Detection [p. 1638]
Teich, J.: An Automated Data Structure Migration Concept - From CAN to Ethernet/IP in Automotive Embedded Systems (CANoverIP) [p. 112]; DynOAA - Dynamic Offset Adaptation Algorithm for Improving Response Times of CAN Systems [p. 269]; A Rule-Based Static Dataflow Clustering Algorithm for Efficient Embedded Software Synthesis [p. 521]
Temiz, Y.: Towards Thermally-Aware Design of 3D MPSoCs with Inter-Tier Cooling [p. 1466]
Tendulkar, P.: Fine-Grain OpenMP Runtime Support with Explicit Communication Hardware Primitives [p. 891]
Tennakoon, H.: Power Reduction via Near-Optimal Library-Based Cell-Size Selection [p. 867]
Thapliyal, H.: A New Reversible Design of BCD Adder [p. 1180]
Theocharides, T.: Depth-Directed Hardware Object Detection [p. 1442]
Thiele, L.: Worst-Case Temperature Analysis for Real-Time Systems [p. 631]; Composing Heterogeneous Components for System-Wide Performance Analysis [p. 842]; X-SENSE: Sensing in Extreme Environments [p. 1460]
Thome, J.R.: Towards Thermally-Aware Design of 3D MPSoCs with Inter-Tier Cooling [p. 1466]
Thorolfsson, T.: An Energy-Efficient 64-QAM MIMO Detector for Emerging Wireless Standards [p. 246]
Tilli, A.: A Distributed and Self-Calibrating Model-Predictive Controller for Energy and Thermal Management of High-Performance Multicores [p. 830]
Timoncini, N.: Error Correcting Code Analysis for Cache Memory High Reliability and Performance [p. 1620]
Tinfena, F.: Characterization of an Intelligent Power Switch for LED Driving with Control of Wiring Parasitics Effects [p. 1119]
Tino, A.: Multi-Objective Tabu Search Based Topology Generation Technique for Application-Specific Network-on-Chip Architectures [p. 485]
Tiwari, P.: Power Management Verification Experiences in Wireless SoCs [p. 507]
Topham, N.: Virtual Manycore Platforms: Moving Towards 100+ Processor Cores [p. 715]
Torrens, G.: Stability Optimization of Embedded 8T SRAMs Using Word-Line Voltage Modulation [p. 986]
Trajcevski, G.: Efficient Parameter Variation Sampling for Architecture Simulations [p. 1578]
Trajkovic, J.: Optical Ring Network-on-Chip (ORNoC): Architecture and Design Methodology [p. 788]
Traulsen, C.: Compiling SyncCharts to Synchronous C [p. 563]
Tsai, T.-Y.: On Routing Fixed Escaped Boundary Pins for High Speed Boards [p. 461]
Tsay, R.-S.: DOM: A Data-Dependency-Oriented Modeling Approach for Efficient Simulation of OS Preemptive Scheduling [p. 335]; Cycle-Count-Accurate Processor Modeling for Fast and Accurate System-Level Simulation [p. 341]; A Shared-Variable-Based Synchronization Approach to Efficient Cache Coherence Simulation for Multi-Core Systems [p. 347]
Tseng, C.-K.: Black-Box Leakage Power Modeling for Cell Library and SRAM Compiler [p. 637]
Tseng, W.-C.: Towards Energy Efficient Hybrid On-Chip Scratch Pad Memory with Non-Volatile Memory [p. 746]
Tsukiyama, S.: An Algorithm to Improve Accuracy of Criticality in Statistical Static Timing Analysis [p. 1529]
Ttofis, C.: Depth-Directed Hardware Object Detection [p. 1442]
Tuohy, W.: Towards Coverage Closure: Using Goldmine Assertions for Generating Design Validation Stimulus [p. 173]
Turkewadikar, S.: Circuit and DFT Techniques for Robust and Low Cost Qualification of a Mixed-Signal SoC with Integrated Power Management System [p. 551]

Valgimigli, F.: An Integrated Platform for Advanced Diagnostics [p. 1454]
van Beurden, M.: Test Time Reduction in Analogue/Mixed-Signal Devices by Defect Oriented Testing: An Industrial Example [p. 371]
van der Kolk, K.-J.: Fast Statistical Analysis of RC Nets Subject to Manufacturing Variabilities [p. 32]
van der Meijs, N.: Fast Statistical Analysis of RC Nets Subject to Manufacturing Variabilities [p. 32]; Pseudo Circuit Model for Representing Uncertainty in Waveforms [p. 1521]
Van der Plas, G.: An Analytical Compact Model for Estimation of Stress in Multiple Through-Silicon Via Configurations [p. 505]
van der Wolf, P.: SoC Infrastructures for Predictable System Integration [p. 857]
Vasicek, Z.: A Global Postsynthesis Optimization Method for Combinational Circuits [p. 1525]
Vasudevan, S.: Towards Coverage Closure: Using Goldmine Assertions for Generating Design Validation Stimulus [p. 173]; Efficient Validation Input Generation in RTL by Hybridized Source Code Analysis [p. 1596]
Vatajelu, E.I.: Robustness Analysis of 6T SRAMs in Memory Retention Mode under PVT Variations [p. 980]
Veneris, A.: Automated Debugging of SystemVerilog Assertions [p. 323]
Venkatesan, R.: VESPA: Variability Emulation for System-on-Chip Performance Analysis [p. 2]
Venugopalan, S.: SAMURAI: An Accurate Method for Modeling and Simulating Non-Stationary Random Telegraph Noise in SRAMs [p. 1113]
Vera, X.: Architectures for Online Error Detection and Recovery in Multicore Processors [p. 533]
Verbauwhede, I.: Low-cost Fault Detection Method for ECC Using Montgomery Powering Ladder [p. 1016]
Verdant, A.: Smart Imagers of the Future [p. 437]
Vermeulen, B.: Optimal Scheduling of Switched FlexRay Networks [p. 926]
Vidal, J.: Dynamic Applications on Reconfigurable Systems: From UML Model Design to FPGAs Implementation [p. 1208]
Vijayaraghavan, R.C.: Circuit and DFT Techniques for Robust and Low Cost Qualification of a Mixed-Signal SoC with Integrated Power Management System [p. 551]
Visintainer, F.: Sensor Networks on the Car: State of the Art and Future Challenges [p. 1030]
Vissers, K.: Building Real-time HDTV Applications in FPGAs Using Processors, AXI Interfaces and High Level Synthesis Tools [p. 848]
Vivet, P.: 3D Embedded Multi-Core: Some Perspectives [p. 1327]
von Hanxleden, R.: Compiling SyncCharts to Synchronous C [p. 563]
Vrudhula, S.: Reliability-aware Thermal Management for Hard Real-time Applications on Multi-core Processors [p. 137]

Wachs, M.: Intermediate Representations for Controllers in Chip Generators [p. 1394]
Wagner, F.R.: Improving the Efficiency of a Hardware Transactional Memory on an NoC-based MPSoC [p. 1168]
Wagner, I.: Distributed Hardware Matcher Framework for SoC Survivability [p. 305]
Wagner, M.: Powering and Communicating with mm-size Implants [p. 722]
Wang, C.: Evaluating the Potential of Graphics Processors for High Performance Embedded Computing [p. 709]
Wang, G.: Coordinate Strip-Mining and Kernel Fusion to Lower Power Consumption on GPU [p. 1216]
Wang, K.: Optimization of Stateful Hardware Acceleration in Hybrid Architectures [p. 567]
Wang, L.: Wireless Communication and Energy Harvesting in Automobiles [p. 1042]; Accelerated Simulation of Tunable Vibration Energy Harvesting Systems Using a Linearised State-Space Technique [p. 1267]
Wang, L.-C.: Multidimensional Parametric Test Set Optimization of Wafer Probe Data for Predicting in Field Failures and Setting Tighter Test Limits [p. 794]
Wang, P.-C.: DOM: A Data-Dependency-Oriented Modeling Approach for Efficient Simulation of OS Preemptive Scheduling [p. 335]
Wang, P.-Y.: An All-Digital Built-In Self-Test Technique for Transfer Function Characterization of RF PLLs [p. 359]
Wang, X.: High-Temperature (>500°C) Reconfigurable Computing Using Silicon Carbide NEMS Switches [p. 1065]
Wang, Y.: An Endurance-Enhanced Flash Translation Layer via Reuse for NAND Flash Memory Storage Systems [p. 14]; Gemma in April: A Matrix-Like Parallel Programming Architecture on OpenCL [p. 703]; Battery-Supercapacitor Hybrid System for High-Rate Pulsed Load Applications [p. 875]; FlexMemory: Exploiting and Managing Abundant Off-Chip Optical Bandwidth [p. 968]; Modeling Circuit Performance Variations Due to Statistical Variability: Monte Carlo Static Timing Analysis [p. 1537]
Wang, Z.: An Approach to Improve Accuracy of Source-Level TLMs of Embedded Software [p. 216]; A Specialized Low-Cost Vectorized Loop Buffer for Embedded Processors [p. 1200]
Wang, Z.-C.: A New Architecture for Power Network in 3D IC [p. 401]
Wanner, L.: Variability-Aware Duty Cycle Scheduling in Long Running Embedded Sensing Systems [p. 131]
Watanabe, Y.: Realistic Performance-Constrained Pipelining in High-Level Synthesis [p. 1382]
Weddell, A.S.: Ultra Low-Power Photovoltaic MPPT Technique for Indoor and Outdoor Wireless Sensor Nodes [p. 905]; Accelerated Simulation of Tunable Vibration Energy Harvesting Systems Using a Linearised State-Space Technique [p. 1267]
Wedler, M.: STABLE: A New QF-BV SMT Solver for Hard Verification Problems combining Boolean Reasoning with Computer Algebra [p. 155]
Weger, A.J.: Early Chip Planning Cockpit [p. 863]
Wehn, N.: Design Space Exploration for 3D-Stacked DRAMs [p. 389]
Weis, C.: Design Space Exploration for 3D-Stacked DRAMs [p. 389]
Welp, T.: An Approach for Dynamic Selection of Synthesis Transformations Based on Markov Decision Processes [p. 1533]
Wen, X.: Transition-Time-Relation Based Capture-Safety Checking for At-Speed Scan Test Generation [p. 895]
Weng, C.-C.: Black-Box Leakage Power Modeling for Cell Library and SRAM Compiler [p. 637]
Weng, T.: Understanding the Role of Buildings in a Smart Microgrid [p. 1224]
Werthimer, D.: Powering and Communicating with mm-size Implants [p. 722]
Wiegand, T.: Architecture and FPGA-Implementation of a High Throughput K⁺-Best Detector [p. 240]
Wille, R.: Verifying Dynamic Aspects of UML Models [p. 1077]; Determining the Minimal Number of Lines for Large Reversible Circuits [p. 1204]
Winemberg, L.: Multidimensional Parametric Test Set Optimization of Wafer Probe Data for Predicting in Field Failures and Setting Tighter Test Limits [p. 794]
Wink, T.: MARC II: A Parametrized Speculative Multi-Ported Memory Subsystem for Reconfigurable Computers [p. 1352]
Winter, M.: Guaranteed Service Virtual Channel Allocation in NoCs for Run-Time Task Scheduling [p. 419]
Winterholer, M.: Embedded Software Debug and Test - Needs and Requirements for Innovations in Debugging [p. 721]
Wittmann, R.: Generator Based Approach for Analog Circuit and Layout Design and Optimization [p. 1675]
Woh, M.: Low Power Interconnects for SIMD Computers [p. 600]
Wolff, F.G.: High-Temperature (>500°C) Reconfigurable Computing Using Silicon Carbide NEMS Switches [p. 1065]
Wong, N.: A Block-Diagonal Structured Model Reduction Scheme for Power Grid Networks [p. 44]
Wong, S.: A New Reconfigurable Clock-Gating Technique for Low Power SRAM-Based FPGAs [p. 752]; Targeting Code Diversity with Run-Time Adjustable Issue-Slots in a Chip Multiprocessor [p. 1358]
Wong, W.-F.: A UML 2-Based Hardware/Software Co-Design Framework for Body Sensor Network Applications [p. 1505]
Wright, P.K.: What Does the Power Industry Need from the EDA Industry and What Is the EDA Industry Doing About It? [p. 1541]
Wu, C.-A.: Speeding up MPSoC Virtual Platform Simulation by Ultra Synchronization Checking Method [p. 353]
Wu, D.: Gemma in April: A Matrix-Like Parallel Programming Architecture on OpenCL [p. 703]
Wu, K.: LOEDAR: A Low Cost Error Detection and Recovery Scheme for ECC [p. 1010]
Wu, K.-C.: Aging-Aware Timing Analysis and Optimization Considering Path Sensitization [p. 1572]
Wu, M.-H.: DOM: A Data-Dependency-Oriented Modeling Approach for Efficient Simulation of OS Preemptive Scheduling [p. 335]; Cycle-Count-Accurate Processor Modeling for Fast and Accurate System-Level Simulation [p. 341]; A Shared-Variable-Based Synchronization Approach to Efficient Cache Coherence Simulation for Multi-Core Systems [p. 347]
Wu, T.: Gemma in April: A Matrix-Like Parallel Programming Architecture on OpenCL [p. 703]
Wu, T.-H.: Power-Driven Global Routing for Multi-Supply Voltage Domains [p. 443]
Wu, Y.: Empirical Design Bugs Prediction for Verification [p. 161]
Wunderlich, H.-J.: SAT-Based Fault Coverage Evaluation in the Presence of Unknown Values [p. 1303]

Xia, F.: Run-Time Deadlock Detection in Networks-on-Chip Using Coupled Transitive Closure Networks [p. 497]
Xiao, N.: A Specialized Low-Cost Vectorized Loop Buffer for Embedded Processors [p. 1200]
Xie, X.: Evaluating the Potential of Graphics Processors for High Performance Embedded Computing [p. 709]
Xie, Y.: An Energy-Efficient 3D CMP Design with Fine-Grained Voltage Scaling [p. 539]; Design Implications of Memristor-Based RRAM Cross-Point Structures [p. 734]
Xing, Y.: Test Time Reduction in Analogue/Mixed-Signal Devices by Defect Oriented Testing: An Industrial Example [p. 371]
Xu, C.: Design Implications of Memristor-Based RRAM Cross-Point Structures [p. 734]
Xu, H.: Analytical Heat Transfer Model for Thermal Through-Silicon Vias [p. 395]
Xu, N.: Gemma in April: A Matrix-Like Parallel Programming Architecture on OpenCL [p. 703]
Xu, Q.: On Multiplexed Signal Tracing for Post-Silicon Debug [p. 685]
Xue, C.J.: Register Allocation for Simultaneous Reduction of Energy and Peak Temperature on Registers [p. 20]; Towards Energy Efficient Hybrid On-Chip Scratch Pad Memory with Non-Volatile Memory [p. 746]
Xue, L.: Floorplanning Exploration and Performance Evaluation of a New Network-on-Chip [p. 625]

Yakovlev, A.: Run-Time Deadlock Detection in Networks-on-Chip Using Coupled Transitive Closure Networks [p. 497]; Energy-Modulated Computing [p. 1340]; Redressing Timing Issues for Speed-Independent Circuits in Deep Submicron Age [p. 1376]
Yamato, Y.: Transition-Time-Relation Based Capture-Safety Checking for At-Speed Scan Test Generation [p. 895]
Yan, C.: An Efficient Algorithm for Multi-Domain Clock Skew Scheduling [p. 1364]
Yan, J.-T.: Obstacle-Aware Multiple-Source Rectilinear Steiner Tree with Electromigration and IR-Drop Avoidance [p. 449]; Timing-Constrained I/O Buffer Placement for Flip-Chip Designs [p. 619]
Yang, B.: A Clock-Gating Based Capture Power Droop Reduction Methodology for At-Speed Scan Testing [p. 197]
Yang, C.: Frugal but Flexible Multicore Topologies in Support of Resource Variation-Driven Adaptivity [p. 1255]
Yang, H.: Worst-Case Temperature Analysis for Real-Time Systems [p. 631]; Gemma in April: A Matrix-Like Parallel Programming Architecture on OpenCL [p. 703]
Yang, J.: Proactive Recovery for BTI in High-K SRAM Cells [p. 992]
Yang, S.: A New Distributed Event-Driven Gate-Level HDL Simulation by Accurate Prediction [p. 547]; Case Study: Alleviating Hotspots and Improving Chip Reliability via Carbon Nanotube Thermal Interface [p. 1071]; Temporal Parallel Simulation: A Fast Gate-Level HDL Simulation Using Higher Level Models [p. 1584]
Yang, X.: Robust 6T Si Tunneling Transistor SRAM Design [p. 740]
Ye, J.: On Diagnosis of Multiple Faults Using Compressed Responses [p. 679]
Yeh, C.-T.: A UML 2-Based Hardware/Software Co-Design Framework for Body Sensor Network Applications [p. 1505]
Yeh, Y.-F.: Speeding up MPSoC Virtual Platform Simulation by Ultra Synchronization Checking Method [p. 353]
Yeric, G.: Correlating Models and Silicon for Improved Parametric Yield [p. 1159]
Yeung, P.: Challenges in Designing High Speed Memory Subsystem for Mobile Applications [p. 509]
Yi, W.: Energy-Efficient Scheduling of Real-Time Tasks on Cluster-Based Multicores [p. 1135]
Yip, T.G.: Challenges in Designing High Speed Memory Subsystem for Mobile Applications [p. 509]
Yoo, S.: A Novel Tag Access Scheme for Low Power L2 Cache [p. 655]; A Quantitative Analysis of Performance Benefits of 3D Die Stacking on Mobile and Embedded SoC [p. 1333]
Yoon, J.W.: I²CRF: Incremental Interconnect Customization for Embedded Reconfigurable Fabrics [p. 1346]
Yu, C.-C.: Trigonometric Method to Handle Realistic Error Probabilities in Logic Circuits [p. 64]
Yu, H.: Optimization of Stateful Hardware Acceleration in Hybrid Architectures [p. 567]
Yu, K.: A High-Level Analytical Model for Application Specific CMP Design Exploration [p. 1095]

Zadegan, F.G.: Design Automation for IEEE P1687 [p. 1412]
Zafalon, R.: Solid State Photodetectors for Nuclear Medical Imaging Applications [p. 511]
Zahedi, S.: Variability-Aware Duty Cycle Scheduling in Long Running Embedded Sensing Systems [p. 131]
Zaidi, Y.: Simulation Based Tuning of System Specification [p. 1273]
Zaki, M.H.: Ensuring Correctness of Analog Circuits in Presence of Noise and Process Variations Using Pattern Matching [p. 1188]
Zarrineh, K.: Feedback Based Droop Mitigation [p. 879]
Zatt, B.: Multi-Level Pipelined Parallel Hardware Architecture for High Throughput Motion and Disparity Estimation in Multiview Video Coding [p. 1448]
Zebelein, C.: A Rule-Based Static Dataflow Clustering Algorithm for Efficient Embedded Software Synthesis [p. 521]
Zeng, X.: An Efficient Algorithm for Multi-Domain Clock Skew Scheduling [p. 1364]
Zergainoh, N.-E.: A fault-Tolerant Deadlock-Free Adaptive Routing for On Chip Interconnects [p. 909]; Eliminating Speed Penalty in ECC Protected Memories [p. 1614]
Zhai, A.: Enabling Improved Power Management in Multicore Processors through Clustered DVFS [p. 293]
Zhang, L.: FlexMemory: Exploiting and Managing Abundant Off-Chip Optical Bandwidth [p. 968]
Zhang, W.: Case Study: Alleviating Hotspots and Improving Chip Reliability via Carbon Nanotube Thermal Interface [p. 1071]
Zhang, X.: Gemma in April: A Matrix-Like Parallel Programming Architecture on OpenCL [p. 703]; RON: An On-Chip Ring Oscillator Network for Hardware Trojan Detection [p. 1638]
Zhang, Y.: Floorplanning Exploration and Performance Evaluation of a New Network-on-Chip [p. 625]; Proactive Recovery for BTI in High-K SRAM Cells [p. 992]
Zhang, Z.: A Block-Diagonal Structured Model Reduction Scheme for Power Grid Networks [p. 44]; A Confidence-Driven Model for Error-Resilient Computing [p. 1608]
Zhao, C.: An Extension to SystemC-A to Support Mixed-Technology Systems with Distributed Components [p. 1279]
Zhao, J.: An Energy-Efficient 3D CMP Design with Fine-Grained Voltage Scaling [p. 539]
Zhi, Y.: An Efficient Algorithm for Multi-Domain Clock Skew Scheduling [p. 1364]
Zhou, H.: A High-Level Analytical Model for Application Specific CMP Design Exploration [p. 1095]; An Efficient Algorithm for Multi-Domain Clock Skew Scheduling [p. 1364]
Zhou, H.: Integrated Circuit White Space Redistribution for Temperature Optimization [p. 613]
Zhu, H.: An Efficient Algorithm for Multi-Domain Clock Skew Scheduling [p. 1364]
Zhu, M.: Evaluating the Potential of Graphics Processors for High Performance Embedded Computing [p. 709]
Zhuge, Q.: Towards Energy Efficient Hybrid On-Chip Scratch Pad Memory with Non-Volatile Memory [p. 746]
Ziermann, T.: DynOAA - Dynamic Offset Adaptation Algorithm for Improving Response Times of CAN Systems [p. 269]
Zimmerling, M.: X-SENSE: Sensing in Extreme Environments [p. 1460]
Ziv, A.: A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation [p. 1590]
Zjajo, A.: Pseudo Circuit Model for Representing Uncertainty in Waveforms [p. 1521]
Zuber, P.: Variability Aware Modeling for Yield Enhancement of SRAM and Logic [p. 1153]
Zukoski, A.: Reliability-driven Don't Care Assignment for Logic Synthesis [p. 1560]
Zuo, Q.: Floorplanning Exploration and Performance Evaluation of a New Network-on-Chip [p. 625]
Zwolinski, M.: Modeling Circuit Performance Variations Due to Statistical Variability: Monte Carlo Static Timing Analysis [p. 1537]