DATE 2000 Table of Contents

DATE Sponsor Committee
DATE Executive Committee
Technical Program Chairs
Vendors Committee
Technical Program Committee
Reviewers
Welcome to DATE 2000
Best Paper Awards
Tutorials
Call for Papers for DATE 2001

Plenary -- Keynote Session: Connected, Smart Devices - Computing Beyond the Desktop

Moderator: I. Bolsens, IMEC, B
Speakers: Jerry Fiddler, Chairman and Co-founder of Wind River Systems, USA
Wim Roelandts, CEO Xilinx, USA

Session 1A: Embedded Software Generation

Code Selection for Media Processors with SIMD Instructions [p. 4]

R. Leupers

Analysis of High-Level Address Code Transformations for Programmable Processors [p. 9]

S. Gupta, M. Miranda, F. Catthoor, R. Gupta

Free MDD-based Software Optimization Techniques for Embedded Systems [p. 14]

C. Kim, L. Lavagno, A. Sangiovanni-Vincentelli

Session 1B: Low-Power Issues in System-Level Design

Quantitative Comparison of Power Management Algorithms [p. 20]

Y. Lu, E. Chung, T. Simunic, L. Benini, G. De Micheli

Efficient Power Co-Estimation Techniques for System-On-Chip Design [p. 27]

M. Lajolo, A. Raghunathan, S. Dey, L. Lavagno

A Discrete-Time Battery Model for High-Level Power Estimation [p. 35]

L. Benini, G. Castelli, A. Macii, E. Macii, M. Poncino, R. Scarsi

Session 1C: Circuit Analysis and Synthesis

The Generalized Boundary Curve -- A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits [p. 42]

R. Schwencker, F. Schenkel, H. Graeb, K. Antreich

A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated Circuits [p. 48]

O. Guerra, E. Roca, F. Fernández, A. Rodríguez-Vázquez

Layout-Oriented Synthesis of High Performance Analog Circuits [p. 53]

M. Dessouky, M. Louërat, J. Porte

Technology Mapping and Retargeting for Field-Programmable Analog Arrays [p. 58]

S. Ganesan, R. Vemuri

Embedded Tutorial -- Design Practices for Better Reliability and Yield

Tutorial Statement [p. 66]

The Road to better Reliability and Yield Embedded DfM Tools [p. 67]

K. Veelenturf

Yield Improvement and Repair Trade-Off for Large Embedded Memories [p. 69]

Y. Zorian

Stay Away from Minimum Design-Rule Values [p. 71]

C. Strolenberg

Session 2A: Embedded Tutorial -- System Level Design Using C++

System Level Design using C++ [p. 74]

D. Verkest, J. Kunkel, F. Schirrmeister

Session 2B: IP and Design Reuse

Techniques for Reducing Read Latency of Core Bus Wrappers [p. 84]

R. Lysecky, F. Vahid, T. Givargis

Formalized Three-Layer System-Level Reuse Model and Methodology for Embedded Data-Dominated Applications [p. 92]

F. Vermeulen, F. Catthoor, D. Verkest, H. De Man

Virtual Fault Simulation of Distributed IP-based Designs [p. 99]

M. Dalpasso, A. Bogliolo, L. Benini, M. Favalli

Session 2C: Layout

Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation [p. 106]

X. Tang, R. Tian, D. Wong

A New Effective and Efficient Multi-Level Partitioning Algorithm [p. 112]

Y. Saab

Faster Optimal Single-Row Placement with Fixed Ordering [p. 117]

U. Brenner, J. Vygen

Layout Compaction for Yield Optimization via Critical Area Minimization [p. 122]

Y. Bourai, C. Shi

Session 2D: Heterogeneous Aspects in SOC Testing

Test Synthesis for Mixed-Signal SOC Paths [p. 128]

S. Ozev, I. Bayraktaroglu, A. Orailoglu

Analysis and Minimization of Test Time in a Combined BIST and External Test Approach [p. 134]

M. Sugihara, H. Date, H. Yasuura

CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip [p. 141]

M. Benabdenebi, W. Maroufi, M. Marzouki

Design and Test Space Exploration of Transport-Triggered Architectures [p. 146]

V. Zivkovic, R. Tangelder, H. Kerkhoff

Session 3A: System Specification

Composite Signal Flow: A Computational Model Combining Events, Sampled Streams, and Vectors [p. 154]

A. Jantsch, P. Bjurèus

MASCOT: A Specification and Cosimulation Method Integrating Data and Control Flow [p. 161]

P. Bjurèus, A. Jantsch

Delay-Insensitive Interface Specification and Synthesis [p. 169]

M. Josephs, D. Furey

Session 3B: Implementation of Telecom Systems

A 50 Mbit/s Iterative Turbo-Decoder [p. 176]

F. Viglione, G. Masera, G. Piccinini, M. Roch, M. Zamboni

Smart Antenna Receiver based on a Single Chip Solution for GSM/DCS Baseband Processing [p. 181]

U. Girola, A. Picciriello, D. Vincenzoni

Protocol Stack-based Telecom-Emulator [p. 186]

T. Murooka, T. Miyazaki

Session 3C: Logic Synthesis: Combination

Transformational Placement and Synthesis [p. 194]

W. Donath, P. Kudva, L. Stok, P. Villarrubia, L. Reddy, A. Sullivan, K. Chakraborty

Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs [p. 202]

B. Kumthekar, F. Somenzi

Constructive Library-Aware Synthesis using Symmetries [p. 208]

V. Kravets, K. Sakallah

Session 3D: BIST for Mixed-Signal Applications

A BIST Scheme for On-Chip ADC and DAC Testing [p. 216]

J. Huang, C. Ong, K. Cheng

An On Chip ADC Test Structure [p. 221]

Y. Wen, K. Lee

Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filter [p. 226]

E. Cota, L. Carro, M. Renovell, M. Lubaszewski, F. Azaïs, Y. Bertrand

Session 4A: Decision Diagram Based Methods

A BDD-based Satisfiability Infrastructure using the Unate Recursive Paradigm [p. 232]

P. Kalla, Z. Zeng, M. Ciesielski, C. Huang

Automatic Lighthouse Generation for Directed State Space Search [p. 237]

P. Yalagandula, V. Singhal, A. Aziz

Analyzing Real-Time Systems [p. 243]

J. Ruf, T. Kropf

Session 4B: Multi-Processor Architectures and Design Methods

A Generic Architecture for On-Chip Packet-Switched Interconnections [p. 250]

P. Guerrier, A. Greiner

Memory Arbitration and Cache Management in Stream-based Systems [p. 257]

F. Harmsze, A. Timmer, J. van Meerbergen

HW/SW Codesign of an Engine Management System [p. 263]

M. Baleani, A. Ferrari, A. Sangiovanni-Vincentelli, C. Turchetti

Session 4C: Logic Synthesis: Performance Optimization

Wave Steered FSMs [p. 270]

L. Macchiarulo, S. Shu, M. Marek-Sadowska

Delay Minimization and Technology Mapping of Two-Level Structures and Implementation using Clock-Delayed Domino Logic [p. 277]

J. Ciric, G. Yee, C. Sechen

Gate Sizing using a Statistical Delay Model [p. 283]

E. Jacobs, M. Berkelaar

Session 4D: TPG and Diagnosis in BIST

Optimal Hardware Pattern Generation for Functional BIST [p. 292]

S. Cataldo, S. Chiusano, P. Prinetto, H. Wunderlich

Built-in Generation of Weighted Test Sequences for Synchronous Sequential Circuits [p. 298]

I. Pomeranz, S. Reddy

Diagnostic Testing of Embedded Memories using BIST [p. 305]

T. Bergfeld, E. Rudnick, D. Niggemeyer

Session 5A: Architectural-Level Synthesis

Resolution of Dynamic Memory Allocation and Pointers for the Behavioral Synthesis from C [p. 312]

L. Séméria, K. Sato, G. De Micheli

An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement [p. 320]

S. Ganesan, R. Vemuri

Target Architecture Oriented High-Level Synthesis for Multi-FPGA based Emulation [p. 326]

O. Bringmann, C. Menn, W. Rosenstiel

Fast Cache and Bus Power Estimation for Parameterized System-On-A-Chip Design [p. 333]

T. Givargis, F. Vahid, J. Henkel

Session 5B: Analysis of Communication Circuits

Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits [p. 340]

A. Demir, P. Feldmann

A New Approach for Computation of Timing Jitter in Phase Locked Loops [p. 345]

M. Gourary, S. Rusakov, S. Ulyanov, M. Zharov, K. Gullapalli, B. Mulvaney

Compact Modeling of Nonlinear Distortion in Analog Communication Circuits [p. 350]

P. Wambacq, P. Dobrovolný, S. Donnay, M. Engels, I. Bolsens

Session 5C: Logic Synthesis: Covering and PTL Circuits

On using Satisfiability-based Pruning Techniques in Covering Algorithms [p. 356]

V. Manquinho, J. Marques-Silva

An Efficient Heuristic Approach to Solve the Unate Covering Problem [p. 364]

R. Cordone, F. Ferrandi, D. Sciuto, R. Calvo

On the Generation of Multiplexer Circuits for Pass Transistor Logic [p. 372]

C. Scholl, B. Becker

Session 5D: Delay and Functional Testing

On Applying Incremental Satisfiability to Delay Fault Testing [p. 380]

J. Kim, J. Whittemore, J. Marques-Silva, K. Sakallah

Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience [p. 385]

F. Corno, M. Sonza Reorda, G. Squillero, A. Manzone, A. Pincetti

A VHDL Error Simulator for Functional Test Generation [p. 390]

A. Fin, F. Fummi

Functional Test Generation for Full Scan Circuits [p. 396]

I. Pomeranz, S. Reddy

Session 6A: Co-Synthesis of Embedded Systems

Shared Memory Implementations of Synchronous Dataflow Specification [p. 404]

P. Murthy, S. Bhattacharyya

Constraint-Driven System Partitioning [p. 411]

M. López-Vallejo, J. Grajal, J. López

A System-Level Synthesis Algorithm with Guaranteed Solution Quality [p. 417]

U. Shenoy, P. Banerjee, A. Choudhary

Session 6B: Hot Topic -- How to Solve the Current Memory Access and Data Transfer Bottlenecks: At the Processor Architecture or at the Compiler Level?

How to Solve the Current Memory Access and Data Transfer Bottlenecks: At the Processor Architecture or at the Compiler Level? [p. 426]

F. Catthoor, N. Dutt, C. Kozyrakis

Session 6C: Wire Performance

Meeting Delay Constraints in DSM by Minimal Repeater Insertion [p. 436]

I. Liu, A. Aziz, D. Wong

A Bus Delay Reduction Technique Considering Crosstalk [p. 441]

K. Hirose, H. Yasuura

Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications [p. 446]

T. Adler, E. Barke

Static Timing Analysis Taking Crosstalk into Account [p. 451]

M. Ringe, T. Lindenkreuz, E. Barke

Session 6D: Analogue Aspects of System Testing Wire Performance

A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects [p. 458]

S. Park, T. Kim

Alternative Test Methods using IEEE 1149.4 [p. 463]

U. Kac, F. Novak, S. Macek, M. Zarnik

Test Quality and Fault Risk in Digital Filter Datapath BIST [p. 468]

L. Goodby, A. Orailoglu

A Fault Simulation Methodology for MEMS [p. 476]

A. Rosing, A. Richardson, A. Dorey

Session 7A: Abstraction Techniques

Abstraction from Counters: An Application on Real-Time Systems [p. 486]

G. Logothetis, K. Schneider

Automatic Abstraction for Worst-Case Analysis of Discrete Systems [p. 494]

F. Balarin

Iterative Abstraction-based CTL Model Checking [p. 502]

J. Jang, I. Moon, G. Hachtel

Session 7B: Panel Session -- A Design Automation Roadmap for Europe

Panel Statement [p. 510]

Session 7C: Interconnect Modelling and Analysis

Wire-Sizing for Delay Minimization and Ringing Control using Transmission Line Model [p. 512]

Y. Gao, D. Wong

Predicting Coupled Noise in RC Circuits [p. 517]

B. Sheehan

Clocktree RLC Extraction with Efficient Inductance Modeling [p. 522]

N. Chang, S. Lin, L. He, O. Nakagawa, W. Xie

All Digital Built-In Delay and Crosstalk Measurement for On-Chip Buses [p. 527]

C. Su, Y. Chen, G. Chen, M. Huang, C. Lee

Session 7D: Mixed A/D System Design

A VHDL-based Methodology for Design and Verification of Pipeline A/D Converters [p. 534]

E. Peralías, A. Acosta, A. Rueda, J. Huertas

Assessing the Cost Effectiveness of Integrated Passives [p. 539]

M. Scheffler, G. Tröster

Non-Linear Components for Mixed Circuits Analog Front-End [p. 544]

L. Carro, A. Souza Jr., M. Negreiros, G. Jahn, D. Franco

Session 8A: Scheduling and Timing Analysis for Real-Time Embedded Systems

Static Timing Analysis of Embedded Software on Advanced Processor Architectures [p. 552]

A. Hergenhan, W. Rosenstiel

Efficient Resource Arbitration in Reconfigurable Computing Environments [p. 560]

I. Ouaiss, R. Vemuri

Bus Access Optimization for Distributed Embedded Systems based on Schedulability Analysis [p. 567]

P. Pop, P. Eles, Z. Peng

Session 8B: Hot Topic -- Standards for System Level Design: Practical Reality or Solution in Search of a Question?

Standards for System-Level Design: Practical Reality or Solution in Search of a Question? [p. 576]

C. Lennard, P. Schaumont, G. de Jong, A. Haverinen, P. Hardee

Session 8D: Dependability Issues in Advanced ICs and Systems

Evaluating System Dependability in a Co-Design Framework [p. 586]

M. Lajolo, M. Rebaudengo, M. Sonza Reorda, M. Violante, L. Lavagno

Cost Reduction and Evaluation of a Temporary Faults Detecting Technique [p. 591]

L. Anghel, M. Nicolaidis

Detection of Defective Sensor Elements using sigma-delta-Modulation and a Matched Filter [p. 599]

D. Weiler, O. Machul, D. Hammerschmidt, B. Hosticka

Session 9A: High-Level Power Optimization

System Level Online Power Management Algorithms [p. 606]

D. Ramanathan, R. Gupta

Architectural Power Optimization by Bus Splitting [p. 612]

C. Hsieh, M. Pedram

A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors [p. 617]

T. Ishihara, H. Yasuura

Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths [p. 624]

M. Münch, B. Wurth, R. Mehra, J. Sproch, N. Wehn

Session 9B: Panel Session -- The Optimal Architecture Platform for System Design

Panel Statement: The Future of Flexible HW Platform Architectures [p. 634]

Session 9C: Embedded Tutorial: How Thin Is The Ice? -- Designing Closer to the Edge

Designing Closer to the Edge [p. 636]

S. Nassif

Session 9D: Defect Oriented Test

Reducing the Complexity of Defect Level Modeling using the Clustering Effect [p. 640]

J. de Sousa, V. Agrawal

Influence of Manufacturing Variations in I_DDQ Measurements: A New Test Criterion [p. 645]

J. Díez, J. López

Parametric Fault Simulation and Test Vector Generation [p. 650]

K. Saab, N. Ben-Hamida, B. Kaminska

Session 10A: Simulation and Emulation

Parallel and Distributed VHDL Simulation [p. 658]

D. Lungeanu, C. Shi

Fast Hardware-Software Coverification by Optimistic Execution of Real Processor [p. 663]

S. Yoo, J. Lee, J. Jung, K. Rha, Y. Cho, K. Choi

Retargeting of Compiled Simulators for Digital Signal Processors using a Machine Description Language [p. 669]

S. Pees, A. Hoffmann, H. Meyr

Logic Simulation using Networks of State Machines [p. 674]

P. Maurer

A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level [p. 679]

N. Fröhlich, V. Glöckel, J. Fleischmann

Session 10B: Embedded System Design Frameworks

From High-Level Specifications down to Software Implementations of Parallel Embedded Real-Time Systems [p. 686]

C. Rust, F. Stappert, P. Altenbernd, J. Tacken

An Object Oriented Design Method for Reconfigurable Computing Systems [p. 692]

M. Edwards, P. Green

System Synthesis for Multiprocessor Embedded Applications [p. 697]

L. Carro, M. Kreutz, F. Wagner, M. Oyamada

System Design based on Single Language and Single-Chip Java ASIP Microcontroller [p. 703]

S. Ito, L. Carro, R. Jacobi

Session 10D: Power and Cost Issues in Testing

Cost and Benefit Models for Logic and Memory BIST [p. 710]

J. Lu, C. Wu

Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits [p. 715]

N. Nicolici, B. Al-Hashimi

Detecting Undetectable Controller Faults using Power Analysis [p. 723]

J. Carletta, C. Papachristou, M. Nourani

Multi-Node Static Logic Implications for Redundancy Identification [p. 729]

K. Gulrajani, M. Hsiao

Poster Papers

Dynamic Power Management of Laptop Hard Disk [p. 736]

T. Simunic, L. Benini, P. Glynn, G. De Micheli

Lower Bounds on the Power Consumption in Scheduled Data Flow Graphs with Resource Constraints [p. 737]

L. Kruse, E. Schmidt, G. Jochens, A. Stammermann, W. Nebel

Area Optimization of Analog Circuits Considering Matching Constraints [p. 738]

C. Paulus, U. Kleine, R. Thewes

XFridge: A SPICE-based, Portable, User-Friendly Cell-Level Sizing Tool [p. 739]

F. Pérez-Montes, F. Medeiro, R. Domínguez-Castro, F. Fernández, A. Rodríguez-Vázquez

Evaluation of Interconnects with TDR [p. 740]

U. Pillkahn

Structural Testing on Real Boards [p. 741]

P. Bach, M. Bosch

Cycle-True Simulation of the ST10 Microcontroller [p. 742]

L. Gauthier, A. Jerraya

Cycle-based Simulation Algorithms for Digital Systems using High-Level Decision Diagrams [p. 743]

A. Morawiec, R. Ubar, J. Raik

Mixed-Signal BIST using Correlation and Reconfigurable Hardware [p. 744]

J. da Silva, J. Duarte, J. Matos

An Experimental Study of Satisfiability Search Heuristics [p. 745]

F. Aloul, J. Marques-Silva, K. Sakallah

A Memory Architecture with 4-Address Configurations for Video Signal Processing [p. 746]

S. Chang, J. Kim, L. Kim

A Hardware Platform for VLIW based Emulation of Digital Designs [p. 747]

G. Haug, U. Kebschull, W. Rosenstiel

Architecture Exploration of Parameterizable EPIC SOC Architectures [p. 748]

A. Halambi, R. Cornea, P. Grun, N. Dutt, A. Nicolau

Improving the Schedule Quality of Static-List Time-Constrained Scheduling [p. 749]

S. Govindarajan, R. Vemuri

Synthesis for Mixed CMOS/PTL Logic [p. 750]

C. Yang, M. Ciesielski

TOP: An Algorithm for Three-Level Optimization of PLDs [p. 751]

E. Dubrova, P. Ellervee, D. Miller, J. Muzio

Testing Arithmetic Coprocessor in System Environment [p. 752]

J. Sosnowski, T. Bech

A Flexibile Specification Framework for Hardware-Software Codesign [p. 753]

J. Moya, S. Domínguez, F. Moya, J. López

An Integrated Design Environment for Early Stage Conceptual Design [p. 754]

J. Zuo, S. Director

A Web-based System for Assessing and Searching for Designs [p. 755]

H. Kahn, A. Carpenter, N. Whitaker

A Versatile Built-In Self Test Scheme for Delay Fault Testing [p. 756]

Y. Tsiatouhas, T. Haniotakis, D. Nikolos, A. Arapoyanni

Effective Low Power BIST for Datapaths [p. 757]

D. Gizopoulos, N. Kranitis, A. Paschalis, M. Psarakis, Y. Zorian

Exploiting Hierarchy for Multiple Error Correction in Combinational Circuits [p. 758]

D. Hoffmann, T. Kropf

Automatic Equivalence Check of Circuit Descriptions at Clocked Algorithmic and Register Transfer Level [p. 759]

J. Schönherr, B. Straube

A Single Phase Latch for High Speed GaAs Domino Circuits [p. 760]

S. Nooshabadi, J. Montiel-Nelson, A. Núñez

An Incremental Specification Flow for Real Time Embedded Systems [p. 761]

A. Niemegeers, G. de Jong

Improving the Error Detection Ability of Concurrent Checkers by Observation Point Insertion in the Circuit under Check [p. 762]

V. Vardanian, L. Mirzoyan

On-Line Testing and Diagnosis of Bus Lines with Respect to Intermediate Voltage Values [p. 763]

C. Metra, M. Favalli, B. Riccò

Efficient Method of Failure Detection in Iterative Array Multiplier [p. 764]

A. Drozd

Incorporation of Hard-Fault-Coverage in Model-based Testing of Mixed-Signal ICs [p. 765]

C. Wegener, M. Kennedy