Technical Program

Session Title	Opening Session: Plenary, Awards Ceremony & Keynote Addresses
Session Code / Room	1.1/Amphithéâtre Dauphine
Date / Time	Tuesday 10 March 2020 / 08:30 - 10:30
Chair	Giorgio Di Natale, DATE 2020 General Chair, FR
Co-Chair	Cristiana Bolchini, DATE 2020 Programme Chair, IT

1.1.1 08:15 - 08:25	Welcome Addresses Giorgio Di Natale and Cristiana Bolchini
1.1.2 08:25 - 09:15	Presentation of Awards
1.1.3 09:15 - 10:30	Plenary Keynote: The Industrial IoT Microelectronics Revolution Philippe Magarshack
1.1.4 09:15 - 10:30	Plenary Keynote: Open Parallel Ultra-Low Power Platforms for Extreme Edge AI Luca Benini

Session Title	Executive Session: Memories for Emerging Applications
Session Code / Room	2.1 / Amphithéâtre Jean Prouve
Date / Time	Tuesday 10 March 2020 / 11:30 - 13:00
Chair	Pierre-Emmanuel Gaillardon, University of Utah, US
Co-Chair	Kvatinsky Shahar, Technion, IL

2.1.1 11:30 - 12:00	Resistive Ram and Its Dense 3D Integration for the N3XT 1,000X Subhasish Mitra
2.1.2 12:00 - 12:30	Emerging Memories for Von Neumann and for Neuromorphic Computing Jamil Kawa
2.1.3 12:30 - 13:00	Reram Technology for Next Generation Ai and Cost-Effective Embedded Memory Amir Regev

Session Title	Hardware-assisted Secure Systems
Session Code / Room	2.2 / Chamrousse
Date / Time	Tuesday 10 March 2020 / 11:30 - 13:00
Chair	Prabhat Mishra, University of Florida, US
Co-Chair	Kavun Elif Bilge, University of Sheffield, GB

2.2.1 11:30 - 12:00	Backtracking Search for Optimal Parameters of a PLL-based True Random Number Generator Brice Colombier, Nathalie Bochard, Florent Bernard and Lilian Bossuet
2.2.2 12:00 - 12:15	Long-term Continuous Assessment of SRAM PUF and Source of Random Numbers Rui Wang, Georgios Selimis, Roel Maes and Sven Goossens
2.2.3 12:15 - 12:30	Rescuing Logic Encryption in Post-SAT Era by Locking & Obfuscation Amin Rezaei, Yuanqi Shen and Hai Zhou
2.2.4 12:30 - 12:45	Selective Concolic Testing for Hardware Trojan Detection in Behavioral SystemC Designs Bin Lin, Jinchao Chen and Fei Xie
2.2.5 12:45 - 13:00	Test Pattern Superposition to Detect Hardware Trojans Chris Nigh and Alex Orailoglu

Session Title	Fueling the future of computing: 3D, TFT, or disruptive memories?
Session Code / Room	2.3 / Autrans
Date / Time	Tuesday 10 March 2020 / 11:30 - 13:00
Chair	Yvain Thonnart, CEA-Leti, FR
Co-Chair	Marco Vacca, Politecnico di Torino, IT

2.3.1 11:30 - 12:00	Ternary Compute-Enabled Memory using Ferroelectric Transistors for Accelerating Deep Neural Networks Sandeep Krishna Thirumala, Shubham Jain, Sumeet Kumar Gupta and Anand Raghunathan
2.3.2 12:00 - 12:30	Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs Lennart Bamberg, Alberto García-Ortiz, Lingjun Zhu, Sai Pentapati, Da Eun Shim and Sung Kyu Lim
2.3.3 12:30 - 12:45	Quantifying the Benefits of Monolithic 3D Computing Systems Enabled by TFT and RRAM Abdallah M. Felfel, Kamalika Datta, Arko Dutt, Hasita Veluri, Ahmed Zaky, Aaron Voon-Yew Thean and Mohamed M. Sabry Aly
2.3.4 12:45 - 13:00	Organic-Flow: An Open-Source Organic Standard Cell Library and Process Development Kit Ting-Jung Chang, Zhuozhi Yao, Barry P. Rand and David Wentzlaff

Session Title	Challenges in Analog Design Automation & Security
Session Code / Room	2.4 / Stendhal
Date / Time	Tuesday 10 March 2020 / 11:30 - 13:00
Chair	Manuel Barragan, TIMA, FR
Co-Chair	Haralampos Stratigopoulos, LIP6, FR

2.4.1 11:30 - 12:00	GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani and Sachin S. Sapatnekar
2.4.2 12:00 - 12:30	Securing Programmable Analog ICs Against Piracy Mohamed Elshamy, Alhassan Sayed, Marie-Minerve Louërat, Amine Rhouni, Hassan Aboushady and Haralampos-G. Stratigopoulos
2.4.3 12:30 - 13:00	An Efficient Bayesian Optimization Approach for Analog Circuit Synthesis via Sparse Gaussian Process Modeling Biao He, Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou and Xuan Zeng

Session Title	Pruning Techniques for Embedded Neural Networks
Session Code / Room	2.5 / Bayard
Date / Time	Tuesday 10 March 2020 / 11:30 - 13:00
Chair	Marian Verhelst, KU Leuven, BE
Co-Chair	Dirk Ziegenbein, Robert Bosch GmbH, DE

2.5.1 11:30 - 12:00	Deeper Weight Pruning without Accuracy Loss in Deep Neural Networks Byungmin Ahn and Taewhan Kim
2.5.2 12:00 - 12:30	Flexible Group-Level Pruning of Deep Neural Networks for On-Device Machine Learning Kwangbae Lee, Hoseung Kim, Hayun Lee and Dongkun Shin
2.5.3 12:30 - 13:00	Sparsity-Aware Caches to Accelerate Deep Neural Networks Vinod Ganesan, Sanchari Sen, Pratyush Kumar, Neel Gala, Kamakoti Veezhinathan and Anand Raghunathan

Session Title	Improving reliability and fault tolerance of advanced memories
Session Code / Room	2.6 / Lesdiguières
Date / Time	Tuesday 10 March 2020 / 11:30 - 13:00
Chair	Mounir Benabdenbi, TIMA Laboratory, FR
Co-Chair	Said Hamdioui, TU Delft, NL

2.6.1 11:30 - 12:00	On Improving Fault Tolerance of Memristor Crossbar Based Neural Network Designs by Target Sparsifying Song Jin, Songwei Pei and Yu Wang
2.6.2 12:00 - 12:30	An Efficient SRAM yield Analysis Using Scaled-Sigma Adaptive Importance Sampling Liang Pang, Mengyun Yao and Yifan Chai
2.6.3 12:30 - 12:45	Fast and Accurate High-Sigma Failure Rate Estimation through Extended Bayesian Optimized Importance Sampling Michael Hefenbrock, Dennis D. Weller, Michael Beigl and Mehdi B. Tahoori
2.6.4 12:45 - 13:00	Valid Window: A New Metric to Measure the Reliability of NAND Flash Memory Min Ye, Qiao Li, Jianqiang Nie, Tei-Wei Kuo and Chun Jason Xue

Session Title	Optimizing emerging applications for power-efficient computing
Session Code / Room	2.7 / Berlioz
Date / Time	Tuesday 10 March 2020 / 11:30 - 13:00
Chair	Jungwook Choi, Hanyang University, KR
Co-Chair	Shafique Muhammad, TU Wien, AT

2.7.1 11:30 - 12:00	GenieHD: Efficient DNA Pattern Matching Accelerator Using Hyperdimensional Computing Yeseong Kim, Mohsen Imani, Niema Moshiri and Tajana Rosing
2.7.2 12:00 - 12:30	REPUTE: An OpenCL based Read Mapping Tool for Embedded Genomics Sidharth Maheshwari, Rishad Shafik, Ian Wilson, Alex Yakovlev and Amit Acharyya
2.7.3 12:30 -13:00	A Fast and Energy Efficient Computing-in-Memory Architecture for Few-Shot Learning Applications Dayane Reis, Ann Franchesca Laguna, Michael Niemier and Xiaobo Sharon Hu

Session Title	LUNCHTIME KEYNOTE SESSION: Neuromorphic Computing: Past, Present, and Future
Session Code / Room	3.0 / Amphithéâtre Jean Prouve
Date / Time	Tuesday 10 March 2020 / 13:50 - 14:20
Chair	Marco Casale-Rossi, Synopsys, IT
Co-Chair	Giovanni De Micheli, EPFL, CH

3.0.1
13:50 - 14:30

Neuromorphic Computing: Past, Present, and Future
Catherine Schuman

Session Title	Special Session: Architectures for Emerging Technologies
Session Code / Room	3.1 / Amphithéâtre Jean Prouve
Date / Time	Tuesday 10 March 2020 / 14:30 - 16:00
Chair	Pierre-Emmanuel Gaillardon, University of Utah, US
Co-Chair	Michael Niemier, University of Notre Dame, US

3.1.1 14:30 - 14:45	CRYO-CMOS Interfaces for A Scalable Quantum Computer Edoardo Charbon, Andrei Vladimirescu, Fabio Sebastiano and Masoud Babaie
3.1.2 14:45 - 15:00	The N3xt 1,000X for The Coming Superstorm Of Abundant Data: Carbon Nanotube Fets, Resistive Ram, Monolithic 3d Gage Hills and Mohamed M. Sabry
3.1.3 15:00 - 15:15	Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic Eleonora Testa, Samantha Lubaba Noor, Odysseas Zografos, Mathias Soeken, Francky Catthoor, Azad Naeemi and Giovanni De Micheli
3.1.4 15:15 - 15:30	Quantum Computer Architecture: Towards Full-Stack Quantum Accelerators K. Bertels, A. Sarkar, T. Hubregtsen, M. Serrao, A.A. Mouedenne, A. Yadav, A. Krol and I. Ashraf
3.1.5 15:30 - 15:45	Utilizing Buried Power Rails And Backside PDN To Further CMOS Scaling Below 5nm Nodes Odysseas Zografos, Sudhir Patli, Satadru Sarkar, Bilal Chehab, Doyoung Jang, Rogier Baert, Peter Debacker, Myung-Hee Na and Julien Ryckaert
3.1.6 15:45 - 16:00	A RRAM-Based FPGA for Energy-Efficient Edge Computing Xifan Tang, Ganesh Gore, Patsy Cadareanu, edouard giacomin and Pierre-Emmanuel Gaillardon

Session Title	Accelerating Design Space Exploration
Session Code / Room	3.2 / Lesdiguières
Date / Time	Tuesday 10 March 2020 / 14:30 - 16:00
Chair	Christian Pilato, Politecnico di Milano, IT
Co-Chair	Luca Carloni, Columbia University, US

3.2.1 14:30 - 15:00	Efficient and Robust High-Level Synthesis Design Space Exploration through offline Micro-kernels Pre-characterization Zi Wang, Jianqi Chen and Benjamin Carrion Schafer
3.2.2 15:00 - 15:30	Prospector: Synthesizing Efficient Accelerators via Statistical Learning Atefeh Mehrabi, Aninda Manocha, Benjamin C. Lee and Daniel J. Sorin
3.2.3 15:30 - 16:00	Tango: An Optimizing Compiler for Just-In-Time RTL Simulation Blaise-Pascal Tine, Sudhakar Yalamanchili and Hyesoon Kim

Session Title	EU/ESA projects on Heterogeneous Computing
Session Code / Room	3.3 / Autrans
Date / Time	Tuesday 10 March 2020 / 14:30 - 16:00
Chair	Carles Hernandez, UPV, ES
Co-Chair	Francisco J. Cazorla, BSC, ES

3.3.1 14:30 - 15:00	ESA Athena WFI Onboard Electronics - Distributed Control and Data Processing Markus Plattner, Sabine Ott, Sebastian Albrecht, Jintin Tran, Christopher Mandla, Jan-Christoph Tenzer, Thomas Schanz, Samuel Pliego, Denis Tcherniak, Manfred Steller, Harald Jeszensky, Roland Ottensamer, Konrad Skup, Chris Thomas and Julian Thornhill
3.3.2 15:00 - 15:30	LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing B. Salami, K. Parasyris, A. Cristal, O. Unsal, X. Martorell, P. Carpenter, R. De La Cruz, L. Bautista, D. Jimenez, C. Alvarez, S. Nabavi, S. Madonar, M. Pericàs, P. Trancoso, M. Abduljabbar, J. Chen, P. N. Soomro, M Manivannan (Chalmers), M. Berge, S. Krupop (CHR), F. Klawonn, Al Mekhlafi, S. May (HZI), T. Becker, G. Gaydadjiev (Maxeler), H. Salomonsson, D. Dubhashi (MIS), O. Port, Y. Etsion (Technion), Le Quoc Do, Christof Fetzer (TUD), M. Kaiser, N. Kucza, J. Hagemeyer, R. Griessl, L. Tigges, K. Mika, A. Hüffmeier (UBI), M. Pasin, V. Schiavoni, I. Rocha, C. Göttel and P. Felber (UniNE)
3.3.3 15:30 - 16:00	Efficient Compilation and Execution of JVM-Based Data Processing Frameworks on Heterogeneous Co- Processors Christos Kotselidis, Sotiris Diamantopoulos, Orestis Akrivopoulos, Viktor Rosenfeld, Katerina Doka, Hazeef Mohammed, Georgios Mylonas, Vassilis Spitadakis and Will Morgan

Session Title	Accelerating Neural Networks and Vision Workloads
Session Code / Room	3.4 / Stendhal
Date / Time	Tuesday 10 March 2020 / 14:30 - 16:00
Chair	Leonidas Kosmidis, BSC, ES
Co-Chair	Georgios Keramidas, Aristotle University of Thessaloniki/Think Silicon S.A., GR

3.4.1 14:30 - 15:00	PSB-RNN: A Processing-in-Memory Systolic Array Architecture using Block Circulant Matrices for Recurrent Neural Networks Nagadastagiri Challapalle, Sahithi Rampalli, Makesh Chandran, Gurpreet Kalsi, Sreenivas Subramoney, John Sampson and Vijaykrishnan Narayanan
3.4.2 15:00 - 15:30	XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Davide Rossi and Luca Benini
3.4.3 15:30 - 15:45	SNA: A Siamese Network Accelerator to Exploit the Model-Level Parallelism of Hybrid Network Structure Xingbin Wang, Boyan Zhao, Rui Hou and Dan Meng
3.4.4 15:45 - 16:00	HcveAcc: A High-Performance and Energy-Efficient Accelerator for Tracking Task in VSLAM System Renwei Li, Junning Wu, Meng Liu, Zuding Chen, Shengang Zhou and Shanggong Feng

Session Title	Parallel real-time systems
Session Code / Room	3.5 / Bayard
Date / Time	Tuesday 10 March 2020 / 14:30 - 16:00
Chair	Liliana Cucu-Grosjean, Inria, FR
Co-Chair	Antoine Bertout, ENSMA, FR

3.5.1 14:30 - 15:00	On the Volume Calculation for Conditional DAG Tasks: Hardness and Algorithms Jinghao Sun, Yaoyao Chi, Tianfei Xu, Lei Cao, Nan Guan, Zhishan Guo and Wang Yi
3.5.2 15:00 - 15:30	WCET-aware Code Generation and Communication Optimization for Parallelizing Compilers Simon Reder and Jürgen Becker
3.5.3 15:30 - 15:45	Template Schedule Construction For Global Real-Time Scheduling on Unrelated Multiprocessor Platforms Antoine Bertout, Joël Goossens, Emmanuel Grolleau and Xavier Poczekajlo
3.5.4 15:45 - 16:00	Application-Aware Scheduling of Networked Applications over the Low-Power Wireless Bus Kacper Wardega and Wenchao Li

Session Title	NoC in the age of neural network and approximate computing
Session Code / Room	3.6 / Lesdiguières
Date / Time	Tuesday 10 March 2020 / 14:30 - 16:00
Chair	Romain Lemaire, CEA-Leti, FR

3.6.1 14:30 - 15:00	GRAMARCH: A GPU-ReRAM based Heterogeneous Architecture for Neural Image Segmentation Biresh Kumar Joardar, Nitthilan Kannappan Jayakodi, Janardhan Rao Doppa, Hai Li, Partha Pratim Pande and Krishnendu Chakrabarty
3.6.2 15:00 - 15:30	An Approximate Multiplane Network-on-Chip Ling Wang, Yadong Wang and Xiaohang Wang
3.6.3 15:30 - 16:00	Shenjing: A Low Power Reconfigurable Neuromorphic Accelerator with Partial-Sum and Spike Networks-on-Chip Bo Wang, Jun Zhou, Weng-Fai Wong and Li-Shiuan Peh

Session Title	Augmented and Assisted Living: A reality
Session Code / Room	3.7 / Berlioz
Date / Time	Tuesday 10 March 2020 / 14:30 - 16:00
Chair	Graziano Pravadelli, Università di Verona, IT
Co-Chair	Vassilis Pavlidis, Aristotle University of Thessaloniki, GR

3.7.1 14:30 - 15:00	Compressing Subject-specific Brain–Computer Interface Models into One Model by Superposition in Hyperdimensional Space Michael Hersche, Philipp Rupp, Luca Benini and Abbas Rahimi
3.7.2 15:00 - 15:30	A novel FPGA-based system for Tumor Growth Prediction Konstantinos Malavazos, Maria Papadogiorgaki, Pavlos Malakonakis and Ioannis Papaefstathiou
3.7.3 15:30 - 15:45	An Event-Based System for Low-Power ECG QRS Complex Detection Silvio Zanoli, Tomas Teijeiro, Fabio Montagna and David Atienza
3.7.4 15:45 - 16:00	Semi-Autonomous Personal Care Robots Interface driven by EEG Signals Digitization Giovanni Mezzina and Daniela De Venuto

Session Title	Interactive Presentations
Session Code / Room	IP1 / Poster Area
Date / Time	Tuesday 10 March 2020 / 16:00 - 16:30

IP1-1	DynUnlock: Unlocking Scan Chains Obfuscated using Dynamic Keys Nimisha Limaye and Ozgur Sinanoglu
IP1-2	CMOS Implementation of Switching Lattices Ismail Cevick, Levent Aksoy and Mustafa Altun
IP1-3	A Timing Uncertainty-Aware Clock Tree Topology Generation Algorithm for Single Flux Quantum Circuits Soheil Nazar Shahsavani, Bo Zhang and Massoud Pedram
IP1-4	Symmetry-based A/M-S BIST (SymBIST): Demonstration on a SAR ADC IP Antonios Pavlidis, Marie-Minerve Louërat, Eric Faehn, Anand Kumar and Haralampos-G. Stratigopoulos
IP1-5	Range-Controlled Floating-Gate Transistors: A Unified Solution for Unlocking and Calibrating Analog ICs Sai Govinda Rao Nimmalapudi, Georgios Volanis, Yichuan Lu, Angelos Antonopoulos, Andrew Marshall and Yiorgos Makris
IP1-6	Testing Through Silicon Vias in Power Distribution Network of 3D-IC with Manufacturing Variability Cancellation Koutaro Hachiya and Atsushi Kurokawa
IP1-7	TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU Filip Vaverka, Vojtech Mrazek, Zdenek Vasicek and Lukas Sekanina
IP1-8	Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities Valentin Gherman, Samuel Evain and Bastien Giraud
IP1-9	BeLDPC: Bit Errors Aware Adaptive Rate LDPC Codes for 3D TLC NAND Flash Memory Meng Zhang, Fei Wu, Qin Yu, Weihua Liu, Lanlan Cui, Yahui Zhao and Changsheng Xie
IP1-10	Poisoning the (Data) Well in ML-Based CAD: A Case Study of Hiding Lithographic Hotspots Kang Liu, Benjamin Tan, Ramesh Karri and Siddharth Garg
IP1-11	SOLOMON: An Automated Framework for Detecting Fault Attack Vulnerabilities in Hardware Milind Srivastava, Patanjali SLPSK, Indrani Roy, Chester Rebeiro, Aritra Hazra and Swarup Bhunia
IP1-12	Formal Synthesis of Monitoring and Detection Systems for Secure CPS Implementations Ipsita Koley, Saurav Kumar Ghosh, Soumyajit Dey, Debdeep Mukhopadhyay, Amogh Kashyap K N, Sachin Kumar Singh, Lavanya Lokesh, Jithin Nalu Purakkal and Nishant Sinha
IP1-13	ASCELLA: Accelerating Sparse Computation by Enabling Stream Accesses to Memory Bahar Asgari, Ramyad Hadidi and Hyesoon Kim
IP1-14	Acceleration of Probabilistic Reasoning Through Custom Processor Architecture Nimish Shah, Laura I. Galindez Olascoaga, Wannes Meert and Marian Verhelst
IP1-15	A Performance Analysis Framework for Real-Time Systems Sharing Multiple Resources Shayan Tabatabaei Nikkhah, Marc Geilen, Dip Goswami and Kees Goossens
IP1-16	Scaling Up the Memory Interference Analysis for Hard Real-Time Many-Core Systems Maximilien Dupont de Dinechin, Matheus Schuh, Matthieu Moy and Claire Maiza
IP1-17	Lightweight Anonymous Routing in NoC based SoCs Subodha Charles, Megan Logan and Prabhat Mishra
IP1-18	A Non-invasive Wearable Bioimpedance System to Wirelessly Monitor Bladder Filling Markus Reichmuth, Simone Schürle and Michele Magno
IP1-19	InfiniWolf: Energy Efficient Smart Bracelet for Edge Computing with Dual Source Energy Harvesting Michele Magno, Xiaying Wang, Manuel Eggimann, Lukas Cavigelli and Luca Benini

Session Title	Hardware-enabled security
Session Code / Room	4.1 / Amphithéâtre Jean Prouve
Date / Time	Tuesday 10 March 2020 / 17:00 - 18:30
Chair	Marchand Cedric, Ecole Centrale de Lyon, FR
Co-Chair	Hai Zhou, Northwestern University, US

4.1.1 17:00 - 17:30	A Flexible and Scalable NTT Hardware: Applications from Homomorphically Encrypted Deep Learning to Post-Quantum Cryptography Ahmet Can Mert, Emre Karabulut, Erdinç Öztürk, Erkay Savas, Michela Becchi and Aydin Aysu
4.1.2 17:30 - 18:00	Reliable and Lightweight PUF-based Key Generation using Various Index Voting Architecture Jeong-Hyeon Kim, Ho-Jun Jo, Kyung-Kuk Jo, Sung-Hee Cho, Jae-Yong Chung and Joon-Sung Yang
4.1.3 18:00 - 18:30	Estimating the Circuit De-obfuscation Runtime based on Graph Deep Learning Zhiqian Chen, Gaurav Kolhe, Setareh Rafatirad, Chang-Tien Lu, Sai Manoj P D, Houman Homayoun and Liang Zhao

Session Title	Timing in System-Level Modeling and Simulation
Session Code / Room	4.2 / Chamrousse
Date / Time	Tuesday 10 March 2020 / 17:00 - 18:30
Chair	Jorn Janneck, Lund University, SE
Co-Chair	Gianluca Palermo, Politecnico di Milano, IT

4.2.1 17:00 - 17:30	Fast and Accurate DRAM Simulation: Can we Further Accelerate it? Johannes Feldmann, Kira Kraft, Lukas Steiner, Norbert Wehn and Matthias Jung
4.2.2 17:30 - 18:00	Accurate and Efficient Continuous Time and Discrete Events Simulation in SystemC Breytner Fernández-Mesa, Liliana Andrade and Frédéric Pétrot
4.2.3 18:00 - 18:30	Modeling and Verifying Uncertainty-Aware Timing Behaviors using Parametric Logical Time Constraint Fei Gao, Frederic Mallet, Min Zhang and Mingsong Chen

Session Title	EU Projects on Nanoelectronics with CMOS and alternative technologies
Session Code / Room	4.3 / Autrans
Date / Time	Tuesday 10 March 2020 / 17:00 - 18:30
Chair	Dimitris Gizopoulos, UoA, GR
Co-Chair	George Karakonstantis, Queen's University Belfast, GR

4.3.1 17:00 - 17:30	Nano-Crossbar based Computing: Lessons Learned and Future Directions Mustafa Altun, Ismail Cevik, Ahmet Erten, Osman Eksik, Mircea Stan and Csaba Andras Moritz
4.3.2 17:30 - 18:00	RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems M. Jenihhin, S. Hamdioui, M. Sonza Reorda, M. Krstic, P. Langendörfer, C. Sauer, A. Klotz, M. Huebner, J. Nolte, H. T.Vierhaus, G. Selimis, D. Alexandrescu, M. Taouil, G. J. Schrijen, J. Raik, L. Sterpone, G. Squillero and Z. Dyka
4.3.3 18:00 - 18:30	A Universal Spintronic Technology based on Multifunctional Standardized Stack M. Tahoori, S.M. Nair, R. Bishnoi, L. Torres, S. Senni, G. Patrigeon, P. Benoit, G. Di Pendina and G. Prenat

Session Title	Some run it hot, others do not
Session Code / Room	4.4 / Stendhal
Date / Time	Tuesday 10 March 2020 / 17:00 - 18:30
Chair	Pascal Vivet, CEA-Leti, FR
Co-Chair	Daniele J. Pagliari, Politecnico di Torino, IT

4.4.1 17:00 - 17:30	A Learning-Based Thermal Simulation Framework for Emerging Two-Phase Cooling Technologies Zihao Yuan, Geoffrey Vaartstra, Prachi Shukla, Zhengmao Lu, Evelyn Wang, Sherief Reda and Ayse K. Coskun
4.4.2 17:30 - 18:00	Lightweight Thermal Monitoring in Optical Networks-on-Chip via Router Reuse Mengquan Li, Jun Zhou and Weichen Liu
4.4.3 18:00 - 18:15	A Spectral Approach to Scalable Vectorless Thermal Integrity Verification Zhiqiang Zhao and Zhuo Feng
4.4.4 18:15 - 18:30	Dynamic Thermal Management with Proactive Fan Speed Control Through Reinforcement Learning Arman Iranfar, Federico Terraneo, Gabor Csordas, Marina Zapater, William Fornaciari and David Atienza

Session Title	Adaptation and optimization for real-time systems
Session Code / Room	4.5 / Bayard
Date / Time	Tuesday 10 March 2020 / 17:00 - 18:30
Chair	Wanli Chang, University of york, GB
Co-Chair	Emmanuel Grolleau, ENSMA, FR

4.5.1 17:00 - 17:30	Reliable and Energy-Aware Fixed-Priority (m,k)-Deadlines Enforcement with Standby-Sparing Linwei Niu and Dakai Zhu
4.5.2 17:30 - 18:00	Period Adaptation for Continuous Security Monitoring in Multicore Real-Time Systems Monowar Hasan, Sibin Mohan, Rodolfo Pellizzoni and Rakesh B. Bobba
4.5.3 18:00 - 18:15	Efficient Latency Bound Analysis for Data Chains of Real-Time Tasks in Multiprocessor Systems Jiankang Ren, Xin He, Junlong Zhou, Hongwei Ge, Guowei Wu and Guozhen Tan
4.5.4 18:15 - 18:30	Cache Persistence-Aware Memory Bus Contention Analysis for Multicore Systems Syed Aftab Rashid, Geoffrey Nelissen and Eduardo Tovar

Session Title	Artificial Intelligence and Secure Systems
Session Code / Room	4.6 / Lesdiguières
Date / Time	Tuesday 10 March 2020 / 17:00 - 18:30
Chair	Annelie Heuser, Univ Rennes, Inria, CNRS, France, FR
Co-Chair	Ilia Polian, University of Stuttgart, DE

4.6.1 17:00 - 17:30	A Particle Swarm Optimization Guided Approximate Key Search Attack on Logic Locking in The Absence of Scan Access Rajit Karmakar and Santanu Chattopadhyay
4.6.2 17:30 - 18:00	Effect of Aging on PUF Modeling Attacks based on Power Side-Channel Observations Trevor Kroeger, Wei Cheng, Sylvain Guilley, Jean-Luc Danger and Naghmeh Karimi
4.6.3 18:00 - 18:30	OFFLINE MODEL GUARD: Secure and Private ML on Mobile Devices Sebastian P. Bayerl, Tommaso Frassetto, Patrick Jauernig, Korbinian Riedhammer, Ahmad-Reza Sadeghi, Thomas Schneider, Emmanuel Stapf and Christian Weinert

Session Title	Future computing fabrics: security and design integration
Session Code / Room	4.7 / Berlioz
Date / Time	Tuesday 10 March 2020 / 17:00 - 18:30
Chair	Elena Gnani, Università di Bologna, IT
Co-Chair	Gage Hills, Massachusetts Institute of Technology, US

4.7.1 17:00 - 17:30	Security Enhancement for RRAM Computing System through Obfuscating Crossbar Row Connections Minhui Zou, Zhenhua Zhu, Yi Cai, Junlong Zhou, Chengliang Wang and Yu Wang
4.7.2 17:30 - 18:00	Modeling a Floating-Gate Memristive Device for Computer Aided Design of Neuromorphic Computing L. Danial, V. Gupta, E. Pikhay, Y. Roizin and S. Kvatinsky
4.7.3 18:00 - 18:15	Ground Plane Partitioning for Current Recycling of Superconducting Circuits Naveen Kumar Katam, Bo Zhang and Massoud Pedram
4.7.4 18:15 - 18:30	Silicon Photonic Microring Resonators: Design Optimization Under Fabrication Non-Uniformity Asif Mirza, Febin Sunny, Sudeep Pasricha and Mahdi Nikdast

Session Title	Special Day on "Embedded AI": Tutorial Overviews
Session Code / Room	5.1 / Amphithéâtre Jean Prouve
Date / Time	Wednesday 11 March 2020 / 08:30 - 10:00
Chair	Dmitri Strukov, University of California, Santa Barbara, US
Co-Chair	Bernabe Linares-Barranco, CSIC, ES

5.1.1 8:30 - 9:15	Neural Networks Circuits Based On Resistive Memories Carlo Reita
5.1.2 9:15 - 10:00	Exploiting Activation Sparsity In Dram-Based Scalable CNN and RNN Accelerators Tobi Delbrück

Session Title	Machine Learning Approaches to Analog Design
Session Code / Room	5.2 / Chamrousse
Date / Time	Wednesday 11 March 2020 / 08:30 - 10:00
Chair	Marie-Minerve Louerat, Sorbonne University Lip6, FR
Co-Chair	Sebastien Cliquennois, STMicroelectronics, FR

5.2.1 8:30 - 9:00	AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs Keertana Settaluri, Ameer Haj-Ali, Qijing Huang, Kourosh Hakhamaneshi and Borivoje Nikolic
5.2.2 9:00 - 9:30	Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning Mingjie Liu, Keren Zhu, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun and David Z. Pan
5.2.3 9:30 - 10:00	Design of Multi-Output Switched-Capacitor Voltage Regulator via Machine Learning Zhiyuan Zhou, Syrine Belakaria, Aryan Deshwal, Wookpyo Hong, Janardhan Rao Doppa, Partha Pratim Pande and Deukhyoun Heo

Session Title	Special Session: Secure Composition of Hardware Systems
Session Code / Room	5.3 / Autrans
Date / Time	Wednesday 11 March 2020 / 08:30 - 10:00
Chair	Ilia Polian, Stuttgart University, DE
Co-Chair	Francesco Regazzoni, ALARI, CH

5.3.1 8:30 - 8:55	Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA Johann Knechtel, Elif Bilge Kavun, Francesco Regazzoni, Annelie Heuser, Anupam Chattopadhyay, Debdeep Mukhopadhyay, Soumyajit Dey, Yunsi Fei, Yaacov Belenky, Itamar Levi, Tim Güneysu, Patrick Schaumont and Ilia Polian
5.3.2 8:55 - 9:15	Attacker Modeling On Composed Systems Pierre Schnarz
5.3.3 9:15 - 9:35	Pitfalls in Machine Learning-based Adversary Modeling for Hardware Systems Fatemeh Ganji, Sarah Amir, Shahin Tajik, Domenic Forte and Jean-Pierre Seifert
5.3.4 9:35 - 10:00	Using Universal Composition to Design and Analyze Secure Complex Hardware Systems Ran Canetti, Marten van Dijk, Hoda Maleki, Ulrich Rührmair and Patrick Schaumont

Session Title	New Frontiers in Formal Verification for Hardware
Session Code / Room	5.4 / Stendhal
Date / Time	Wednesday 11 March 2020 / 08:30 - 10:00
Chair	Alessandro Cimatti, Fondazione Bruno Kessler, IT
Co-Chair	Heinz Riener, EPFL, CH

5.4.1 8:30 - 9:00	Gap-free Processor Verification by S²QED and Property Generation Keerthikumara Devarajegowda, Mohammad Rahmani Fadiheh, Eshan Singh Clark Barrett, Subhasish Mitra, Wolfgang Ecker, Dominik Stoffel and Wolfgang Kunz
5.4.2 9:00 - 9:30	SPEAR: Hardware-based Implicit Rewriting for Square-root Circuit Verification Atif Yasin, Tiankai Su, Sébastien Pillement and Maciej Ciesielski
5.4.3 9:30 - 9:45	A Reinforcement Learning Approach to Directed Test Generation for Shared Memory Verification Nícolas Pfeifer, Bruno V. Zimpel, Gabriel A. G. Andrade and Luiz C. V. dos Santos
5.4.4 9:45 - 10:00	Towards Formal Verification of Optimized and Industrial Multipliers Alireza Mahzoon, Daniel Große,Christoph Scholl and Rolf Drechsler

Session Title	Model-Based Analysis and Security
Session Code / Room	5.5 / Bayard
Date / Time	Wednesday 11 March 2020 / 08:30 - 10:00
Chair	Ylies Falcone, University Grenoble Alpes and Inria, FR
Co-Chair	Todd Austin, University of Michigan, US

5.5.1 8:30 - 9:00	Is Register Transfer Level Locking Secure? Chandan Karfa, Ramanuj Chouksey, Christian Pilato, Siddharth Garg and Ramesh Karri
5.5.2 9:00 - 9:30	Design Space Exploration for Model-based Communication Systems Valentina Richthammer, Marcel Rieß, Julian Bestler, Frank Slomka and Michael Glaß
5.5.3 9:30 - 10:00	Statistical Time-based Intrusion Detection in Embedded Systems Nadir A. Carreón, Allison Gilbreath and Roman Lysecky

Session Title	Logic synthesis towards fast, compact, and secure designs
Session Code / Room	5.6 / Lesdiguières
Date / Time	Wednesday 11 March 2020 / 08:30 - 10:00
Chair	Valeria Bertacco, University of Michigan, US
Co-Chair	Lukas Sekanina, Brno University of Technology, CZ

5.6.1 8:30 - 9:00	A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks Eleonora Testa, Mathias Soeken, Heinz Riener, Luca Amaru and Giovanni De Micheli
5.6.2 9:00 - 9:30	Saving Power by Converting Flip-Flop to 3-Phase Latch-Based Designs Huimei Cheng, Xi Li, Yichen Gu and Peter A. Beerel
5.6.3 9:30 - 9:45	Computing the Full Quotient in Bi-Decomposition by Approximation Anna Bernasconi, Valentina Ciriani, Jordi Cortadella and Tiziano Villa
5.6.4 9:45 - 10:00	MiniDelay: Multi-Strategy Timing-Aware Layer Assignment for Advanced Technology Nodes Xinghai Zhang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu, Wenzhong Guo and Ting-Chi Wang

Session Title	Stochastic Computing
Session Code / Room	5.7 / Berlioz
Date / Time	Wednesday 11 March 2020 / 08:30 - 10:00
Chair	Robert Wille, Johannes Kepler University Linz, AT
Co-Chair	Shigeru Yamashita, Ritsumeikan, JP

5.7.1 8:30 - 9:00	The Hypergeometric Distribution as a More Accurate Model for Stochastic Computing Timothy J. Baker and John P. Hayes
5.7.2 9:00 - 9:30	Accuracy Analysis for Stochastic Circuits with D-Flip Flop Insertion Kuncai Zhong and Weikang Qian
5.7.3 9:30 - 10:00	Dynamic Stochastic Computing for Digital Signal Processing Applications Siting Liu and Jie Han

Session Title	Special Session: HLS for AI HW
Session Code / Room	5.8 / Exhibition Theatre
Date / Time	Wednesday 11 March 2020 / 08:30 - 10:00
Chair	Massimo Cecchetti, Mentor, A Siemens Business, US
Co-Chair	Astrid Ernst, Mentor, A Siemens Business, US

5.8.1 8:30 - 9:00	Introduction to HLS Concepts Open-Source IP and References Designs Enabling Building AI Acceleration Hardware Mike Fingeroff
5.8.2 9:00 - 9:30	Early Soc Performance Verification Using Systemc With Nvidia Matchlib and HLS Stuart Swan
5.8.3 9:30 - 10:00	Customer Case Studies of Using HLS for Ultra-Low Power AI Hardware Acceleration Ellie Burns

Session Title	Interactive Presentations
Session Code / Room	IP2 / Poster Area
Date / Time	Wednesday 11 March 2020 / 10:00 - 10:30

IP2-1	Sampling from Discrete Distributions in Combinational Hardware with Application to Post-Quantum Cryptography Michael X. Lyons and Kris Gaj
IP2-2	On the Performance of Non-Profiled Differential Deep Learning Attacks against an AES Encryption Algorithm Protected using a Correlated Noise Generation based Hiding Countermeasure Amir Alipour, Athanasios Papadimitriou, Vincent Beroulle, Ehsan Aerabi, David Hély
IP2-3	Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes Vladimir Herdt, Daniel Große and Rolf Drechsler
IP2-4	Automated Generation of LTL Specifications For Smart Home IoT Using Natural Language Shiyu Zhang, Juan Zhai, Lei Bu, Mingsong Chen, Linzhang Wang and Xuandong Li
IP2-5	A Heat-Recirculation-Aware VM Placement Strategy for Data Centers Hao Feng, Yuhui Deng and Yi Zhou
IP2-6	Energy Optimization in NCFET-based Processors Sami Salamin, Martin Rapp, Hussam Amrouch, Andreas Gerstlauer and Jörg Henkel
IP2-7	Towards a Model-based Multi-Objective Optimization Approach For Safety-Critical Real-Time Systems Soulimane Kamni, Yassine Ouhammou, Antoine Bertout and Emmanuel Grolleau
IP2-8	Current-Mode Carry-Free Multiplier Design using a Memristor-Transistor Crossbar Architecture Shengqi Yu, Ahmed Soltan, Rishad Shafik, Thanasin Bunnam, Fei Xia, Domenico Balsamo and Alex Yakovlev
IP2-9	n-bit Data Parallel Spin Wave Logic Gate Abdulqader Mahmoud, Frederic Vanderveken, Florin Ciubotaru Christoph Adelmann, Sorin Cotofana and Said Hamdioui
IP2-10	High-Speed Analog Simulation of CMOS Vision Chips Using Explicit Integration Techniques on Many-Core Processors Gines Domenech-Asensi and Tom J. Kazmierski
IP2-11	A 100KHz-1GHz Termination-dependent Human Body Communication Channel Measurement using Miniaturized Wearable Devices Shitij Avlani, Mayukh Nath, Shovan Maity and Shreyas Sen
IP2-12	From DRUP to PAC and Back Daniela Kaufmann, Armin Biere and Manuel Kauers
IP2-13	Verifiable Security Templates for Hardware William L. Harrison and Gerard Allwein
IP2-14	IFFSET: In-Field Fuzzing of Industrial Control Systems using System Emulation Dimitrios Tychalas and Michail Maniatakos
IP2-15	FANNet: Formal Analysis of Noise Tolerance, Training Bias and Input Sensitivity in Neural Networks Mahum Naseer, Mishal Fatima Minhas, Faiq Khalid, Muhammad Abdullah Hanif, Osman Hasan and Muhammad Shafique
IP2-16	A Scalable Mixed Synthesis Framework for Heterogeneous Networks Max Austin, Scott Temple, Walter Lau Neto, Luca Amarù, Xifan Tang and Pierre-Emmanuel Gaillardon
IP2-17	DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies Shubham Rai, Michael Raitza, Siva Satyendra Sahoo and Akash Kumar
IP2-18	A 16×128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream Length Qian Chen, Yuqi Su, Hyunjoon Kim, Taegeun Yoo, Tony Tae-Hyoung Kim and Bongjin Kim
IP2-19	Towards Exploring the Potential of Alternative Quantum Computing Architectures Arighna Deb, Gerhard W. Dueck and Robert Wille
IP2-20	Accelerating Quantum Approximate Optimization Algorithm using Machine Learning Mahabubul Alam, Abdullah Ash-Saki and Swaroop Ghosh

Session Title	Special Day on "Embedded AI": Emerging Devices, Circuits and Systems
Session Code / Room	6.1 / Amphithéâtre Jean Prouve
Date / Time	Wednesday 11 March 2020 / 11:00 - 12:30
Chair	Carlo Reita, CEA, FR
Co-Chair	Bernabe Linares-Barranco, CSIC, ES

6.1.1 11:00 - 11:22	In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical Applications Bogdan Penkovsky, Marc Bocquet, Tifenn Hirtzlin, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal and Damien Querlioz
6.1.2 11:22 - 11:44	Mixed-Signal Vector-by-Matrix Multiplier Circuits Based on 3D-NAND Memories for Neurocomputing Mohammad Bavandpour, Shubham Sahay, Mohammad Reza Mahmoodi and Dmitri Strukov
6.1.3 11:44 - 12:06	Modular Rram Based In-Memory Computing Design for Embedded AI Xinxin Wang, Qiwen Wang, Mohammed A. Zidan, Fan-Hsuan Meng, John Moon and Wei Lu
6.1.4 12:06 - 12:30	Neuromorphic Computing: Toward Dynamical Data Processing Fabian Alibart

Session Title	Secure and fast memory and storage
Session Code / Room	6.2 / Chamrousse
Date / Time	Wednesday 11 March 2020 / 11:00 - 12:30
Chair	Hao Yu, SUSTech, CN
Co-Chair	Chengmo Yang, University of Delaware, US

6.2.1 11:00 - 11:30	An Efficiant Persistency and Recovery Mechanism for SGX-style Integrity Tree in Secure NVM Mengya Lei, Fang Wang, Dan Feng, Fan Li and Jie Xu
6.2.2 11:30 - 12:00	Revisiting Persistent Hash Table Design for Commercial Non-Volatile Memory Kaixin Huang, Yan Yan and Linpeng Huang
6.2.3 12:00 - 12:15	Optimizing Performance of Persistent Memory File Systems using Virtual Superpages Chaoshu Yang, Duo Liu, Runyu Zhang, Xianzhang Chen, Shun Nie, Qingfeng Zhuge and Edwin H.-M. Sha
6.2.4 12:15 - 12:30	Frequent Access Pattern-based Prefetching Inside of Solid-State Drives Xiaofei Xu, Zhigang Cai, Jianwei Liao and Yutaka Ishiakwa

Session Title	Special Session: Modern Logic Reasoning Methods for Functional ECO
Session Code / Room	6.3 / Autrans
Date / Time	Wednesday 11 March 2020 / 11:00 - 12:30
Chair	Patrick Vuillod, Synopsys, US
Co-Chair	Christoph Scholl, Albert-Ludwigs-University Freiburg, DE

6.3.1 11:00 - 11:20	Engineering Change Order for Combinational and Sequential Design Rectification Jie-Hong R. Jiang, Victor N. Kravets and Nian-Ze Lee
6.3.2 11:20 - 11:40	Exact DAG-Aware Rewriting Heinz Riener, Alan Mishchenko and Mathias Soeken
6.3.3 11:40 - 12:05	Learning to Automate the Design Updates From Observed Engineering Changes in the Chip Development Cycle Victor N. Kravets, Jie-Hong R. Jiang and Heinz Riener
6.3.4 12:05 - 12:30	Synthesis and Optimization of Multiple Portions of Circuits for ECO based on Set-Covering and QBF Formulations Masahiro Fujita, Yusuke Kimura, Xingming Le, Yukio Miyasaka and Amir Masoud Gharehbaghi

Session Title	Microarchitecture to the rescue of memory
Session Code / Room	6.4 / Stendhal
Date / Time	Wednesday 11 March 2020 / 11:00 - 12:30
Chair	Olivier Sentieys, INRIA, FR
Co-Chair	Jeronimo Castrillon, TU Dresden, DE

6.4.1 11:00 - 11:30	Efficient Hardware-Assisted Crash Consistency in Encrypted Persistent Memory Zhan Zhang, Jianhui Yue, Xiaofei Liao and Hai Jin
6.4.2 11:30 - 12:00	2DCC: Cache Compression in Two Dimensions Amin Ghasemazar, Mohammad Ewais, Prashant Nair and Mieszko Lis
6.4.3 12:00 - 12:30	GRAPHVINE: Exploiting Multicast for Scalable Graph Analytics Leul Belayneh and Valeria Bertacco

Session Title	Efficient Data Representations in Neural Networks
Session Code / Room	6.5 / Bayard
Date / Time	Wednesday 11 March 2020 / 11:00 - 12:30
Chair	Brandon Reagen, Facebook and New York University, US
Co-Chair	Sebastian Steinhorst, TU Munich, DE

6.5.1 11:00 - 11:30	ACOUSTIC: Accelerating Convolutional Neural Networks through Or-Unipolar Skipped Stochastic Computing Wojciech Romaszkan, Tianmu Li, Tristan Melton, Sudhakar Pamarti and Puneet Gupta
6.5.2 11:30 - 12:00	Accuracy Tolerant Neural Networks Under Aggressive Power Optimization Xiang-Xiu Wu, Yi-Wen Hung, Yung-Chih Chen and Shih-Chieh Chang
6.5.3 12:00 - 12:15	A Convolutional Result Sharing Approach for Binarized Neural Network Inference Ya-Chun Chang, Chia-Chun Lin, Yi-Ting Lin, Yung-Chih Chen and Chun-Yao Wang
6.5.4 12:15 - 12:30	PhoneBit: Efficient GPU-Accelerated Binary Neural Network Inference Engine for Mobile Phones Gang Chen, Shengyu He, Haitao Meng and Kai Huang

Session Title	From DFT to Yield Optimization
Session Code / Room	6.6 / Lesdiguières
Date / Time	Wednesday 11 March 2020 / 11:00 - 12:30
Chair	Maria Micheal, University of Cyprus, CY
Co-Chair	Sanchez Ernesto, Politecnico di Torino, IT

6.6.1 11:00 - 11:30	A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs Guilherme Cardoso Medeiros, Cemil Cem Gürsoy, Lizhou Wu, Moritz Fieback, Maksim Jenihhin, Mottaqiallah Taouil and Said Hamdioui
6.6.2 11:30 - 12:00	Synthesis of Fault-Tolerant Reconfigurable Scan Networks Sebastian Brandhofer, Michael A. Kochte and Hans-Joachim Wunderlich
6.6.3 12:00 - 12:15	Using Programmable Delay Monitors for Wear-Out and Early Life Failure Prediction Chang Liu, Eric Schneider and Hans-Joachim Wunderlich
6.6.4 12:15 - 12:30	Maximizing Yield for Approximate Integrated Circuits Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi and Alberto Bosio

Session Title	Safety and efficiency for smart automotive and energy systems
Session Code / Room	6.7 / Berlioz
Date / Time	Wednesday 11 March 2020 / 11:00 - 12:30
Chair	Selma Saidi, TU Dortmund, DE
Co-Chair	Donghwa Shin, Soongsil University, KR

6.7.1 11:00 - 11:30	A Diode-Aware Model of PV Modules from Datasheet Specifications Sara Vinco, Yukai Chen, Enrico Macii and Massimo Poncino
6.7.2 11:30 - 12:00	Achieving Determinism in Adaptive AUTOSAR Christian Menard, Andrés Goens, Marten Lohstroh and Jeronimo Castrillon
6.7.3 12:00 - 12:15	A Fail-safe Architecture for Automated Driving Sebastian vom Dorff, Bert Böddeker, Maximilian Kneissl and Martin Fränzle
6.7.4 12:15 - 12:30	Priority-Preserving Optimization of Status Quo ID-Assignments in Controller Area Network Sebastian Schwitalla, Lea Schönberger and Jian-Jia Chen

Session Title	LUNCHTIME KEYNOTE SESSION: Leveraging Embedded Intelligence in Industry: Challenges and Opportunities
Session Code / Room	7.0 / Amphitéâtre Jean Prouvé
Date / Time	Wednesday 11 March 2020 / 13:45 - 14:20
Chair	Bernabe Linares-Barranco, CSIC, ES
Co-Chair	Dmitri Strukov, University of California, Santa Barbara, US

7.0.0 13:45 - 13:50	CEDA Luncheon Announcement David Atienza
7.0.1 13:50 - 14:20	Leveraging Embedded Intelligence In Industry: Challenges and Opportunities Jim Tung

Session Title	Special Day on "Embedded AI": Industry AI chips
Session Code / Room	7.1 / Amphithéâtre Jean Prouve
Date / Time	Wednesday 11 March 2020 / 14:30 - 16:00
Chair	Tobi Delbrück, ETH Zurich, CH
Co-Chair	Bernabe Linares-Barranco, CSIC, ES

7.1.1 14:30 - 14:52	Opportunities for Analog Acceleration of Deep Learning With Phase Change Memory Pritish Narayanan, Geoffrey W. Burr, Stefano Ambrogio, Hsinyu Tsai, Charles Mackin, Katherine Spoon, An Chen, Alexander Friz and Andrea Fasoli
7.1.2 14:52 - 15:14	Event-Based Ai for Automotive and IOT Etienne Perot
7.1.3 15:14 - 15:36	NeuronFlow: a neuromorphic processor architecture for Live AI applications Orlando Moreira, Amirreza Yousefzadeh, Fabian Chersi, Gokturk Cinserin, Rik-Jan Zwartenkot, Ajay Kapoor, Peng Qiao, Peter Kievits, Mina Khoei, Louis Rouillard, Aimee Ferouge, Jonathan Tapson and Ashoka Visweswara
7.1.4 15:36 - 16:00	Speck - Sub-Mw Smart Vision Sensor for Mobile IOT Applications Ning Qiao

Session Title	Reconfigurable Systems and Architectures
Session Code / Room	7.2 / Chamrousse
Date / Time	Wednesday 11 March 2020 / 14:30 - 16:00
Chair	Christian Pilato, Politecnico di Milano, IT
Co-Chair	Philippe Coussy, University Bretagne Sud / Lab-STICC, FR

7.2.1 14:30 - 15:00	A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs Ankita Nayak, Keyi Zhang, Raj Setaluri, Alex Carsello, Makai Mann, Stephen Richardson, Rick Bahr, Pat Hanrahan, Mark Horowitz and Priyanka Raina
7.2.2 15:00 - 15:30	BlastFunction: An FPGA-as-a-Service System for Accelerated Serverless Computing Marco Bacis, Rolando Brondolin and Marco D. Santambrogio
7.2.3 15:30 - 16:00	Energy-aware Placement for SRAM-NVM Hybrid FPGAs Seongsik Park, Jongwan Kim and Sungroh Yoon

Session Title	Special Session: Realizing Quantum Algorithms on Real Quantum Computing Devices
Session Code / Room	7.3 / Autrans
Date / Time	Wednesday 11 March 2020 / 14:30 - 16:00
Chair	Eduard Alarcon, UPC BarcelonaTech, ES
Co-Chair	Swaroop Ghosh, Pennsylvania State University, US

7.3.1 14:30 - 14:45	Running Quantum Algorithms On Resource-Constrained Quantum Devices Carmen G. Almudever
7.3.2 14:45 - 15:00	Realizing Quantum Circuits On IBM Q Devices Robert Wille
7.3.3 15:00 - 15:30	Every Device is (Almost) Equal Before the Compiler Gian Giacomo Guerreschi
7.3.4 15:30 - 16:00	Realizing Quantum Algorithms on Real Quantum Computing Devices Carmen G. Almudever, Lingling Lao, Robert Wille and Gian G. Guerreschi

Session Title	Simulation and Verification: Where Real Issues Meet Scientific Innovation
Session Code / Room	7.4 / Stendhal
Date / Time	Wednesday 11 March 2020 / 14:30 - 16:00
Chair	Avi Ziv, IBM, IL
Co-Chair	Graziano Pravadelli, Università di Verona, IT

7.4.1 14:30 - 15:00	Verification Runtime Analysis: Get the Most Out of Partial Verification Martin Ring, Fritjof Bornebusch, Christoph Lüth, Robert Wille and Rolf Drechsler
7.4.2 15:00 - 15:30	GPU-accelerated Time Simulation of Systems with Adaptive Voltage and Frequency Scaling Eric Schneider and Hans-Joachim Wunderlich
7.4.3 15:30 - 15:45	Lazy Event Prediction using Defining Trees and Schedule Bypass for Out-of-Order PDES Daniel Mendoza, Zhongqi Cheng, Emad Arasteh and Rainer Dömer
7.4.4 15:45 - 16:00	Embedding Hierarchical Signal to Siamese Network for Fast Name Rectification Yi-An Chen, Gung-Yu Pan, Che-Hua Shih, Yen-Chin Liao, Chia-Chih Yen and Hsie-Chia Chang

Session Title	Runtime Support for Multi/Many Cores
Session Code / Room	7.5 / Bayard
Date / Time	Wednesday 11 March 2020 / 14:30 - 16:00
Chair	Sara Vinco, Politecnico di Torino, IT
Co-Chair	Jeronimo Castrillon, TU Dresden, DE

7.5.1 14:30 - 15:00	Resource-Aware MapReduce Runtime for Multi/Many-core Architectures Konstantinos Iliakis, Sotirios Xydis and Dimitrios Soudris
7.5.2 15:00 - 15:30	Towards a Qualifiable OpenMP Framework for Embedded Systems Adrian Munera, Sara Royuela and Eduardo Quiñones
7.5.3 15:30 - 16:00	Energy-efficient Runtime Resource Management for Adaptable Multi-application Mapping Robert Khasanov and Jeronimo Castrillon

Session Title	Attacks on Hardware Architectures
Session Code / Room	7.6 / Lesdiguières
Date / Time	Wednesday 11 March 2020 / 14:30 - 16:00
Chair	Johanna Sepúlveda, Airbus Defence and Space, DE
Co-Chair	Jean-Luc Danger, Télécom ParisTech, FR

7.6.1 14:30 - 15:00	Sweeping for Leakage in Masked Circuit Layouts Danilo Šijačić, Josep Balasch and Ingrid Verbauwhede
7.6.2 15:00 - 15:15	Increased Reproducibility and Comparability of Data Leak Evaluations Using ExOT Philipp Miedl, Bruno Klopott and Lothar Thiele
7.6.3 15:15 - 15:30	GhostBusters: Mitigating Spectre Attacks on a DBT-Based Processor Simon Rokicki
7.6.4 15:30 - 15:45	Dynamic Faults based Hardware Trojan Design in STT-MRAM Sarath Mohanachandran Nair, Rajendra Bishnoi, Arunkumar Vijayan and Mehdi B. Tahoori
7.6.5 15:45 - 16:00	Oracle-based Logic Locking Attacks: Protect the Oracle Not Only the Netlist Emmanouil Kalligeros, Nikolaos Karousos and Irene G. Karybali

Session Title	Self-Adaptive and Learning Systems
Session Code / Room	7.7 / Berlioz
Date / Time	Wednesday 11 March 2020 / 14:30 - 16:00
Chair	Gilles Sassatelli, Université de Montpellier, FR
Co-Chair	Rishad Shafik, University of Newcastle, GB

7.7.1 14:30 - 15:00	AnytimeNet: Controlling Time-Quality Tradeoffs in Deep Neural Network Architectures Jung-Eun Kim, Richard Bradford and Zhong Shao
7.7.2 15:00 - 15:30	AntiDote: Attention-based Dynamic Optimization for Neural Network Runtime Efficiency Fuxun Yu, Chenchen Liu, Di Wang, Yanzhi Wang and Xiang Chen
7.7.3 15:30 - 16:00	Using Learning Classifier Systems for the DSE of Adaptive Embedded Systems Fedor Smirnov, Behnaz Pourmohseni and Jürgen Teich

Session Title	Interactive Presentations
Session Code / Room	IP3 / Poster Area
Date / Time	Wednesday 11 March 2020 / 16:00 - 16:30

IP3-1	CNT-Cache: an Energy-Efficient Carbon Nanotube Cache with Adaptive Encoding Dawen Xu, Kexin Chu, Cheng Liu, Ying Wang, Lei Zhang and Huawei Lie
IP3-2	Enhancing Multithreaded Performance of Asymmetric Multicores with SIMD Offloading Jeckson Dellagostin Souza, Madhavan Manivannan, Miquel Pericàs and Antonio Carlos Schneider Beck
IP3-3	Hardware Acceleration of CNN with One-Hot Quantization of Weights and Activations Gang Li, Peisong Wang, Zejian Liu, Cong Leng and Jian Cheng
IP3-4	BNNsplit: Binarized Neural Networks for embedded distributed FPGA-based computing systems Giorgia Fiscaletti, Marco Speziali, Luca Stornaiuolo, Marco D. Santambrogio and Donatella Sciuto Politecnico di Milano
IP3-5	L2L: A Highly Accurate Log_2_Lead Quantization of Pre-trained Neural Networks Salim Ullah, Siddharth Gupta, Kapil Ahuja, Aruna Tiwari and Akash Kumar
IP3-6	Fault Diagnosis of Via-Switch Crossbar in Non-volatile FPGA Ryutaro Doi, Xu Bai, Toshitsugu Sakamoto and Masanori Hashimoto
IP3-7	Applying Reservation-based Scheduling to a C-based Hypervisor: An industrial case study Dakshina Dasari, Michael Pressler, Arne Hamann, Dirk Ziegenbein and Paul Austin
IP3-8	Real-Time Energy Monitoring in IoT-enabled Mobile Devices Nitin Shivaraman, Seima Saki, Zhiwei Liu, Saravanan Ramanathan, Arvind Easwaran and Sebastian Steinhorst
IP3-9	Towards Specification and Testing of RISC-V ISA Compliance Vladimir Herdt, Daniel Große and Rolf Drechsler
IP3-10	Post-Silicon Validation of the IBM POWER9 Processor Tom Kolan, Hillel Mendelson, Vitali Sokhin, Kevin Reick, Elena Tsanko and Greg Wetli
IP3-11	On the Task Mapping and Scheduling for DAG-based Embedded Vision Applications on Heterogeneous Multi/Many-core Architectures Stefano Aldegheri, Nicola Bombieri and Hiren Patel
IP3-12	Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks? Ognjen Glamočanin, Louis Coulon, Francesco Regazzoni and Mirjana Stojilović
IP3-13	Efficient Training on Edge Devices Using Online Quantization Michale H.Ostertag, Sarah Al-Doweesh and Tajana Rosing
IP3-14	Multi-Agent Actor-Critic Method for Joint Duty-Cycle and Transmission Power Control Sota Sawaguchi, Jean-Frédéric Christmann, Anca Molnos, Carolynn Bernier and Suzanne Lesecq

Session Title	Special Day on "Embedded AI": Neuromorphic chips and systems
Session Code / Room	8.1 / Amphithéâtre Jean Prouve
Date / Time	Wednesday 11 March 2020 / 17:00 - 18:30
Chair	Wei Lu, University of Michigan, US
Co-Chair	Bernabe Linares-Barranco, CSIC, ES

8.1.1 17:00 - 17:30	SPINNAKER2 : A Platform for Bio-Inspired Artificial Intelligence and Brain Simulation Bernhard Vogginger, Christian Mayr, Sebastian Höppner, Johannes Partzsch and Steve Furber
8.1.2 17:30 - 18:00	An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays Shruti R. Kulkarni, Shihui Yin, Jae-sun Seo and Bipin Rajendran
8.1.3 18:00 - 18:30	Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories Shanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang and Shimeng Yu

Session Title	We are all Hackers: Design and Detection of Security Attacks
Session Code / Room	8.2 / Chamrousse
Date / Time	Wednesday 11 March 2020 / 17:00 - 18:30
Chair	Regazzoni Francesco, ALaRI, CH
Co-Chair	Daniel Grosse, University of Bremen, DE

8.2.1 17:00 - 17:30	Automated Test Generation for Trojan Detection using Delay-based Side Channel Analysis Yangdi Lyu and Prabhat Mishra
8.2.2 17:30 - 18:00	Microfluidic Trojan Design in Flow-based Biochips Mohammed Shayan, Sukanta Bhattacharjee, Yong-Ak Song, Krishnendu Chakrabarty and Ramesk Karri
8.2.3 18:00 - 18:30	Towards Malicious Exploitation of Energy Management Mechanisms Safouane Noubir, Maria Mendez Real and Sébastien Pillement

Session Title	Optimizing System-Level Design for Machine Learning
Session Code / Room	8.3 / Autrans
Date / Time	Wednesday 11 March 2020 / 17:00 - 18:30
Chair	Luciano Lavagno, Politecnico di Torino, IT
Co-Chair	Yuko Hara-Azumi, Tokyo Institute of Technology, JP

8.3.1 17:00 - 17:30	ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning Davide Giri, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani and Luca P. Carloni
8.3.2 17:30 - 18:00	Probabilistic Sequential Multi-Objective Optimization of Convolutional Neural Networks Zixuan Yin, Warren Gross and Brett H. Meyer
8.3.3 18:00 - 18:30	ARS: Reducing F2FS Fragmentation for Smartphones using Decision Trees Lihua Yang, Fang Wang, Zhipeng Tan, Dan Feng, Jiaxing Qian and Shiyun Tu

Session Title	Architectural and Circuit Techniques toward Energy-efficient Computing
Session Code / Room	8.4 / Stendhal
Date / Time	Wednesday 11 March 2020 / 17:00 - 18:30
Chair	Sara Vinco, Politecnico di Torino, IT
Co-Chair	Davide Rossi, Università di Bologna, IT

8.4.1 17:00 - 17:30	TRANSPIRE: An Energy-efficient TRANSprecision Floating-point Programmable archItectuRE Rohit Prasad, Satyajit Das, Kevin J. M. Martin, Giuseppe Tagliavini, Philippe Coussy, Luca Benini and Davide Rossi
8.4.2 17:30 - 18:00	Modeling and Designing of a PVT Auto-tracking Timing-speculative SRAM Shan Shen, Tianxiang Shao, Ming Ling, Jun Yang and Longxing Shi
8.4.3 18:00 - 18:15	Solving Constraint Satisfaction Problems Using the Loihi Spiking Neuromorphic Processor Chris Yakopcic, Nayim Rahman, Tanvir Atahary, Tarek M. Taha and Scott Douglass
8.4.4 18:15 - 18:30	Accurate Power Density Map Estimation for Commercial Multi-Core Microprocessors Jinwei Zhang, Sheriff Sadiqbatcha, Wentian Jin and Sheldon X.-D. Tan

Session Title	CNN Dataflow Optimizations
Session Code / Room	8.5 / Bayard
Date / Time	Wednesday 11 March 2020 / 17:00 - 18:30
Chair	Mario Casu, Politecnico di Torino, IT
Co-Chair	Wanli Chang, University of York, GB

8.5.1 17:00 - 17:30	Analysis and Solution of CNN Accuracy Reduction over Channel Loop Tiling Yesung Kang, Yoonho Park, Sunghoon Kim, Eunji Kwon, Taeho Lim, Sangyun Oh, Mingyu Woo and Seokhyeong Kang
8.5.2 17:30 - 18:00	DC-CNN: Computational Flow Redefinition for Efficient CNN through Structural Decoupling Fuxun Yu, Zhuwei Qin, Di Wang, Ping Xu, Chenchen Liu, Zhi Tian and Xiang Chen
8.5.3 18:00 - 18:15	ABC: Abstract prediction Before Concreteness Jung-Eun Kim, Richard Bradford, Man-Ki Yoon and Zhong Shao
8.5.4 18:15 - 18:30	A Compositional Approach Using Keras for Neural Networks in Real-Time Systems Xin Yang, Partha Roop, Hammond Pearce and Jin Woo Ro

Session Title	Microarchitecture-level Reliability Analysis and Protection
Session Code / Room	8.6 / Lesdiguières
Date / Time	Wednesday 11 March 2020 / 17:00 - 18:30
Chair	Michail Maniatakos, New York University Abu Dhabi, UA
Co-Chair	Alessandro Savino, Politecnico di Torino, IT

8.6.1 17:00 - 17:30	rACE: Reverse-Order Processor Reliability Analysis Athanasios Chatzidimitriou and Dimitris Gizopoulos
8.6.2 17:30 - 18:00	DEFCON: Generating and Detecting Failure-prone Instruction Sequences via Stochastic Search Ioannis Tsiokanos, Lev Mukhanov, Giorgis Georgakoudis, Dimitrios S.Nikolopoulos and Georgios Karakonstantis
8.6.3 18:00 - 18:30	LAD-ECC: Energy-Efficient ECC Mechanism for GPGPUs Register File Xiaohui Wei, Hengshan Yue and Jingweijia Tan

Session Title	Physical Design and Analysis
Session Code / Room	8.7 / Berlioz
Date / Time	Wednesday 11 March 2020 / 17:00 - 18:30
Chair	Vasilis Pavlidis, The University of Manchester, GB
Co-Chair	L. Miguel Silveira, INESC ID / IST, U Lisboa, PT

8.7.1 17:00 - 17:30	Floating Random Walk Based Capacitance Solver for VLSI Structures with Non-Stratified Dielectrics Mingye Song, Ming Yang and Wenjian Yu
8.7.2 17:30 - 18:00	Towards Serial-Equivalent Multi-Core Parallel Routing for FPGAs Minghua Shen and Nong Xiao
8.7.3 18:00 - 18:15	Self-Aligned Double-Patterning Aware Legalization Hua Xiang, Gi-Joon Nam, Gustavo Tellez, Shyam Ramji and Xiaoqing Xu
8.7.4 18:15 - 18:30	Explainable DRC Hotspot Prediction with Random Forest and SHAP Tree Explainer Wei Zeng, Azadeh Davoodi and Rasit Onur Topaloglu

Session Title	Special Day on "Silicon Photonics": Advancements on Silicon Photonics
Session Code / Room	9.1 / Amphithéâtre Jean Prouve
Date / Time	Thursday 12 March 2020 / 08:30 - 10:00
Chair	Gabriela Nicolescu, Polytechnique Montréal, CA
Co-Chair	Luca Ramini, Hewlett Packard Labs, US

9.1.1 8:30 - 9:00	System Study of Silicon Photohotonicnics Modulator In Short Reach Gridless Coherent Networks Sadok Aouini, Ahmad Abdo, Xueyang Li, Md Samiul Alam, Mahdi Parvizi, Claude D'Amours and David V. Plant
9.1.2 9:00 - 9:30	Fully Integrated Photonic Circuits On Silicon By Means of Iii-V/Silicon Bonding Florian Denis
9.1.3 9:30 - 10:00	III-V/Silicon Hybrid Lasers Integration On CMOS-Compatible 200mm and 300mm Platforms Karim Hassan, Szelag Bertrand, Laetitia Adelmini, Cecilia Dupre, Elodie Ghegin, Philippe Rodriguez, Fabrice Nemouchi, Pierre Brianceau, Antoine Schembri, David Carrara, Pierrick Cavalie, Florent Franchin, Marie-Christine Roure, Loic Sanchez, Christophe Jany and Ségoléne Olivier

Session Title	Autonomous Systems Design Initiative: Architectures and Frameworks for Autonomous Systems
Session Code / Room	9.2 / Chamrousse
Date / Time	Thursday 12 March 2020 / 08:30 - 10:00
Chair	Selma Saidi, TU Dortmund, DE
Co-Chair	Rolf Ernst, TU Braunschweig, DE

9.2.1 8:30 - 9:00	DeepRacing: A Framework for Autonomous Racing Trent Weiss and Madhur Behl
9.2.2 9:00 - 9:30	Fail-Operational Automotive Software Design Using Agent-Based Graceful Degradation Philipp Weiss, Andreas Weichslgartner, Felix Reimann and Sebastian Steinhorst
9.2.3 9:30 - 10:00	A Distributed Safety Mechanism using Middleware and Hypervisors for AutonomousVehicles Tjerk Bijlsma, Andrii Buriachevskyi, Alessandro Frigerio, Yuting Fu, Kees Goossens, Ali Osman Örs, Pieter J. van der Perk, Andrei Terechko and Bart Vermeulen

Session Title	Special Session: In Memory Computing for Edge AI
Session Code / Room	9.3 / Autrans
Date / Time	Thursday 12 March 2020 / 08:30 - 10:00
Chair	Maha Kooli, CEA-Leti, FR
Co-Chair	Alexandre Levisse, EPFL, CH

9.3.1 8:30 - 8:50	Fledge: Flexible Edge Platforms Enabled by In-memory Computing Kamalika Datta, Arko Dutt, Ahmed Zaky, Umesh Chand, Devendra Singh, Yida Li, Jackson Chun-Yang Huang, Aaron Thean and Mohamed M Sabry Aly
9.3.2 8:50 - 9:10	Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing J.-P. Noel, V. Egloff, M. Kooli, R. Gauchi, J.-M. Portal, H.-P. Charles, P. Vivet and B. Giraud
9.3.3 9:10 - 9:35	Demonstrating In-Cache Computing Thanks to Cross-Layer Design Optimizations Marco Rios, William Simon, Alexandre Levisse, Marina Zapater and David Atienza
9.3.4 9:35 - 10:00	Device, Circuit and Software Innovations to Make Deep Learning With Analog Memory A Reality Pritish Narayanan, Stefano Ambrogio, Hsinyu Tsai, Katie Spoon and Geoffrey W. Burr

Session Title	Efficient DNN Design with Approximate Computing.
Session Code / Room	9.4 / Stendhal
Date / Time	Thursday 12 March 2020 / 08:30 - 10:00
Chair	Daniel Menard, INSA Rennes, FR
Co-Chair	Seokhyeong Kang, Pohang University of Science and Technology, KR

9.4.1 8:30 - 9:00	ProxSim: GPU-based Simulation Framework for Cross-Layer Approximate DNN Optimization Cecilia De la Parra, Andre Guntoro and Akash Kumar
9.4.2 9:00 - 9:30	PCM: Precision-Controlled Memory System for Energy Efficient Deep Neural Network Training Boyeal Kim, Sang Hyun Lee, Hyun Kim, Duy-Thanh Nguyen, Minh-Son Le, Ik Joon Chang, Dohun Kwon, Jin Hyeok Yoo, Jun Won Choi and Hyuk-Jae Lee
9.4.3 9:30 - 10:00	ReD-CaNe: A Systematic Methodology for Resilience Analysis and Design of Capsule Networks under Approximations Alberto Marchisio, Vojtech Mrazek, Muhammad Abudllah Hanif and Muhammad Shafique

Session Title	Emerging Memory Devices
Session Code / Room	9.5 / Bayard
Date / Time	Thursday 12 March 2020 / 08:30 - 10:00
Chair	Alexandere Levisse, EPFL, CH
Co-Chair	Marco Vacca, Politecnico di Torino, IT

9.5.1 8:30 - 9:00	Impact of Magnetic Coupling and Density on STT-MRAM Performance L. Wu, S. Rao, M. Taouil, E.J. Marinissen, G. S. Kar and S. Hamdioui
9.5.2 9:00 - 9:30	High-Density, Low-Power Voltage-Control Spin Orbit Torque Memory with Synchronous Two-Step Write and Symmetric Read Techniques Haotian Wang, Wang Kang, Liuyang Zhang, He Zhang, Brajesh Kumar Kaushik and Weisheng Zhao
9.5.3 9:30 - 10:00	Design of Almost-Nonvolatile Embedded DRAM Using Nanoelectromechanical Relay Devices Hongtao Zhong, Mingyang Gu, Juejian Wu, Huazhong Yang and Xueqing Li

Session Title	Intelligent Dependable Systems
Session Code / Room	9.6 / Lesdiguières
Date / Time	Thursday 12 March 2020 / 08:30 - 10:00
Chair	Saqib Khursheed, University of Liverpool, GB
Co-Chair	Rishad Shafik, Newcastle University, GB

9.6.1 8:30 - 9:00	Thermal-Cycling-aware Dynamic Reliability Management in Many-Core System-on-Chip Mohammad-Hashem Haghbayan, Antonio Miele, Zhuo Zou, Hannu Tenhunen and Juha Plosila
9.6.2 9:00 - 9:30	Deterministic Cache-based Execution of On-line Self-Test Routines in Multi-core Automotive System-on-Chips Andrea Floridia, Tzamn Melendez Carmona, Davide Piumatti, Annachiara Ruospo, Ernesto Sanchez, Sergio De Luca, Rosario Martorana and Mose Alessandro Pernice
9.6.3 9:30 - 10:00	FT-ClipAct: Resilience Analysis of Deep Neural Networks and Improving their Fault Tolerance using Clipped Activation Le-Ha Hoang, Muhammad Abdullah Hanif and Muhammad Shafique

Session Title	Diverse Applications of Emerging Technologies
Session Code / Room	9.7 / Berlioz
Date / Time	Thursday 12 March 2020 / 08:30 - 10:00
Chair	Pavlidis Vasilis, The University of Manchester, GB
Co-Chair	Bing Li, TU Munich, DE

9.7.1 8:30 - 9:00	Q-learning Based Backup for Energy Harvesting Powered Embedded Systems Wei Fan, Yujie Zhang, Weining Song, Mengying Zhao, Zhaoyan Shen and Zhiping Jia
9.7.2 9:00 - 9:30	A Novel TIGFET-based DFF Design for Improved Resilience to Power Side-Channel Attacks Mohammad Mehdi Sharifi, Ramin Rajaei, Patsy Cadareanu, Pierre-Emmanuel Gaillardon, Yier Jin, Michael Niemier and X. Sharon Hu
9.7.3 9:30 - 9:45	Low Complexity Multi-directional In-Air Ultrasonic Gesture Recognition Using a TCN Emad A. Ibrahim, Marc Geilen, Jos Huisken, Min Li and José Pineda de Gyvez
9.7.4 9:45 - 10:00	PIM-Aligner: A Processing-in-MRAM Platform for Biological Sequence Alignment Shaahin Angizi, Jiao Sun, Wei Zhang and Deliang Fan

Session Title	Special Session: Panel: Variation-aware analyzes of Mega-MOSFET Memories, Challenges and Solutions
Session Code / Room	9.8 / Exhibition Theatre
Date / Time	Thursday 12 March 2020 / 08:30 - 10:00
Moderators	Firas MOHAMED, Silvaco, FR and Jean-Baptiste DULUC, Silvaco, FR Jean-Baptiste DULUC, Silvaco, FR

Session Title	Interactive Presentations
Session Code / Room	IP4 / Poster Area
Date / Time	Thursday 12 March 2020 / 10:00 - 10:30

IP4-1	HIT: A Hidden Instruction Trojan Model for Processors Jiaqi Zhang, Ying Zhang, Huawei Li and Jianhui Jiang
IP4-2	Bitstream Modification Attack on SNOW 3G Michail Moraitis and Elena Dubrova
IP4-3	A Machine Learning Based Write Policy for SSD Cache in Cloud Block Storage Yu Zhang, Ke Zhou, Ping Huang, Hua Wang, Jianying Hu, Yangtao Wang, Yongguang Ji and Bin Cheng
IP4-4	You Only Search Once: A Fast Automation Framework for Single-Stage DNN/Accelerator Co-design Weiwei Chen, Ying Wang, Shuang Yang, Chen Liu and Lei Zhang
IP4-5	When Sorting Network Meets Parallel Bitstreams: A Fault-Tolerant Parallel Ternary Neural Network Accelerator based on Stochastic Computing Yawen Zhang, Sheng Lin, Runsheng Wang, Yanzhi Wang, Yuan Wang, Weikang Qian and Ru Huang
IP4-6	WavePro: Clock-less Wave-Propagated Pipeline Compiler for Low-Power and High-Throughput Computation Yehuda Kra, Tzachi Noy and Adam Teman
IP4-7	DeepNVM: A Framework for Modeling and Analysis of Non-Volatile Memory Technologies for Deep Learning Applications Ahmet Fatih Inci, Mehmet Meric Isgenc and Diana Marculescu
IP4-8	Efficient Embedded Machine Learning applications using Echo State Networks L. Cerina, M. D. Santambrogio, G. Franco, C. Gallicchio and A. Micheli
IP4-9	ExplFrame: Exploiting Page Frame Cache for Fault Analysis of Block Ciphers Anirban Chakraborty, Sarani Bhattacharya, Sayandeep Saha and Debdeep Mukhopadhyay
IP4-10	XGBIR: An XGBoost-based IR Drop Predictor for Power Delivery Network Chi-Hsien Pao, An-Yu Su and Yu-Min Lee
IP4-11	On Pre-Assignment Route Prototyping for Irregular Bumps on BGA Packages Jyun-Ru Jiang, Yun-Chih Kuo, Simon Yi-Hung Chen and Hung-Ming Chen
IP4-12	Towards Best-effort Approximation: Applying NAS to General-purpose Approximate Computing Weiwei Chen, Ying Wang, Shuang Yang, Chen Liu and Lei Zhang
IP4-13	On the Automatic Exploration of Weight Sharing for Deep Neural Network Compression Etienne Dupuis, David Novo, Ian O’Connor and Alberto Bosio
IP4-14	Robust and High-Performance 12-T Interlocked SRAM for In-Memory Computing Neelam Surana, Mili Lavania, Abhishek Barma and Joycee MekieChang
IP4-15	High Density STT-MRAM compiler design, validation and characterization methodology in 28nm FDSOI technology Piyush Jain, Akshay Kumar, Nicolaas Van Winkelhoff, Didier Gayraud, Surya Gupta, Abdelali El Amraoui, Giorgio Palma, Alexandra Gourio, Laurent Vachez, Luc Palau, Jean-Christophe Buy and Cyrille Dray
IP4-16	An Approximation-based Fault Detection Scheme for Image Processing Applications Matteo Biasielli, Luca Cassano and Antonio Miele
IP4-17	Transport-Free Module Binding for Sample Preparation using Microfluidic Fully Programmable Valve Arrays Gautam Choudhary, Sandeep Pal, Debraj Kundu, Sukanta Bhattacharjee, Shigeru Yamashita, Bing Li, Ulf Schlichtmann and Sudip Roy

Session Title	Special Day on "Silicon Photonics": High-Speed Silicon Photonics Interconnects for Data Center and HPC
Session Code / Room	10.1 / Amphithéâtre Jean Prouve
Date / Time	Thursday 12 March 2020 / 11:00 - 12:30
Chair	Ian O'Connor, Ecole Centrale de Lyon, FR
Co-Chair	Luca Ramini, Hewlett Packard Labs, US

10.1.1 11:00 - 11:30	The Need and Challenges of Co-Packaging and Optical Integration In Data Centers Liron Gantz
10.1.2 11:30 - 12:00	Power and Cost Estimate of Scalable All-To-All Topologies With Silicon Photonics Links Luca Ramini
10.1.3 12:00 - 12:30	The Next Frontier In Silicon Photonic Design: Experimentally Validated Statistical Models Geoff Duggan, James Pond, Xu Wang, Ellen Schelew, Federico Gomez, Milad Mahpeykar, Ray Chung, Zequin Lu, Parya Samadian, Jens Niegemann, Adam Reid, Roberto Armenta, Dylan McGuire, Peng Sun, Jared Hulme, Mudit Jan and Ashkan Seyedi

Session Title	Autonomous Systems Design Initiative: Uncertainty Handling in Safe Autonomous Systems (UHSAS)
Session Code / Room	10.2 / Chamrousse
Date / Time	Thursday 12 March 2020 / 11:00 - 12:30
Chair	Philipp Mundhenk, Autonomous Intelligent Driving GmbH, DE
Co-Chair	Ahmad Adee, Bosch Corporate Research, DE

10.2.1 11:00 - 11:30	Making the Relationship between Uncertainty Estimation and Safety Less Uncertain Vincent Aravantinos and Peter Schlicht
10.2.2 11:30 - 12:00	System Theoretic View on Uncertainties Roman Gansch and Ahmad Adee
10.2.3 12:00 - 12:30	Detection of False Positive and False Negative Samples in Semantic Segmentation Matthias Rottmann, Kira Maag, Robin Chan, Fabian Hüger, Peter Schlicht and Hanno Gottschalk

Session Title	Special Session: Next Generation Arithmetic for Edge Computing
Session Code / Room	10.3 / Autrans
Date / Time	Thursday 12 March 2020 / 11:00 - 12:30
Chair	Farhad Merchant, RWTH Aachen University, DE
Co-Chair	Akash Kumar, TU Dresden, DE

10.3.1 11:00 - 11:18	Paradigm On Approximate Compute for Complex Perception-Based Neural Networks Andre Guntoro and Cecilia De la Parra
10.3.2 11:18 - 11:36	Next Generation FPGA Arithmetic for AI Martin Langhammer
10.3.3 11:36 - 11:55	Application-Specific Arithmetic Design Florent de Dinechin
10.3.4 11:55 - 12:14	A Comparison of Posit and IEEE 754 Floating-Point Arithmetic That Accounts for Exception Handling John Gustafson
10.3.5 12:14 - 12:30	Next Generation Arithmetic for Edge Computing Andre Guntoro, Cecilia De La Parra, Farhad Merchant, Florent De Dinechin, John L. Gustafson, Martin Langhammer, Rainer Leupers and Sangeeth Nambiar

Session Title	Design Methodologies for Hardware Approximation
Session Code / Room	10.4 / Stendhal
Date / Time	Thursday 12 March 2020 / 11:00 - 12:30
Chair	Lukas Sekanina, Brno University of Technology, CZ
Co-Chair	David Novo, CNRS & University of Montpellier, FR

10.4.1 11:00 - 11:30	REALM: Reduced-Error Approximate Log-based Integer Multiplier Hassaan Saadat, Haris Javaid, Aleksandar Ignjatovic and Sri Parameswaran
10.4.2 11:30 - 12:00	A fast BDD Minimization Framework for Approximate Computing Andreas Wendler and Oliver Keszocze
10.4.3 12:00 - 12:15	On the Design of High Performance HW Accelerator through High-level Synthesis Scheduling Approximations Siyuan Xu and Benjamin Carrion Schafer
10.4.4 12:15 - 12:30	Fast Kriging-based Error Evaluation for Approximate Computing Systems Justine Bonnot, Daniel Menard and Karol Desnos

Session Title	Emerging Machine Learning Applications and Models
Session Code / Room	10.5 / Bayard
Date / Time	Thursday 12 March 2020 / 11:00 - 12:30
Chair	Mladen Berekovic, TU Braunschweig, DE
Co-Chair	Sophie Quinton, INRIA, FR

10.5.1 11:00 - 11:30	Communication-efficient View-Pooling for Distributed Multi-View Neural Networks Manik Singhal, Vijay Raghunathan and Anand Raghunathan
10.5.2 11:30 - 12:00	An Anomaly Comprehension Neural Network for Surveillance Videos on Terminal Devices Yuan Cheng, Guangtai Huang, Peining Zhen, Bin Liu, Hai-Bao Chen, Ngai Wong and Hao Yu
10.5.3 12:00 - 12:30	BYNQNet: Bayesian Neural Network with Quadratic Activations for Sampling-Free Uncertainty Estimation on FPGA Hiromitsu Awano and Masanori Hashimoto

Session Title	Secure Processor Architecture
Session Code / Room	10.6 / Lesdiguières
Date / Time	Thursday 12 March 2020 / 11:00 - 12:30
Chair	Emanule Regnath, TU Munich, DE
Co-Chair	Erkay Savas, Sabanci University, TR

10.6.1 11:00 - 11:30	Capturing and Obscuring Ping-Pong Patterns to Mitigate Continuous Attacks Kai Wang, Fengkai Yuan, Rui Hou, Zhenzhou Ji and Dan Meng
10.6.2 11:30 - 12:00	Mitigating Cache-Based Side-Channel Attacks through Randomization: A Comprehensive System and Architecture Level Analysis Han Wang, Hossein Sayadi, Tinoosh Mohsenin, Liang Zhao, Avesta Sasan, Setareh Rafatirad and Houman Homayoun
10.6.3 12:00 - 12:30	Extending the RISC-V Instruction Set for Hardware Acceleration of the Post-Quantum Scheme LAC Tim Fritzmann, Georg Sigl and Johanna Sepúlveda

Session Title	Accelerators for Neuromorphic Computing
Session Code / Room	10.7 / Berlioz
Date / Time	Thursday 12 March 2020 / 11:00 - 12:30
Chair	Michael Niemier, University of Notre Dame, US
Co-Chair	Alexandre Levisse, EPFL, CH

10.7.1 11:00 - 11:30	A Pulse-width Modulation Neuron with Continuous Activation for Processing-In-Memory Engines Shuhang Zhang, Bing Li, Hai (Helen) Li and Ulf Schlichtmann
10.7.2 11:30 - 12:00	Go Unary: A Novel Synapse Coding and Mapping Scheme for Reliable ReRAM-based Neuromorphic Computing Chang Ma, Yanan Sun, Weikang Qian, Ziqi Meng, Rui Yang and Li Jiang
10.7.3 12:00 - 12:30	LightBulb: A Photonic-Nonvolatile-Memory-based Accelerator for Binarized Convolutional Neural Networks Farzaneh Zokaee, Qian Lou, Nathan Youngblood, Weichen Liu, Yiyuan Xie and Lei Jiang

Session Title	Exhibition Theatre Keynote: Design-in-the-Cloud: Myth and Reality
Session Code / Room	10.8 / Amphitéâtre Jean Prouvé
Date / Time	Thursday 12 March 2020 / 11:00 - 11:45
Speaker	Philippe Quinio, STMicroelectronics, France

Session Title	LUNCHTIME KEYNOTE SESSION
Session Code / Room	11.0 / Amphitéâtre Jean Prouvé
Date / Time	Thursday 12 March 2020 / 13:20 - 13:50
Chair	Gabriela Nicolescu, Polytechnique Montréal, CA
Co-Chair	Luca Ramini, Hewlett Packard Labs, US

11.0.1
13:20 - 13:50

Memory Driven Computing to Revolutionize the Medical Sciences
Joachim Schultze

Session Title	Special Day on "Silicon Photonics": Advanced Applications
Session Code / Room	11.1 / Amphithéâtre Jean Prouve
Date / Time	Thursday 12 March 2020 / 14:00 - 15:30
Chair	Olivier Sentieys, University of Rennes, IRISA, INRIA, FR
Co-Chair	Gabriela Nicolescu, Polytechnique Montréal, CA

11.1.1 14:00 - 14:30	System-level Evaluation of Chip-Scale Silicon Photonic Networks for Emerging Data-Intensive Applications Aditya Narayan, Yvain Thonnart, Pascal Vivety, Ajay Joshi and Ayse K. Coskun
11.1.2 14:30 - 15:00	OSCAR: An Optical Stochastic Computing AcceleRator for Polynomial Functions Hassnaa El-Derhalli, Sébastien Le Beux and Sofiène Tahar
11.1.3 15:00 - 15:30	POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems Yvain Thonnart, Stéphane Bernabé, Jean Charbonnier, Christian Bernard, David Coriat, César Fuguet, Pierre Tissier, Benoît Charbonnier, Stéphane Malhouitre, Damien Saint-Patrice, Myriam Assous, Aditya Narayan, Ayse Coskun, D. Dutoit and P. Vivet

Session Title	Autonomous Systems Design Initiative: Autonomous Cyber-Physical Systems: Modeling and Verification
Session Code / Room	11.2 / Chamrousse
Date / Time	Thursday 12 March 2020 / 14:00 - 15:30
Chair	Nikos Aréchiga, Toyota Research Institute, US
Co-Chair	Jyotirmoy V. Deshmukh, University of Southern California, US

11.2.1 14:00 - 14:30	Trustworthy Autonomy: Behavior Prediction and Validation Katherine Driggs-Campbell
11.2.2 14:30 - 15:00	On Infusing Logical Reasoning Into Robot Learning Marco Pavone
11.2.3 15:00 - 15:30	Formally-Specifiable Agent Behavior Models for Autonomous Vehicle Test Generation Jonathan DeCastro

Session Title	Special Session: Emerging Neural Algorithms and Their Impact on Hardware
Session Code / Room	11.3 / Autrans
Date / Time	Thursday 12 March 2020 / 14:00 - 15:30
Chair	Ian O'Connor, Ecole Centrale de Lyon, FR
Co-Chair	Michael Niemier, University of Notre Dame, US

11.3.1 14:00 - 14:30	Analog Resistive Crossbar Arrays for Neural Network Acceleration Martin Frank
11.3.2 14:30 - 15:00	In-Memory Computing for Memory Augmented Neural Networks X. Sharon Hu and Anand Raghunathan
11.3.3 15:00 - 15:30	Hardware Challenges for Neural Recommendation Systems Udit Gupta
11.3.3 15:00 - 15:30	Emerging Neural Algorithms and Their Impact on Hardware David Brooks, Martin M. Frank, Tayfun Gokmen, Udit Gupta, X. Sharon Hu, Shubham Jain, Ann Franchesca Laguna, Michael Niemier, Ian O'Connor, Anand Raghunathan, Ashish Ranjan, Dayane Reis, Jacob R. Stevens, Carole-Jean Wu and Xunzhao Yin

Session Title	Reliable in-Memory Computing
Session Code / Room	11.4 / Stendhal
Date / Time	Thursday 12 March 2020 / 14:00 - 15:30
Chair	Jean-Philippe Noel, CEA-Leti, FR
Co-Chair	Kvatinsky Shahar, Technion, IL

11.4.1 14:00 - 14:30	REBOC: Accelerating Block-Circulant Neural Networks in ReRAM Yitu Wang, Fan Chen, Linghao Song, C. -J. Richard Shi, Hai “Helen” Li and Yiran Chen
11.4.2 14:30 - 15:00	GraphRSim: A Joint Device-Algorithm Reliability Analysis for ReRAM-based Graph Processing Chin-Fu Nien, Yi-Jou Hsiao, Hsiang-Yun Cheng, Cheng-Yu Wen, Ya-Cheng Ko and Che-Ching Linz
11.4.3 15:00 - 15:15	STAIR: High Reliable STT-MRAM Aware Multi-Level I/O Cache Architecture by Adaptive ECC Allocation Mostafa Hadizadeh, Elham Cheshmikhani and Hossein Asadi
11.4.4 15:15 - 15:30	Effective Write Disturbance Mitigation Encoding Scheme for High-density PCM Muhammad Imran, Taehyun Kwon and Joon-Sung Yang

Session Title	Compile Time and Virtualization Support for Embedded System Design
Session Code / Room	11.5 / Bayard
Date / Time	Thursday 12 March 2020 / 14:00 - 15:30
Chair	Nicola Bombieri, Università di Verona, IT
Co-Chair	Rodolfo Pellizzoni, University of Waterloo, CA

11.5.1 14:00 - 14:30	Unified Thread- and Data-Mapping for Multi-Threaded Multi-Phase Applications on SPM Many-Cores Vanchinathan Venkataramani, Anuj Pathania and Tulika Mitra
11.5.2 14:30 - 15:00	Generalized Data Placement Strategies for Racetrack Memories Asif Ali Khan, Andrés Goens, Fazal Hameed and Jeronimo Castrillon
11.5.3 15:00 - 15:30	ARM-on-ARM: Leveraging Virtualization Extensions for Fast Virtual Platforms Lukas Jünger, Jan Luca Malte Bölke, Stephan Tobies, Rainer Leupers and Andreas Hoffmann

Session Title	Aging: Estimation and Mitigation
Session Code / Room	11.6 / Lesdiguières
Date / Time	Thursday 12 March 2020 / 14:00 - 15:30
Chair	Arnaud Virazel, Université de Montpellier / LIRMM, FR
Co-Chair	Lorena Anghel, University Grenoble-Alpes, FR

11.6.1 14:00 - 14:30	Impact of NBTI Aging on Self-Heating in Nanowire FET Om Prakash, Hussam Amrouch, Sanjeev Manhas and Jörg Henkel
11.6.2 14:30 - 15:00	PowerPlanningDL: Reliability-Aware Framework for On-Chip Power Grid Design using Deep Learning Sukanta Dey, Sukumar Nandi and Gaurav Trivedi
11.6.3 15:00 - 15:30	An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs Bo Hu, Mustafa Shihab, Yiorgos Makris, Benjamin Carrion Schaefer and Carl Sechen

Session Title	System Level Security
Session Code / Room	11.7 / Berlioz
Date / Time	Thursday 12 March 2020 / 14:00 - 15:30
Chair	Pascal Benoit, Université de Montpellier, FR
Co-Chair	David Hely, Unviversity Grenoble Alpes, FR

11.7.1 14:00 - 14:30	AMSA: Adaptive Merkle Signature Architecture Emanuel Regnath and Sebastian Steinhorst
11.7.2 14:30 - 15:00	DISSECT: Dynamic Skew-and-Split Tree for Memory Authentication Saru Vig, Rohan Juneja and Siew-Kei Lam
11.7.3 15:00 - 15:30	Design-flow Methodology for Secure Group Anonymous Authentication Rashmi Agrawal, Lake Bu, Eliakin Del Rosario and Michel A. Kinsy

Session Title	Special Session: Self-Aware, Biologically-Inspired Adaptive Hardware Systems for Ultimate Dependability and Longevity
Session Code / Room	11.8 / Exhibition Theatre
Date / Time	Thursday 12 March 2020 / 14:00 - 15:30
Chair	Martin A. Trefzer, University of York, UK
Co-Chair	Andy M. Tyrrell, University of York, UK

11.8.1 14:00 - 14:20	Embedded Social Insect-Inspired Intelligence Networks for System-level Runtime Management Matthew R. P. Rowlings, Andy M. Tyrrell and Martin A. Trefzer
11.8.2 14:20 - 14:40	Optimising Resource Management for Embedded Machine Learning Lei Xun, Long Tran-Thanh, Bashir M Al-Hashimi and Geoff V. Merrett
11.8.3 14:40 - 15:00	Emergent Control of MPSoC Operation by a Hierarchical Supervisor / Reinforcement Learning Approach Florian Maurer, Bryan Donyanavard, Amir M. Rahmani, Nikil Dutt and Andreas Herkersdorf
11.8.4 15:00 - 15:30	AstroByte: Multi-FPGA Architecture for Accelerated Simulations of Spiking Astrocyte Neural Networks Shvan Karim, Jim Harkin, Liam McDaid, Bryan Gardiner and Junxiu Liu

Session Title	Interactive Presentations
Session Code / Room	IP5 / Poster Area
Date / Time	Thursday 12 March 2020 / 15:30 - 16:00

IP5-1	Statistical Model Checking of Approximate Circuits: Challenges and Opportunities Josef Strnadel
IP5-2	Runtime Accuracy-Configurable Approximate Hardware Synthesis Using Logic Gating and Relaxation Tanfer Alan, Andreas Gerstlauer and Jörg Henkel
IP5-3	Post-Quantum Secure Boot Vinay B. Y. Kumar, Naina Gupta, Anupam Chattopadhyay, Michael Kasper, Christoph Krauß and Ruben Niederhagen
IP5-4	ROQ: A Noise-Aware Quantization Scheme Towards Robust Optical Neural Networks with Low-bit Controls Jiaqi Gu, Zheng Zhao, Chenghao Feng, Hanqing Zhu ,Ray T. Chen and David Z. Pan
IP5-5	Statistical Training for Neuromorphic Computing using Memristor-based Crossbars Considering Process Variations and Noise Ying Zhu, Grace Li Zhang, Tianchen Wang, Bing Li, Yiyu Shi, Tsung-Yi Ho and Ulf Schlichtmann
IP5-6	Computational Restructuring: Rethinking Image Processing using Memristor Crossbar Arrays Baogang Zhang, Necati Uysal and Rickard Ewetz
IP5-7	SCRIMP: A General Stochastic Computing Architecture using ReRAM in-Memory Processing Saransh Gupta, Mohsen Imani, Joonseop Sim, Andrew Huang, Fan Wu, M. Hassan Najafi and Tajana Rosing
IP5-8	TDO-CIM: Transparent Detection and Offloading for Computation In-memory Kanishkan Vadivel, Lorenzo Chelini, Ali BanaGozar, Gagandeep Singh, Stefano Corda, Roel Jordans and Henk Corporaal
IP5-9	BackFlow: Backward Edge Control Flow Enforcement for Low End ARM Microcontrollers Cyril Bresch, Roman Lysecky and David Hély
IP5-10	Delay Sensitivity Polynomials Based Design-Dependent Performance Monitors for Wide Operating Ranges Ruikai Shi, Liang Yang and Hao Wang
IP5-11	Mitigation of Sense Amplifier Degradation Using Skewed Design Daniël Kraak, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans and Francky Catthoor
IP5-12	Blockchain Technology Enabled Pay Per Use Licensing Approach for Hardware IPs Krishnendu Guha, Debasri Saha and Amlan Chakrabarti

Session Title	Special Day on "Silicon Photonics": Design Automation for Photonics
Session Code / Room	12.1 / Amphithéâtre Jean Prouve
Date / Time	Thursday 12 March 2020 / 16:00 - 17:30
Chair	Dave Penkler, SCINTIL Photonics, US
Co-Chair	Luca Ramini, Hewlett Packard Labs, US

12.1.1 16:00 - 16:30	Opportunities for Cross-Layer Design in High-Performance Computing Systems with Integrated Silicon Photonic Networks Asif Mirza, Shadi Manafi Avari, Ebadollah Taheri, Sudeep Pasricha and Mahdi Nikdast
12.1.2 16:30 - 17:00	Design and Validation of Photonic IP Macros Based On Foundry PDKS Ruping Cao
12.1.3 17:00 - 17:30	Efficient Optical Power Delivery System for Hybrid Electronic-Photonic Manycore Processors Shixi Chen, Jiang Xu, Xuanqi Chen, Zhifei Wang, Jun Feng, Jiaxu Zhang, Zhongyuan Tian and Xiao Li

Session Title	Autonomous Systems Design Initiative: Emerging Approaches to Autonomous Systems Design
Session Code / Room	12.2 / Chamrousse
Date / Time	Thursday 12 March 2020 / 16:00 - 17:30
Chair	Dirk Ziegenbein, Robert Bosch GmbH, DE
Co-Chair	Sebastian Steinhorst, TU Munich, DE

12.2.1 16:00 - 16:30	A Preliminary View on Automotive Cyber Security Management Systems Christoph Schmittner, Jrgen Dobaj, Georg Macher and Eugen Brenner
12.2.2 16:30 - 17:00	Towards Safety Verification of Direct Perception Neural Networks Chih-Hong Cheng, Chung-Hao Huang, Thomas Brunner and Vahid Hashemi
12.2.3 17:00 - 17:30	Minimizing Execution Duration in the Presence of Learning-Enabled Components Kunal Agrawal, Sanjoy Baruah, Alan Burns and Abhishek Singh

Session Title	Reconfigurable Systems for Machine Learning
Session Code / Room	12.3 / Autrans
Date / Time	Thursday 12 March 2020 / 16:00 - 17:30
Chair	Bogdan Pasca, Intel, FR
Co-Chair	Smail Niar, Université Polytechnique Hauts-de-France, FR

12.3.1 16:00 - 16:30	Exploration of Memory Access Optimization for FPGA-based 3D CNN Accelerator Teng Tian, Xi Jin, Letian Zhao, Xiaotian Wang, Jie Wang and Wei Wu
12.3.2 16:30 - 17:00	A Throughput-Latency Co-Optimised Cascade of Convolutional Neural Network Classifiers Alexandros Kouris, Stylianos I. Venieris and Christos-Savvas Bouganis
12.3.3 17:00 - 17:30	OrthrusPE: Runtime Reconfigurable Processing Elements for Binary Neural Networks Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein and Walter Stechele

Session Title	Approximate Computing Works! Applications & Case Studies
Session Code / Room	12.4 / Stendhal
Date / Time	Thursday 12 March 2020 / 16:00 - 17:30
Chair	Oliver Keszocze, Friedrich-Alexander-University Erlangen-Nuremberg (FAU), DE
Co-Chair	Benjamin Carrion Schaefer, University of Texas at Dallas, US

12.4.1 16:00 - 16:30	Towards Generic and Scalable Word-Length Optimization Van-Phu Ha, Tomofumi Yuki and Olivier Sentieys
12.4.2 16:30 - 17:00	Trading Sensitivity for Power in an IEEE 802.15.4 Conformant Adequate Demodulator Paul Detterer, Cumhur Erdin, Jos Huisken, Hailong Jiao, Majid Nabi, Twan Basten and José Pineda de Gyvez
12.4.3 17:00 - 17:30	Approximation Trade Offs in an Image-Based Control System Sayandip De, Sajid Mohamed, Konstantinos Bimpisidis, Dip Goswami, Twan Basten and Henk Corporaal

Session Title	Cyber-Physical Systems for Manufacturing and Transportation
Session Code / Room	12.5 / Bayard
Date / Time	Thursday 12 March 2020 / 16:00 - 17:30
Chair	Ulrike Thomas, Chemnitz University of Technology, DE
Co-Chair	Robert De Simone, INRIA, FR

12.5.1 16:00 - 16:30	CPS-oriented Modeling and Control of Traffic Signals Using Adaptive Back Pressure Wanli Chang, Debayan Roy, Shuai Zhao, Anuradha Annaswamy and Samarjit Chakraborty
12.5.2 16:30 - 17:00	Network Synthesis for Industry 4.0 Enrico Fraccaroli, Alan Michael Padovani, Davide Quaglia and Franco Fummi
12.5.3 17:00 - 17:15	Production Recipe Validation through Formalization and Digital Twin Generation Stefano Spellini, Roberta Chirico, Marco Panato, Michele Lora and Franco Fummi
12.5.4 17:15 - 17:30	Parallel Implementation of Iterative Learning Controllers on Multi-core Platforms Mojtaba Haghi, Yusheng Yao, Dip Goswami and Kees Goossens

Session Title	Industrial Experience: From Wafer-Level Up to IoT Security
Session Code / Room	12.6 / Lesdiguières
Date / Time	Thursday 12 March 2020 / 16:00 - 17:30
Chair	Enrico Macii, Politecnico di Torino, IT
Co-Chair	Norbert Wehn, TU Kaiserslautern, DE

12.6.1 16:00 - 16:15	Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Andrew Yi-Ann Huang, Ji-Wei Li, Leon Li-Yang Chen, Nova Cheng-Yen Tsai, Sying-Jyan Wang, Chen-Shiun Lee, Leon Chou, Peter Yi-Yu Liao, Hsing-Chung Liang and Jwu-E Chen
12.6.2 16:15 - 16:30	A Method of Via Variation Induced Delay Computation Moonsu Kim, Yun Heo, Seungjae Jung, Kelvin Le, Nathaniel Conos, Hanif Fatemi, Jongpil Lee and Youngmin Shin
12.6.3 16:30 - 16:45	Fully Automated Analog Sub-Circuit Clustering with Graph Convolutional Neural Networks Keertana Settaluri and Elias Fallon
12.6.4 16:45 - 17:00	EVPS: An Automotive Video Acquisition and Processing Platform Christophe Flouzat, Erwan Piriou, Mickaël Guibert, Bojan Jovanović and Mohamad Oussayran
12.6.5 17:00 - 17:15	An On-board Algorithm Implementation on an Embedded GPU: A Space Case Study Iván Rodriguez, Leonidas Kosmidis, Olivier Notebaert, Francisco J. Cazorla and David Steenari
12.6.6 17:15 - 17:30	TLS-Level Security for Low Power Industrial IoT Network Infrastructures Jochen Mades, Gerd Ebelt, Boris Janjic, Frederik Lauer, Carl C. Rheinländer and Norbert Wehn

Session Title	Power-Efficient Multi-Core Embedded Architectures
Session Code / Room	12.7 / Berlioz
Date / Time	Thursday 12 March 2020 / 16:00 - 17:30
Chair	Andreas Burg, EPFL, CH
Co-Chair	Semeen Rehman, TU Wien, AT

12.7.1 16:00 - 16:30	Tuning the ISA for increased heterogeneous computation in MPSoCs Pedro H. E. Becker, Jeckson D. Souza and Antonio C. S. Beck
12.7.2 16:30 - 17:00	User Interaction Aware Reinforcement Learning for Power and Thermal Efficiency of CPU-GPU Mobile MPSoCs Somdip Dey, Amit Kumar Singh, Xiaohang Wang and Klaus McDonald-Maier
12.7.3 17:00 - 17:30	Energy-Efficient Two-level Instruction Cache Design for an Ultra-Low-Power Multi-core Cluster Chen Jie, Igor Loi, Luca Benini and Davide Rossi

Session Title	Special Session: EDA Challenges in Monolithic 3D Integration: From Circuits to Systems
Session Code / Room	12.8 / Exhibition Theatre
Date / Time	Thursday 12 March 2020 / 16:00 - 17:30
Chair	Pascal Vivet, CEA-Leti, FR
Co-Chair	Mehdi Tahoori, Karlsruhe Institute of Technology, DE

12.8.1 16:00 - 16:30	M3D-ADTCO: Monolithic 3D Architecture, Design and Technology Co-Optimization for High Energy Efficient 3D IC Sebastien Thuries, Olivier Billoint, Sylvain Choisnet, Romain Lemaire, Pascal Vivet, Perrine Batude and Didier Lattard
12.8.2 16:30 - 17:00	Design of a Reliable Power Delivery Network for Monolithic 3D ICs Shao-Chun Hung and Krishnendu Chakrabarty
12.8.3 17:00 - 17:30	Power, Performance, and Thermal Trade-offs in M3D-enabled Manycore Chips Shouvik Musavvir, Anwesha Chatterjee, Ryan Gary Kim, Dae Hyun Kim, Janardhan Rao Doppa and Partha Pratim Pande