Testing Through Silicon Vias in Power Distribution Network of 3D-IC with Manufacturing Variability Cancellation
Koutaro Hachiyaa and Atsushi Kurokawab
1Faculty of Modern Life Teikyo Heisei University Tokyo, Japan
k.hachiya@thu.ac.jp
2Graduate School of Science and Technology Hirosaki University Hirosaki, Japan
kurokawa@eit.hirosaki-u.ac.jp
ABSTRACT
To detect open defects of power TSVs (Through Silicon Vias) in PDNs (Power Distribution Networks) of stacked 3DICs, a method was proposed which measures resistances between power micro-bumps connected to PDN and detects defects of TSVs by changes of the resistances. It suffers from manufacturing variabilities and must place one micro-bump directly under each TSV (direct-type placement style) to maximize its diagnostic performance, but the performance was not enough for practical applications. A variability cancellation method was also devised to improve the diagnostic performance. In this paper, a novel middle-type placement style is proposed which places one microbump between each pair of TSVs. Experimental simulations using a 3D-IC example show that the diagnostic performances of both the direct-type and the middle-type examples are improved by the variability cancellation and reach the practical level. The middletype example outperforms the direct-type example in terms of number of micro-bumps and number of measurements.
Keywords: Three Dimensional Integrated Circuits, Design for Testability, Through Silicon Via, Micro-Bump, Open Defect, Manufacturing Variability.
