An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays
Shruti R. Kulkarni1, Shihui Yin2, Jae-sun Seo2 and Bipin Rajendran3
1Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ 07102, USA.
2School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ 85287, USA.
3Department of Engineering, King's College London, Strand, London, WC2R 2LS, UK.
bipin.rajendran@kcl.ac.uk
ABSTRACT
In this work, we present a scheme for implementing learning on a digital non-volatile memory (NVM) based hardware accelerator for Spiking Neural Networks (SNNs). Our design estimates across three prominent non-volatile memories - Phase Change Memory (PCM), Resistive RAM (RRAM), and Spin Transfer Torque RAM (STT-RAM) show that the STT-RAM arrays enable at least 2× higher throughput compared to the other two memory technologies. We discuss the design and the signal communication framework through the STT-RAM crossbar array for training and inference in SNNs. Each STTRAM cell in the array stores a single bit value. Our neurosynaptic computational core consists of the memory crossbar array and its read/write peripheral circuitry and the digital logic for the spiking neurons, weight update computations, spike router, and decoder for incoming spike packets. Our STT-RAM based design shows ∼20× higher performance per unit Watt per unit area compared to conventional SRAM based design, making it a promising learning platform for realizing systems with significant area and power limitations.
Keywords: Neuromorphic hardware, Spiking Neural Networks, crossbar arrays, STT-RAM
