2DCC: Cache Compression in Two Dimensions
Amin Ghasemazar1,a, Mohammad Ewais2, Prashant Nair1,b and Mieszko Lis1,c
1University of British Columbia
aaming@ece.ubc.ca
bprashantnair@ece.ubc.ca
cmieszko@ece.ubc.ca
2University of Toronto
mewais@ece.utoronto.ca
ABSTRACT
The importance of caches for performance, and their high silicon area cost, have motivated hardware solutions that transparently compress the cached data to increase effective capacity without sacrificing silicon area. To this end, prior work has taken one of two approaches: either (a) deduplicating identical cache blocks across the cache to take advantage of interblock redundancy or (b) compressing common patterns within each cache block to take advantage of intra-block redundancy.
In this paper, we demonstrate that leveraging only one of these redundancy types leads to a significant loss in compression opportunities for several applications: some workloads exhibit either inter-block or intra-block redundancy, while others exhibit both. We propose 2DCC (Two Dimensional Cache Compression), a simple technique that takes advantage of both types of redundancy. Across the SPEC and Parsec benchmark suites, 2DCC results in a 2.12× compression factor (geomean) compared to 1.44–1.49× for best prior techniques on an iso-silicon basis. For the cache-sensitive subset of these benchmarks run in isolation, 2DCC also achieves a 11.7% speedup (geomean).
