WCET-aware Code Generation and Communication Optimization for Parallelizing Compilers
Simon Redera and Jürgen Beckerb
Karlsruhe Institute of Technology (KIT) Karlsruhe, Germany
asimon.reder@kit.edu
bbecker@kit.edu
ABSTRACT
High performance demands of present and future embedded applications increase the need for multi-core processors in hard real-time systems. Challenges in static multicore WCET-analysis and the more complex design of parallel software, however, oppose the adoption of multi-core processors in that area. Automated parallelization is a promising approach to solve these issues, but specialized solutions are required to preserve static analyzability. With a WCET-aware parallelizing transformation, this work presents a novel solution for an important building block of a real-time capable parallelizing compiler.The approach includes a technique to optimize communication and synchronization in the parallelized program and supports complex memory hierarchies consisting of both shared and coreprivate memory segments. In an experiment with four different applications, the parallelization improved the WCET by up to factor 3.2 on 4 cores. The studied optimization technique and the support for shared memories significantly contribute to these results.
Keywords: Real-Time, Multi-Core, Compiler Tools, WCET
