A Novel TIGFET-based DFF Design for Improved Resilience to Power Side-Channel Attacks

Mohammad Mehdi Sharifi1, Ramin Rajaei1, Patsy Cadareanu2, Pierre-Emmanuel Gaillardon2, Yier Jin3, Michael Niemier1 and X. Sharon Hu1
1Department of Computer Science and Engineering, University of Notre Dame, USA
2Department of Electrical and Computer Engineering, The University of Utah, USA
3Department of Electrical and Computer Engineering, University of Florida, USA

ABSTRACT


Side-channel attacks (SCAs) represent a significant security threat, and aim to reveal otherwise secret data by ana-lyzing a relevant circuit's behavior, e.g., its power consumption. While all circuit components are potential power side channels, D-flip-flops (DFFs) are often the primary source of information leakage to an SCA. This paper proposes a DFF design based on the three-independent-gate field-effect transistor (TIGFET) that reduces side-channel vulnerabilities of sequential circuits. Notably, we find that the I-V characteristics of the TIGFET itself leads to inherent side-channel resilience, which in turn enables simpler and more efficient cryptographic hardware. Our pro-posed design is based on a prior TIGFET-based true single-phase clock (TSPC) DFF design, which offers high performance and reduced area. More specifically, our modified TSPC (mTSPC) design exploits the symmetric I-V characteristics of TIGFETs, which results in pull-up and pull-down currents that are nearly identical. When combined with additional circuit modifications (made possible by the unique characteristics of the TIGFET), the mTSPC circuit draws almost the same amount of supply currents under all possible input transitions (less than 1% variation for different transitions), which can in turn mask information leakage. Using a lOnm TIGFET technology model, simulation results show that the proposed TIGFET-based DFF circuit leads to decreased power consumption (up to 96.9% when compared to the prior secured designs), has a low delay (15.2 ps), and employs only 12 TIGFET devices. Furthermore, an 8-bit S-box whose output is sampled by a group of eight mTSPC DFFs was simulated. A correlation power analysis attack on the simulated S-box with 256 power traces shows that the key is not revealed, which confirms the SCA resiliency of the proposed DFF design.

Keywords: Three-independent-gate FET (TIGFET), Side-channel attack (SCA), Correlation power analysis (CPA) attack, True single-phase clock D-flip-flop (TSPC DFF).



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