GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits
Kishor Kunal1, Tonmoy Dhar1, Meghna Madhusudan1, Jitesh Poojary1, Arvind Sharma1, Wenbin Xu2, Steven M. Burns3, Jiang Hu2, Ramesh Harjani1 and Sachin S. Sapatnekar1
1University of Minnesota, Minneapolis, MN
2Texas A&M University, College Station, TX
3Intel Corporation, Hillsboro, OR
ABSTRACT
Automated subcircuit identification and annotation enables the creation of hierarchical representations of analog netlists, and can facilitate a variety of design automation tasks such as circuit layout and optimization. Subcircuit identification must navigate the numerous alternative structures that can implement any analog function, but traditional graph-based methods cannot easily identify the large number of such structural variants. The novel approach in this paper is based on the use of a trained graph convolutional neural network (GCN) that identifies netlist elements for circuit blocks at upper levels of the design hierarchy. Structures at lower levels of hierarchy are identified using graph-based algorithms. The proposed recognition scheme organically detects layout constraints, such as symmetry and matching, whose identification is essential for high-quality hierarchical layout. The subcircuit identification method demonstrates a high degree of accuracy over a wide range of analog designs, successfully identifies larger circuits that contain subblocks such as OTAs, LNAs, mixers, oscillators, and band-pass filters, and provides hierarchical decompositions of such circuits.
