An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs
Bo Hua, Mustafa Shihabb, Yiorgos Makrisc, Benjamin Carrion Schaeferd and Carl Sechene
Department of Electrical & Computer Engineering, The University of Texas at Dallas
abo.hu@utdallas.edu
bmustafa.shihab@utdallas.edu
cyiorgos.makris@utdallas.edu
dschaferb@utdallas.edu
ecarl.sechen@utdallas.edu
ABSTRACT
Shrinking transistor sizes are jeopardizing the reliability of runtime reconfigurable Field Programmable Gate Arrays (FPGAs), making them increasingly sensitive to aging effects such as Negative Bias Temperature Instability (NBTI). This paper introduces a reliability-aware floorplanner which is tailored to multi-context, coarse-grained, runtime reconfigurable architectures (CGRRAs) and seeks to extend their Mean Time to Failure (MTTF) by balancing the usage of processing elements (PEs). The proposed method is based on a Mixed Integer Linear Programming (MILP) formulation, the solution to which produces appropriately-balanced mappings of workload to PEs on the reconfigurable fabric, thereby mitigating aging-induced lifetime degradation. Results demonstrate that, as compared to the default reliability-unaware floorplanning solutions, the proposed method achieves an average MTTF increase of 2.5× without introducing any performance degradation.
