A Universal Spintronic Technology based on Multifunctional Standardized Stack
M. Tahoori1, S.M. Nair1, R. Bishnoi1, L. Torres2, S. Senni2, G. Patrigeon2, P. Benoit2, G. Di Pendina3 and G. Prenat3
1Karlsruhe Institute of Technology, Karlsruhe, Germany
2LIRMM, UMR CNRS 5506, University of Montpellier, France
3Univ. Grenoble Alpes, CNRS, CEA, INAC-SPINTEC, F-38000 Grenoble, France
ABSTRACT
The goal of the GREAT RIA project is to cointegrate multiple functions like sensors (“Sensing”), RF emitters or receivers (“Communicating”) and logic/memory (“Processing/ Storing”) together within CMOS technology by adapting the Spin-Transfer Torque Magnetic Tunnel Junction (STT-MTJ), elementary constitutive cell of the MRAM memories, to a single baseline technology. Based on the STT unique set of performances (non-volatility, high speed, infinite endurance and moderate read/write power), GREAT will achieve the same goal as heterogeneous integration of devices but in a much simpler way. This will lead to a unique STT-MTJ cell technology called Multifunctional Standardized Stack (MSS). This paper presents the lessons learned in the project from the technology, compact modeling, process design kit, standard cells, as well as memory and system level design evaluation and exploration. The proposed technology and toolsets are giant leaps towards heterogeneous integrated technology and architectures for IoT.
