Modeling and Designing of a PVT Auto-tracking Timing-speculative SRAM
Shan Shena, Tianxiang Shaob, Ming Lingc, Jun Yangd and Longxing Shie
Nation ASIC System Engineering Technology Research Center Southeast University Nanjing, China
ashanshen@seu.edu.cn
btxshao@seu.edu.cn
ctrio@seu.edu.cn
ddragon@seu.edu.cn
elxshi@seu.edu.cn
ABSTRACT
In the low supply voltage region, the performance of 6T cell SRAM degrades seriously, which takes more time to achieve the sufficient voltage difference on bitlines. Timingspeculative techniques are proposed to boost the SRAM frequency and the throughput with speculatively reading data in an aggressive timing and correcting timing failures in one or more extended cycles. However, the throughput gains of timingspeculative SRAM are affected by the process, voltage and temperature (PVT) variations, which causes the timing design of speculative SRAM to be either too aggressive or too conservative.
This paper first proposes a statistical model to abstract the characteristics of speculative SRAM and shows the presence of an optimal sensing time that maximizes the overall throughput. Then, with the guidance of the performance model, a PVT auto-tracking speculative SRAM is designed and fabricated, which can dynamically self-tune the bitline sensing to the optimal time as the working condition changes. According to the measurement results, the maximum throughput gain of the proposed 28nm SRAM is 1.62X compared to the baseline at 0.6V VDD.
Keywords: Timing-speculation, SRAM, low-power design, performance model, PVT.
