A Timing Uncertainty-Aware Clock Tree Topology Generation Algorithm for Single Flux Quantum Circuits
Soheil Nazar Shahsavania, Bo Zhangb and Massoud Pedramc
Department of Electrical and Computer Engineering, University of Southern California, Los Angeles, CA, USA
anazarsha@usc.edu
bzhan254@usc.edu
cpedram@usc.edu
ABSTRACT
This paper presents a low-cost, timing uncertainty-aware synchronous clock tree topology generation algorithm for single flux quantum (SFQ) logic circuits. The proposed method considers the criticality of the data paths in terms of timing slacks as well as the total wirelength of the clock tree and generates a (height-) balanced binary clock tree using a bottom-up approach and an integer linear programming (ILP) formulation. The statistical timing analysis results for ten benchmark circuits show that the proposed method improves the total wirelength and the total negative hold slack by 4:2% and 64:6%, respectively, on average, compared with a wirelength-driven state-of-theart balanced topology generation approach.
Keywords: Single Flux Quantum, Clock Tree Synthesis, Clock Topology Generation, Timing Uncertainty, Mathematical Programming
