On Pre-Assignment Route Prototyping for Irregular Bumps on BGA Packages
Jyun-Ru Jiang1,a, Yun-Chih Kuo1,b, Simon Yi-Hung Chen2 and Hung-Ming Chen1,c
1Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
ap57l63p9c69@gmail.com
bEric-YC.Kuo@mediatek.com
chmchen@mail.nctu.edu.tw
2MediaTek Inc., Taiwan
simonYH.Chen@mediatek.com
ABSTRACT
In modern package design, the bumps often place irregularly due to the macros varied in sizes and positions. This will make pre-assignment routing more difficult, even with massive design efforts. This work presents a 2-stage routing method which can be applied to an arbitrary bump placement on 2-layer BGA packages. Our approach combines escape routing with via assignment: the escape routing is used to handle the irregular bumps and the via assignment is applied for improving the wire congestion and total wirelength of global routing. Experimental results based on industrial cases show that our methodology can solve the routing efficiently, and we have achieved 82% improvement on wire congestion with 5% wirelength increase compared with conventional regular treatments.
