Energy Optimization in NCFET-based Processors
Sami Salamin1,a, Martin Rapp1,b, Hussam Amrouch1,c, Andreas Gerstlauer2 and Jörg Henkel1,d
1Chair of Embedded Systems (CES), Karlsruhe Institute of Technology, Karlsruhe, Germany
asami.salamin@kit.edu
bmartin.rapp@kit.edu
camrouch@kit.edu
dhenkel@kit.edu
2Department of Electrical and Computer Engineering, University of Texas, Austin, USA
gerstl@ece.utexas.edu
ABSTRACT
Energy consumption is a key optimization goal for all modern processors. Negative Capacitance Field-Effect Transistors (NCFETs) are a leading emerging technology that promises outstanding performance in addition to better energy efficiency. Thickness of the additional ferroelectric layer, frequency, and voltage are the key parameters in NCFET technology that impact the power and frequency of processors. However, their joint impact on energy optimization has not been investigated yet.
In this work, we are the first to demonstrate that conventional (i.e., NCFET-unaware) dynamic voltage/frequency scaling (DVFS) techniques to minimize energy are sub-optimal when applied to NCFET-based processors. We further demonstrate that state-of-the-art NCFET-aware voltage scaling for power minimization is also sub-optimal when it comes to energy. This work provides the first NCFET-aware DVFS technique that optimizes the processor’s energy through optimal runtime frequency/ voltage selection. In NCFETs, energy-optimal frequency and voltage are dependent on the workload and technology parameters. Our NCFET-aware DVFS technique considers these effects to perform optimal voltage/frequency selection at runtime depending on workload characteristics. Results show up to 90% energy savings compared to conventional DVFS techniques. Compared to state-of-the-art NCFET-aware power management, our technique provides up to 72% energy savings along with 3:7× higher performance.
