CNT-Cache: an Energy-Efficient Carbon Nanotube Cache with Adaptive Encoding
Dawen Xu1,2,a, Kexin Chu1,2, Cheng Liu2,b, Ying Wang2, Lei Zhang2 and Huawei Lie1
1School of Electronic Science & Applied Physics Hefei University of Technology Anhui,China
2Institute of Computing Technology, Chinese Academy of Sciences,Beijing,China
alchukexin2017@mail.hfut.edu.cn
bliucheng@ict.ac.cn
ABSTRACT
Carbon Nanotubu field-effect transistor (CNFET) that promises both higher clock speed and energy efficiency becomes an attractive alternative to the conventional power-hungry CMOS cache. We observe that the CNFET-based cache constructed with typical SRAM cells has distinct energy consumption when reading/writing 0 and 1 from/to it. For instance, the energy consumption of writing 1 to an SRAM cell is almost 10X higher than writing 0. With this observation, we propose an energy-efficient cache design called CNT-Cache to take advantage of this feature. It predicts the cache line access pattern based on the latest cache line access history. On top of the prediction, it decides the optimal cache line encoding to match the cache operation preferences at runtime. According to our experiments on a set of benchmark programs, the optimized CNFET-based D-Cache reduces the dynamic power consumption by 22.2% on average compared to the baseline CNFET cache.
