A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs
Guilherme Cardoso Medeiros1,a, Cemil Cem Gürsoy2,f, Lizhou Wu1,c, Moritz Fieback1,b, Maksim Jenihhin2,g, Mottaqiallah Taouil1,d and Said Hamdioui1,e
1Computer Engineering Laboratory, Delft University of Technology, The Netherlands
aG.CardosoMedeiros@tudelft.nl
bM.C.R.Fieback@tudelft.nl
cLizhou.Wu@tudelft.nl
dM.Taouil@tudelft.nl
eS.Hamdioui@tudelft.nl
2Department of Computer Systems, Tallinn University of Technology, Estonia
fCemil.Gursoy@taltech.ee
gMaksim.Jenihhin@taltech.ee
ABSTRACT
Manufacturing defects can cause faults in FinFET SRAMs. Of them, easy-to-detect (ETD) faults always cause incorrect behavior, and therefore are easily detected by applying sequences of write and read operations. However, hard-to-detect (HTD) faults may not cause incorrect behavior, only parametric deviations. Detection of these faults is of major importance as they may lead to test escapes. This paper proposes a new designfor- testability (DFT) scheme for FinFET SRAMs to detect such faults by creating a mismatch in the sense amplifier (SA). This mismatch, combined with the defect in the cell, will incorrectly bias the SA and cause incorrect read outputs. Furthermore, postsilicon calibration schemes can be used to avoid over-testing or test escapes caused by process variation effects. Compared to the state of the art, this scheme introduces negligible overheads in area and test time while it significantly improves fault coverage and reduces the number of test escapes.
Keywords: FinFET, SRAM, Hard-to-Detect Faults, Defects, DFT, Memory Testing.
