Unified Thread- and Data-Mapping for Multi-Threaded Multi-Phase Applications on SPM Many-Cores
Vanchinathan Venkataramania, Anuj Pathaniab and Tulika Mitrac
National University of Singapore
avvanchi@comp.nus.edu.sg
bpathania@comp.nus.edu.sg
ctulika@comp.nus.edu.sg
ABSTRACT
Scratchpad Memories (SPMs) are more scalable than caches as they offer better performance with lower power and area overheads. This scalability advocates their suitability as on-chip memory in many-cores. However, SPM many-cores delegate the responsibility of thread- and data-mapping to the software. The mapping is especially challenging in the case of multi-threaded multi-phase applications. Threads from these applications exhibit both inter- and intra-phase data-sharing patterns. These patterns intricately intertwine thread- and datamapping across phases. The accompanying qualitative mapping is the key to extract application performance on SPM many-cores. State-of-the-art framework for SPM many-cores performs thread- and data-mapping independently. Furthermore, it can only operate with single-phase multi-threaded applications. We are the first to propose in this work, a unified thread- and data-mapping framework for NoC-based SPM many-cores when executing multi-threaded multi-phase applications. Experimental evaluations show, on average, 1.36x performance improvement compared to the state-of-the-art framework for multi-threaded multi-phase applications.
Keywords: SPM, many-core, Low-power, Task mapping.
