Power, Performance, and Thermal Trade-offs in M3D-enabled Manycore Chips
Shouvik Musavvir1,a, Anwesha Chatterjee1,b, Ryan Gary Kim2, Dae Hyun Kim1,c, Janardhan Rao Doppa1,d and Partha Pratim Pande1,e
1School of EECS, Washington State University Pullman, WA, 99164, U.S.A.
ashouvik.musavvir@wsu.edu
banwesha.chatterjee@wsu.edu
cdaehyun.kim@wsu.edu
djana.doppa@wsu.edu
epande@wsu.edu
2Department of Electrical and Computer Engineering, Colorado State University Fort Collins, CO, 80524, USA
Ryan.G.Kim@colostate.edu
ABSTRACT
Monolithic 3D (M3D) technology enables unprecedented degrees of integration on a single chip. The miniscule monolithic inter-tier vias (MIVs) in M3D are the key behind higher transistor density and more flexibility in designing circuits compared to conventional through silicon via (TSV)-based architectures. This results in significant performance and energy-efficiency improvements in M3D-based systems. Moreover, the thin inter-layer dielectric (ILD) used in M3D provides better thermal conductivity compared to TSV-based solutions and eliminates the possibility of thermal hotspots. However, the fabrication of M3D circuits still suffers from several non-ideal effects. The thin ILD layer may cause electrostatic coupling between tiers. Furthermore, the low-temperature annealing degrades the top-tier transistors and bottom-tier interconnects. An NoC-based manycore design needs to consider all these M3D-process related non-idealities. In this paper, we discuss various design challenges for an M3D-enabled manycore chip. We present the power-performance-thermal trade-offs associated with these emerging manycore architectures.
Keywords: Monolithic 3D, Manycore system, NoC, Electrostatic Coupling, Process variation, Thermal hotspots.
