Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis
Ken Chau-Cheung Cheng1, Katherine Shu-Min Li2, Andrew Yi-Ann Huang1, Ji-Wei Li1, Leon Li-Yang Chen2, Nova Cheng-Yen Tsai1, Sying-Jyan Wang3, Chen-Shiun Lee1, Leon Chou1, Peter Yi-Yu Liao1, Hsing-Chung Liang4 and Jwu-E Chen5
1Department of Wafer Test, NXP Semiconductors Taiwan Ltd., Kaohsiung, Taiwan
2Department of Computer Science and Engineering, National Sun Yat-Sen University Kaohsiung, Taiwan
3Department of Computer Science and Engineering, National Chung Hsing University, Taichung, Taiwan
4Department of Electronic Engineering, Chung Yuan Christian University, Chungli, Taiwan
5Department of Electrical Engineering, National Central University, Chungli, Taiwan
ABSTRACT
Wafer defect maps provide precious information of fabrication and test process defects, so they can be used as valuable sources to improve fabrication and test yield. This paper applies artificial intelligence based pattern recognition techniques to distinguish fab-induced defects from test-induced ones. As a result, test quality, reliability and yield could be improved accordingly. Wafer test data contain site-dependent information regarding test configurations in automatic test equipment, including effective load push force, gap between probe and load-board, probe tip size, probe-cleaning stress, etc. Our method analyzes both the test paths and site-dependent test characteristics to identify test-induced defects. Experimental results achieve 96.83% prediction accuracy of six NXP products, which show that our methods are both effective and efficient.
Keywords: Wafer Test, Wafer Defect Map, Test-Induced Defects, Test Path Recognition, Test Yield.
