ASCELLA: Accelerating Sparse Computation by Enabling Stream Accesses to Memory
Bahar Asgaria, Ramyad Hadidib and Hyesoon Kimc
Georgia Institute of Technology, Atlanta, GA
abahar.asgari@gatech.edu
brhadidi@gatech.edu
chyesoon.kim@gatech.edu
ABSTRACT
Sparse computations dominate a wide range of applications from scientific problems to graph analytics. The main characterization of sparse computations, indirect memory accesses, prevents them from effectively achieving high performance on general-purpose processors. Therefore, hardware accelerators have been proposed for sparse problems. For these accelerators, the storage format and the decompression mechanism is crucial but have seen less attention in prior work. To address this gap, we propose Ascella, an accelerator for sparse computations, which besides enabling a smooth stream of data and parallel computation, proposes a fast decompression mechanism. Our implementation on a ZYNQ FPGA shows that on average, Ascella executes sparse problems up to 5.1x as fast as prior work.
Keywords: Sparse, Stream Memory Access, FPGA.
