Maximizing Yield for Approximate Integrated Circuits
Marcello Traiola1,a, Arnaud Virazel1,b, Patrick Girard1,c, Mario Barbareschi2 and Alberto Bosio3
1LIRMM - University of Montpellier / CNRS - France
aMarcello.Traiola@lirmm.fr
bArnaud.Virazel@lirmm.fr
cPatrick.Girard@lirmm.fr
2DIETI - University of Naples Federico II - Italy
mario.barbareschi@unina.it
3Lyon Institute of Nanotechnology (INL), École Centrale de Lyon, France
alberto.bosio@ec-lyon.fr
ABSTRACT
Approximate Integrated Circuits (AxICs) have emerged in the last decade as an outcome of Approximate Computing (AxC) paradigm. AxC focuses on efficiency of computing systems by sacrificing some computation quality. As AxICs spread, consequent challenges to test them arose. On the other hand, the opportunity to increase the production yield merged in the AxIC context. Indeed, some particular defects in the manufactured AxIC might not catastrophically impact the final circuit quality. Therefore, some defective AxICs might still be acceptable. Efforts to detect favorable conditions to consider defective AxICs as acceptable – with the goal to increase the production yield – have been done in last years. Unfortunately, the final achieved yield gain is often not as high as expected. In this work, we propose a methodology to actually achieve a yield gain as close as possible to expectations, by proposing a technique to suitably apply tests to AxICs. Experiments carried out on state-of-the-art AxICs show yield gain results very close to the expected ones (i.e., between 98% and 100% of the expectations).
Keywords: Approximate Computing, Approximate Circuits, Testing, Signature analysis.
