DATE 2020 Best Papers 
| • The DATE 2020 Best Papers | • Best Paper Award Nominations |
DATE Best Paper Awards
Each year the Design, Automation and Test in Europe Conference presents awards to the authors of the best papers. The selection is performed by the award committee composed of the Track Chairs Cristiana Bolchini, Theocharis Theocharides, Jaume Abella and Valeria Bertacco and the following members: Borzoo Bonakdarpour, Andrea Calimera, Ramon Canal, Luca Carloni, Alessandro Cimatti, Ayse Coskun, Nikil Dutt, Ioannis Papaefstathiou, Dionisios Pnevmatikatos, Davide Quaglia, Muhammad Shafique, Olivier Sentieys, Luis Miguel Silveira, Juergen Teich, Vasileios Tenentes, Jerzy Tyszer, Arnaud Virazel
The DATE 2020 best papers are:
D Track
Impact of Magnetic Coupling and Density on STT-MRAM Performance
Lizhou Wu1, Siddharth Rao2, Mottaqiallah Taouil1, Erik Jan Marinissen1, Gouri Sankar Kar2 and Said Hamdioui1
1Delft University of Technology, 2IMEC
A Track
A Flexible and Scalable NTT Hardware: Applications from Homomorphically Encrypted Deep Learning to Post-Quantum Cryptography
Ahmet Can Mert1, Emre Karabulut2, Erdinc Ozturk1, Erkay Savas1,
Michela Becchi2 and Aydin Aysu2
1Sabanci University, 2North Carolina State University
T Track
DEFCON: Generating and Detecting Failure-prone Instruction Sequences via Stochastic Search
Ioannis Tsiokanos1, Lev Mukhanov2, Giorgis Georgakoudis3,
Dimitrios S. Nikolopoulos4 and Georgios Karakonstantis1
1Queen's University Belfast, 2QUB, 3Lawrence Livermore National Laboratory, 4Virginia Tech
E Track
Statistical Time-based Intrusion Detection in Embedded Systems
Nadir Carreon Rascon, Allison Gilbreath and Roman Lysecky
University of Arizona
D Track
Fast and Accurate DRAM Simulation: Can we Further Accelerate it?
Johannes Feldmann1, Matthias Jung2, Kira Kraft1, Lukas Steiner1 and Norbert Wehn1
1TU Kaiserslautern, 2Fraunhofer IESE
ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning
Davide Giri, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani and Luca Carloni
Columbia University
Verification Runtime Analysis: Get the Most Out of Partial Verification
Martin Ring1, Fritjof Bornbebusch1, Christoph Lüth1,2, Robert Wille3 and Rolf Drechsler1,2
1DFKI, 2University of Bremen, 3Johannes Kepler University Linz
Gap-free Processor Verification by S2QED and Property Generation
Keerthikumara Devarajegowda1, Mohammad Rahmani Fadiheh2, Eshan Singh3, Clark Barrett3, Subhasish Mitra3, Wolfgang Ecker1, Dominik Stoffel2 and Wolfgang Kunz2
1Infineon Technologies, 2TU Kaiserslautern, 3Stanford University
GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits
Kishor Kunal1, Tonmoy Dhar1, Meghna Madhusudan1, Jitesh Poojary1, Arvind Sharma1, Wenbin Xu2, Steven Burns3, Jiang Hu2, Ramesh Harjani1 and Sachin S. Sapatnekar1
1University of Minnesota, 2Texas A&M University, 3Intel Corporation
Backtracking Search for Optimal Parameters of a PLL-based True Random Number Generator
Brice Colombier, Nathalie Bochard, Florent Bernard and Lilian Bossuet
University of Lyon
GRAMARCH: A GPU-ReRAM based Heterogeneous Architecture for Neural Image Segmentation
Biresh Kumar Joardar1, Nitthilan Kannappan Jayakodi1, Jana Doppa1, Partha Pratim Pande1, Hai (Helen) Li2 and Krishnendu Chakrabarty3
1Washington State University, 2Duke University/TUM-IAS, 3Duke University
PSB-RNN: A Processing-in-Memory Systolic Array Architecture using Block Circulant Matrices for Recurrent Neural Networks
Nagadastagiri1, Sahithi Rampalli1, Makesh Tarun Chandran1, Gurpreet Singh Kalsi2, John (Jack) Sampson1, Sreenivas Subramoney2 and Vijaykrishnan Narayanan1
1The Pennsylvania State University, 2Processor Architecture Research Lab, Intel Labs
A Learning-Based Thermal Simulation Framework for Emerging Two-Phase Cooling Technologies
Zihao Yuan1, Geoffrey Vaartstra2, Prachi Shukla1, Zhengmao Lu2 Evelyn Wang2, Sherief Reda3 and Ayse Coskun1
1Boston University, 2Massachusetts Institute of Technology, 3Brown University
ProxSim: Simulation Framework for Cross-Layer Approximate DNN Optimization
Cecilia De la Parra1, Andre Guntoro1 and Akash Kumar2
1Robert Bosch GmbH, 2TU Dresden
A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs
Ankita Nayak, Keyi Zhang, Raj Setaluri, Alex Carsello, Makai Mann, Stephen Richardson, Rick Bahr, Pat Hanrahan, Mark Horowitz and Priyanka Raina
Stanford University
Floating Random Walk Based Capacitance Solver for VLSI Structures with Non-Stratified Dielectrics
Mingye Song, Ming Yang and Wenjian Yu
Tsinghua University
Ternary Compute-Enabled Memory based on Ferroelectric Transistors for Accelerating Deep Neural Networks
Sandeep Krishna Thirumala, Shubham Jain, Sumeet Gupta and Anand Raghunathan
Purdue University
Impact of Magnetic Coupling and Density on STT-MRAM Performance
Lizhou Wu1, Siddharth Rao2, Mottaqiallah Taouil1 Erik Jan Marinissen2 Gouri Sankar Kar2 Said Hamdioui1
1Delft University of Technology, 2IMEC
A Track
GenieHD: Efficient DNA Pattern Matching Accelerator Using Hyperdimensional Computing
Yeseong Kim, Mohsen Imani, Niema Moshiri, Tajana Rosing
University of California San Diego
Achieving Determinism in Adaptive AUTOSAR
Christian Menard1, Andres Goens1, Marten Lohstroh2 and Jeronimo Castrillon1
1TU Dresden, 2University of California, Berkeley
A Flexible and Scalable NTT Hardware: Applications from Homomorphically Encrypted Deep Learning to Post-Quantum Cryptography
Ahmet Can Mert1, Emre Karabulut2 Erdinc Ozturk1, Erkay Savas1, Michela Becchi2 and Aydin Aysu2
1Sabanci University, 2North Carolina State University
AntiDOte: Attention-based Dynamic Optimization for Neural Network Runtime Efficiency
Fuxun Yu1, Chenchen Liu2, Di Wang3, Yanzhi Wang1 and Xiang Chen1
1George Mason University, 2University of Maryland, 3Microsoft
Go Unary: A Novel Synapse Coding and Mapping Scheme for Reliable ReRAM-based Neuromorphic Computing
Chang Ma, Yanan Sun, Weikang Qian, Ziqi Meng, Rui Yang and Li Jiang
Shanghai Jiao Tong University
T Track
On Improving Fault Tolerance of Memristor Crossbar Based Neural Network Designs by Target Sparsifying
Song Jin1, Songwei Pei2, Yu Wang1
1North China Electric Power University, 2Beijing University of Posts and Telecommunications
Synthesis of Fault-Tolerant Reconfigurable Scan Networks
Sebastian Brandhofer, Michael Kochte and Hans-Joachim Wunderlich
University of Stuttgart
DEFCON: Generating and Detecting Failure-prone Instruction Sequences via Stochastic Search
Ioannis Tsiokanos1, Lev Mukhanov2, Giorgis Georgakoudis3, Dimitrios S. Nikolopoulos4 and Georgios Karakonstantis1
1Queen's University Belfast, 2QUB, 3Lawrence Livermore National Laboratory, 4Virginia Tech
Thermal-Cycling-aware Dynamic Reliability Management in Many-Core System-on-Chip
Mohammad-Hashem Haghbayan1, Antonio Miele2, Zhuo Zou3, Hannu Tenhunen1 and Juha Plosila1
1University of Turku, 2Politecnico di Milano, 3Nanjing University of Computer Science and Technology
E Track
Deeper Weight Pruning without Accuracy Loss in Deep Neural Networks
Byungmin Ahn and Taewhan Kim
Seoul National University
ACOUSTIC: Accelerating Convolutional Neural Networks through Or-Unipolar Skipped Stochastic Computing
Wojciech Romaszkan, Tianmu Li, Tristan Melton, Sudhakar Pamarti and Puneet Gupta
University of California Los Angeles
Statistical Time-based Intrusion Detection in Embedded Systems
Nadir Carreon Rascon, Allison Gilbreath and Roman Lysecky
University of Arizona
Energy-efficient runtime resource management for adaptable multi-application mapping
Robert Khasanov and Jeronimo Castrillon
TU Dresden
CPS-oriented Modeling and Control of Traffic Signals Using Adaptive Back Pressure
Wanli Chang1, Debayan Roy2, Shuai Zhao1, Anuradha Annaswamy3 and Samarjit Chakraborty2
1University of York, 2Technical University of Munich, 3Massachusetts Institute of Technology