Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities
Valentin Gherman1, Samuel Evain1 and Bastien Giraud2
1Paris-Saclay Campus, Nano-INNOV 91191 Gif sur Yvette, France
2CEA-Leti, Minatec Campus Grenoble, France
ABSTRACT
Many memory types are asymmetric with respect to the error vulnerability of stored 0’s and 1’s. For instance, DRAM, STT-MRAM and NAND flash memories may suffer from asymmetric error rates. A recently proposed error protection scheme consists in the inversion of the memory words with too many vulnerable values before they are stored in an asymmetric memory. In this paper, a method is proposed for the optimization of systematic binary linear block error-correcting codes in order to maximize their impact when combined with memory word inversion.
Keywords: Memory Word Inversion, Asymmetric Error Rates.
