MiniDelay: Multi-Strategy Timing-Aware Layer Assignment for Advanced Technology Nodes
Xinghai Zhang1, Zhen Zhuang1, Genggeng Liu1, Xing Huang2, Wen-Hao Liu3, Wenzhong Guo1,a and Ting-Chi Wang2
1College of Mathematics and Computer Science, Fuzhou University, Fuzhou, China
2Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan
3Block Implementation, ICD, Cadence Design Systems, Austin, TX, USA
aguowenzhong@fzu.edu.cn
ABSTRACT
Layer assignment, a major step in global routing of integrated circuits, is usually performed to assign segments of nets to multiple layers. Besides the traditional optimization goals such as overflow and via count, interconnect delay plays an important role in determining chip performance and has been attracting much attention in recent years. Accordingly, in this paper, we propose MiniDelay, a timing-aware layer assignment algorithm to minimize delay for advanced technology nodes, taking both wire congestion and coupling effect into account. MiniDelay consists of the following three key techniques: 1) a non-default-rule routing technique is adopted to reduce the delay of timing critical nets, 2) an effective congestion assessment method is proposed to optimize delay of nets and via count simultaneously, and 3) a net scalpel technique is proposed to further reduce the maximum delay of nets, so that the chip performance can be improved in a global manner. Experimental results on multiple benchmarks confirm that the proposed algorithm leads to lower delay and few vias, while achieving the best solution quality among the existing algorithms with the shortest runtime.
Keywords: Layer Assignment, Delay, Non-Default-Rule Wires, Congestion, Via
