M3D-ADTCO: Monolithic 3D Architecture, Design and Technology Co-Optimization for High Energy Efficient 3D IC
Sebastien Thuriesa, Olivier Billointb, Sylvain Choisnetc, Romain Lemaired, Pascal Vivete, Perrine Batudef and Didier Lattardg
Université Grenoble Alpes - CEA-Leti MINATEC Campus
aSebastien.Thuries@cea.fr
bOlivier.Billoint@cea.fr
cSylvain.Choisnet@cea.fr
dRomain.Lemaire@cea.fr
ePascal.Vivet@cea.fr
fPerrine.Batude@cea.fr
gDidier.Lattard@cea.fr
ABSTRACT
Monolithic 3D (M3D) stands now as the ultimate technology to side step Moore’s Law stagnation. Due to its nanoscale Monolithic Inter-tier Via (MIV), M3D enables an ultrahigh density interconnect between Logic and Memory that is required in the field of highly energy efficient 3D integrated circuits (3D-ICs) designed for new abundant data computing systems. At design level, M3D still suffers from a lack of commercial tools, especially for Place and Route, precluding the capability to provide signoff M3D GDS. In this paper, we introduce M3D-ADTCO, an architecture, design and technology co-optimization platform aimed at providing signoff M3D GDS. It relies on a M3D Process Design Kit and the use of a commercial Place and Route tool. We demonstrate an area reduction of 23.61% at iso performance and power compared to a 2D RISC-V micro-controller based System on Chip (SoC) while creating space to increase (2x) the RISC-V instruction memory.
Keywords: Monolithic 3D (M3D), Signoff Design Flow & Methodologies, CAD Tools, Process Design Kit.
