Synthesis of Fault-Tolerant Reconfigurable Scan Networks
Sebastian Brandhofera, Michael A. Kochteb and Hans-Joachim Wunderlichc
ITI, University of Stuttgart, Pfaffenwaldring 47, D-70569, Stuttgart, Germany
abrandhofer@iti.uni-stuttgart.de
bkochte@iti.uni-stuttgart.de
cwu@informatik.uni-stuttgart.de
ABSTRACT
On-chip instrumentation is mandatory for efficient bring-up, test and diagnosis, post-silicon validation, as well as in-field calibration, maintenance, and fault tolerance. Reconfigurable scan networks (RSNs) provide a scalable and efficient scan-based access mechanism to such instruments. The correct operation of this access mechanism is crucial for all manufacturing, bring-up and debug tasks as well as for in-field operation, but it can be affected by faults and design errors. This work develops for the first time fault-tolerant RSNs such that the resulting scan network still provides access to as many instruments as possible in presence of a fault. The work contributes a model and an algorithm to compute scan paths in faulty RSNs, a metric to quantify its fault tolerance and a synthesis algorithm that is based on graph connectivity and selective hardening of control logic in the scan network. Experimental results demonstrate that fault-tolerant RSNs can be synthesized with only moderate hardware overhead.
Keywords: Fault Tolerance, Reconfigurable Scan Network, IEEE Std 1687, iJTAG, On-Chip Infrastructure, DFT
