Delay Sensitivity Polynomials Based Design-Dependent Performance Monitors for Wide Operating Ranges
Ruikai Shi1,a, Liang Yang2,b and Hao Wang2,c
1State Key Laboratory of Computer Architecture, ICT, CAS University of Chinese Academy of Sciences Beijing, China
ashiruikai@loongson.cn
2Loongson Technology Co., Ltd Beijing, China
byangliang@loongson.cn
cwanghao@loongson.cn
ABSTRACT
The downsizing of CMOS technology makes circuit performance more sensitive to on-chip parameter variations. Previous proposed design-dependent ring oscillator (DDRO) method provides an efficient way to monitor circuit performance at runtime. However, the linear delay sensitivity expression may be inadequate, especially in a wide range of operating conditions. To overcome it, a new design-dependent performance monitor (DDPM) method is proposed in this work, which formulates the delay sensitivity as high-order polynomials, makes it possible to accurately track the nonlinear timing behavior for wide operating ranges. A 28nm technology is used for design evaluation, and quite a low error rate is achieved in circuit performance monitoring comparison.
Keywords: Performance Monitoring, Path delay Modeling, Frequency Estimation, Wide Operating Ranges
