High Density STT-MRAM compiler design, validation and characterization methodology in 28nm FDSOI technology
Piyush Jain1, Akshay Kumar1, Nicolaas Van Winkelhoff2, Didier Gayraud2, Surya Gupta1, Abdelali El Amraoui2, Giorgio Palma2, Alexandra Gourio2, Laurent Vachez2, Luc Palau,2 Jean-Christophe Buy2 and Cyrille Dray2
1ARM Embedded Technologies Pvt. Ltd Noida, India
2ARM France Sophia-Antipolis, France
ABSTRACT
Spin Transfer Torque Magneto-resistive Random- Access Memory (STT-MRAM) is emerging as a promising substitute for flash memories due to scaling challenges for flash in process nodes beyond 28nm. STT-MRAM’s high endurance, fast speed and low power makes it suitable for wide variety of applications. An embedded MRAM (eMRAM) compiler is highly desirable to enable SoC designers to use eMRAM instances in their designs in a flexible manner. However, the development of an eMRAM compiler has added challenges of handling multi-fold higher density and maintaining analog circuits accuracy, on top of the challenges associated with conventional SRAM memory compilers. In this paper, we present a successful design methodology for a high density 128Mb eMRAM compiler in a 28nm fully depleted SOI (FDSOI) process. This compiler enables optimized eMRAM instance generation with varying capacity ranges, word-widths, and optional features like repair and error correction. eMRAM compiler design is achieved by evolving various architecture design, validations and characterization methods. A hierarchical and modular characterization methodology is presented to enable high accuracy characterization and industry-standard EDA view generation from the eMRAM compiler.
Keywords: STT-MRAM, eMRAM, Memory Compiler, Characterization, Architecture.
