GPU-accelerated Time Simulation of Systems with Adaptive Voltage and Frequency Scaling
Eric Schneidera and Hans-Joachim Wunderlichb
University of Stuttgart, Pfaffenwaldring 47, 70569 Stuttgart, Germany
aschneiec@iti.uni-stuttgart.de
bwu@informatik.uni-stuttgart.de
ABSTRACT
Timing validation of systems with adaptive voltageand frequency scaling (AVFS) requires an accurate timing model under multiple operating points. Simulating such a model at gate level is extremely time-consuming, and the state-of-the-art compromises both accuracy and compute efficiency. This paper presents a method for dynamic gate delay modeling on graphics processing unit (GPU) accelerators which is based on polynomial approximation with offline statistical learning using regression analysis. It provides glitch-accurate switching activity information for gates and designs under varying supply voltages with negligible memory and performance impact. Parallelism from the evaluation of operating conditions, gates and stimuli is exploited simultaneously to utilize the high arithmetic computing throughput of GPUs. This way, large-scale design space exploration of AVFS-based systems is enabled. Experimental results demonstrate the efficiency and accuracy of the presented approach showing speedups of three orders of magnitude over conventional time simulation that supports static delays only.
Keywords: AVFS, Voltage-dependent delay, Logic level time simulation, GPU parallelization, Statistical learning
