Post-Silicon Validation of the IBM POWER9 Processor
Tom Kolan1,a, Hillel Mendelson1,b, Vitali Sokhin1,c, Kevin Reick2,d, Elena Tsanko2,e and Greg Wetli2,f
1IBM Research.
atomk@il.ibm.com
bhillelm@il.ibm.com
cvitali@il.ibm.com
2IBM Systems & Technology Group
dreick@us.ibm.com
eetsanko@us.ibm.com
fwetli@us.ibm.com
ABSTRACT
Due to the complexity of designs, post-silicon validation remains a major challenge with few systematic solutions. We provide an overview of the state-of-the-art post silicon validation process used by IBM to verify its latest IBM POWER9 processor. During the POWER9 post-silicon validation, we detected and handled 30% more logic bugs in 80% of the time, as compared to the previous IBM POWER8 bring-up. This improvement is the result of lessons learned from previous designs, leading to numerous innovations. We provide bug analysis data and compare it to POWER8 results.We demonstrate our methodology by describing several bugs from fail detection to root cause.
