Nano-Crossbar based Computing: Lessons Learned and Future Directions
Mustafa Altun1,a, Ismail Cevik1,b, Ahmet Erten1,c, Osman Eksik2, Mircea Stan3 and Csaba Andras Moritz4
1Department of Chemical Engineering, Istanbul Technical University, Istanbul, Turkey
aaltunmus@itu.edu.tr
bceviki@itu.edu.tr
caerten@itu.edu.tr
2Department of Electronics and Communication Engineering, Istanbul Technical University, Istanbul, Turkey
eksikos@itu.edu.tr
3Department of Electrical and Computer Engineering, University of Virginia, Virginia, USA
mircea@virginia.edu
4Department of Electrical and Computer Engineering, University of Massachusetts - Amherst, Massachusetts, USA
andras@ecs.umass.edu
ABSTRACT
In this paper, we first summarize our research activ-ities done through our European Union's Horizon-2020 project between 2015 and 2019. The project has a goal of developing synthesis and performance optimization techniques for nano-crossbar arrays. For this purpose, different computing models including diode, memristor, FET, and four-terminal switch based models, within different technologies including carbon nanotubes, nanowires, and memristors as well as the CMOS technology have been investigated. Their capabilities to realize logic functions and to tolerate faults have been deeply analyzed. From these experiences, we think that instead of replacing CMOS with a completely new crossbar based technology, developing CMOS compatible crossbar technologies and computing models is a more viable solution to overcome challenges in CMOS miniaturization. At this point, four-terminal switch based arrays, called switching lattices, come forward with their CMOS compatibility feature as well as with their area efficient device and circuit realizations. We have showed that switching lattices can be efficiently implemented using a standard CMOS process to implement logic functions by doing experiments in a 65nm CMOS process. Further in this paper, we make an introduction of realizing memory arrays with switching lattices including ROMs and RAMs. Also we discuss challenges and promises in realizing switching lattices for under 30nm CMOS technologies including FinFET technologies.
Keywords: Nano-Crossbar Array, Switching Lattice, Logic Synthesis, Fault Tolerance, Memory
