Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing
J.-P. Noel1,a, V. Egloff1, M. Kooli1, R. Gauchi1, J.-M. Portal2, H.-P. Charles1, P. Vivet1 and B. Giraud1
1 Univ. Grenoble Alpes, CEA, LIST, F-38000 Grenoble
2 Aix-Marseille Univ, Université de Toulon, CNRS, IM2NP, Marseille, France
ajean-philippe.noel@cea.fr
ABSTRACT
This paper presents a new methodology for automating the Computational SRAM (C-SRAM) design based on off-the-shelf memory compilers and a configurable RTL IP. The main goal is to drastically reduce the development effort compared to a full-custom design, while offering a flexibility of use and a high-yield production. The proposed C-SRAM architecture has been developed to process energy-efficient vector data coupled with a scalar processor, while limiting the data transfer on the system bus. The results obtained by post P&R simulations show that 2RW and 4RW C-SRAM configurations using the double pumping technique achieved the highest performance to process vectorized MAC operations compared to the others configurations. Moreover, it has been shown that the impact of the digital wrapper decoding and executing the instructions can be mitigated by increasing the memory cut size to represent less than 10% in area and 20% in power consumption.
