GraphRSim: A Joint Device-Algorithm Reliability Analysis for ReRAM-based Graph Processing
Chin-Fu Nien1,a, Yi-Jou Hsiao2, Hsiang-Yun Cheng1,b, Cheng-Yu Wen3,c, Ya-Cheng Ko3,d and Che-Ching Linz3,e
1Academia Sinica, Taiwan
awatchmannien@citi.sinica.edu.tw
birenegoldson.iie06g@nctu.edu.tw
2National Chiao Tung University, Taiwan
hycheng@citi.sinica.edu.tw
3National Taiwan University, Taiwan
cb05901048@ntu.edu.tw
db05902056@ntu.edu.tw
eb05901039@ntu.edu.tw
ABSTRACT
Graph processing has attracted a lot of interests in recent years as it plays a key role to analyze huge datasets. ReRAM-based accelerators provide a promising solution to accelerate graph processing. However, the intrinsic stochastic behavior of ReRAM devices makes its computation results unreliable. In this paper, we build a simulation platform to analyze the impact of non-ideal ReRAM devices on the error rates of various graph algorithms. We show that the characteristic of the targeted graph algorithm and the type of ReRAM computations employed greatly affect the error rates. Using representative graph algorithms as case studies, we demonstrate that our simulation platform can guide chip designers to select better design options and develop new techniques to improve reliability.
