Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes
Vladimir Herdt1,a, Daniel Große1,2,b and Rolf Drechsler1,2,c
1Institute of Computer Science, University of Bremen, 28359 Bremen, Germany
2Cyber-Physical Systems, DFKI GmbH, 28359 Bremen, Germany
avherdt@informatik.uni-bremen.de
bgrosse@informatik.uni-bremen.de
cdrechsle@informatik.uni-bremen.de
ABSTRACT
RISC-V is gaining huge popularity in particular for embedded systems. Recently, a SystemC-based Virtual Prototype (VP) has been open sourced to lay the foundation for providing support for system-level use cases such as design space exploration, analysis of complex HW/SW interactions and power/timing/performance validation for RISC-V based systems.
In this paper, we propose an efficient core timing model and integrate it into the VP core to enable fast and accurate performance evaluation for RISC-V based systems. As a case-study we provide a timing configuration matching the RISC-V HiFive1 board from SiFive. Our experiments demonstrate that our approach allows to obtain very accurate performance evaluation results while still retaining a high simulation performance.
