AstroByte: Multi-FPGA Architecture for Accelerated Simulations of Spiking Astrocyte Neural Networks
Shvan Karima, Jim Harkinb, Liam McDaidc, Bryan Gardinerd and Junxiu Liue
School of Computing, Engineering and Intelligent Systems Ulster University, Magee Campus, Derry, Northern Ireland, UK, BT48 7JL
ahaji_karim-s@ulster.ac.uk
bjg.harkin@ulster.ac.uk
clj.mcdaid@ulster.ac.uk
db.gardiner@ulster.ac.uk
ej.liu1@ulster.ac.uk
ABSTRACT
Spiking astrocyte neural networks (SANN) are a new computational paradigm that exhibit enhanced self-adapting and reliability properties. The inclusion of astrocyte behaviour increases the computational load and critically the number of connections, where each astrocyte typically communicates with up to 9 neurons (and their associated synapses) with feedback pathways from each neuron to the astrocyte. Each astrocyte cell also communicates with its neighbouring cell resulting in a significant interconnect density. The substantial level of parallelisms in SANNs lends itself to acceleration in hardware, however, the challenge in accelerating simulations of SANNs firmly resides in scalable interconnect and the ability to inject and retrieve data from the hardware. This paper presents a novel multi-FPGA acceleration architecture, AstroByte, for the speedup of SANNs. AstroByte explores Networks-on-Chip (NoC) routing mechanisms to address the challenge of communicating both spike event (neuron data) and numeric (astrocyte data) across significant interconnect pathways between astrocytes and neurons. AstroByte also exploits the NoC interconnect to inject data and retrieve runtime data from the accelerated SANN simulations. Results show that AstroByte can simulate SANN applications with speedup factors of between x162 -x188 over Matlab equivalent simulations.
Keywords: FPGA Acceleration, Multi-FPGA, Data acquisition, Networks on Chip, NoC, Astrocyte, SNN
