A Method of Via Variation Induced Delay Computation
Moonsu Kim1, Yun Heo1, Seungjae Jung2, Kelvin Le3, Nathaniel Conos3, Hanif Fatemi3, Jongpil Lee1 and Youngmin Shin1
1Design Technology Team, System LSI Business, Samsung Electronics, Korea
2Design Enablement Team, Foundry Business, Samsung Electronics, Korea
3Synopsys Inc., USA
ABSTRACT
As process technologies are scaled down, interconnect delay becomes major component of entire path delay, and vias represent a significant portion of the interconnect delay. In this paper, a novel variation-aware delay computation method for vias is proposed. Our experiments show that this method can reduce over five percent of pessimism in arrival time calculation when it is compared with state-of-the-art solutions.
Keywords: Static Timing Analysis, STA, via, Resistance, Random Variation, Statistical Static Timing Analysis, SSTA.
