Prospector: Synthesizing Efficient Accelerators via Statistical Learning
Atefeh Mehrabi1,a, Aninda Manocha2, Benjamin C. Lee1,b and Daniel J. Sorin1,c
1Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA
aatefeh.mehrabi@duke.edu
bbenjamin.c.lee@duke.edu
csorin@ee.duke.edu
2Department of Computer Science, Princeton University, Princeton, NJ, USA
amanocha@princeton.edu
ABSTRACT
Accelerator design is expensive due to the effort required to understand an algorithm and optimize the design. Architects have embraced two technologies to reduce costs. Highlevel synthesis automatically generates hardware from code. Reconfigurable fabrics instantiate accelerators while avoiding fabrication costs for custom circuits. We further reduce design effort with statistical learning. We build an automated framework, called Prospector, that uses Bayesian techniques to optimize synthesis directives, reducing execution latency and resource usage in field-programmable gate arrays. We show in a certain amount of time designs discovered by Prospector are closer to Pareto-efficient designs compared to prior approaches.
Keywords: High-level synthesis, design space exploration, FPGA, Bayesian optimization
