TRANSPIRE: An Energy-efficient TRANSprecision Floating-point Programmable archItectuRE
Rohit Prasad1,2,a, Satyajit Das4, Kevin J. M. Martin1,b, Giuseppe Tagliavini2,d, Philippe Coussy1,c, Luca Benini2,3 and Davide Rossi2,e
1Univ. Bretagne-Sud, UMR 6285, Lab-STICC, F-56100 Lorient, France
aRohit.Prasad@univ-ubs.fr
bKevin.J. M. Martin@univ-ubs.fr
cPhilippe.Coussy@univ-ubs.fr
2Electrical, Electronic, and Information Engineering, University of Bologna, Italy
dGiuseppe.Tagliavini@unibo.it
eDavide.Rossi@unibo.it
3Integrated Systems Laboratory, ETH Zurich, Switzerland
L.Benini@iis.ee.ethz.ch
4Department of Computer Science and Engineering, IIT Palakkad, India
satyajitdas@iitkpd.ac.in
ABSTRACT
In recent years, Coarse Grain Reconfigurable Architecture (CGRA) accelerators have been increasingly deployed in Internet-of-Things (IoT) end nodes. A modern CGRA has to support and efficiently accelerate both integer and floating-point (FP) operations. In this paper, we propose an ultra-low-power tunableprecision CGRA architectural template, called TRANSprecision floating-point Programmable archItectuRE (TRANSPIRE), and its associated compilation flow supporting both integer and FP operations. TRANSPIRE employs transprecision computing and multiple Single Instruction Multiple Data (SIMD) to accelerate FP operations while boosting energy efficiency as well. Experimental results show that TRANSPIRE achieves a maximum of 10:06× performance gain and consumes 12:91× less energy w.r.t. a RISC-V based CPU with an enhanced ISA supporting SIMD-style vectorization and FP data-types, while executing applications for near-sensor computing and embedded machine learning, with an area overhead of 1:25× only.
