High-Speed Analog Simulation of CMOS Vision Chips Using Explicit Integration Techniques on Many-Core Processors
Gines Domenech-Asensi1 and Tom J. Kazmierski2
1Dpt. de Electrónica, Téc. de Computadoras y Proyectos Universidad Politécnica de Cartagena Cartagena, Spain
gines.domenech@upct.es
2University of Southampton Southampton, United Kingdom
tjk@ecs.soton.ac.uk
ABSTRACT
This work describes a high-speed simulation technique of analog circuits which is based on the use of statespace equations and an explicit integration method parallelised on a multiprocessor architecture. The integration step of such method is smaller than the one required by an implicit simulation technique based on Newton–Raphson iterations. However, given that explicit methods do not require the computation of timeconsuming matrix factorizations, the overall simulation time is reduced. The technique described in this work has been implemented on a NVIDIA general purpose GPU and has been tested simulating the Gaussian filtering operation performed by a smart CMOS image sensor. Such devices are used to perform computation on the edge and include built-in image processing functions. Among those, the Gaussian filtering is one of the most common functions, since it is a basic task for early vision processing. These smart sensors are increasingly complex and hence the time required to simulate them during their design cycle is also larger and larger. From a certain imager size, the proposed simulation method yields simulation times two order of magnitude faster that an implicit method based tool such us SPICE.
Keywords: Simulation Acceleration, State-Space Technique, Nany-Core, GPU, CMOS imager.
