Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning
Mingjie Liua, Keren Zhub, Jiaqi Guc, Linxiao Shend, Xiyuan Tange, Nan Sunf and David Z. Pang
ECE Department, The University of Texas at Austin, Austin, TX, USA
ajay_liu@utexas.edu
bkeren.zhu@utexas.edu
cjqgu@utexas.edu
dlynn.shenlx@utexas.edu
exitang@utexas.edu
fnansun@mail.utexas.edu
gdpan@ece.utexas.edu
ABSTRACT
Despite tremendous efforts in analog layout automation, little adoption has been demonstrated in practical design flows. Traditional analog layout synthesis tools use various heuristic constraints to prune the design space to ensure post layout performance. However, these approaches provide limited guarantee and poor generalizability due to a lack of model mapping layout properties to circuit performance. In this paper, we attempt to shorten the gap in post layout performance modeling for analog circuits with a quantitative statistical approach. We leverage a state-of-the-art automatic analog layout tool and industry-level simulator to generate labeled training data in an automated manner. We propose a 3D convolutional neural network (CNN) model to predict the relative placement quality using well-crafted placement features. To achieve data-efficiency for practical usage, we further propose a transfer learning scheme that greatly reduces the amount of data needed. Our model would enable early pruning and efficient design explorations for practical layout design flows. Experimental results demonstrate the effectiveness and generalizability of our method across different operational transconductance amplifier (OTA) designs.
