Fast and Accurate DRAM Simulation: Can we Further Accelerate it?
Johannes Feldmann1,a, Kira Kraft1,b, Lukas Steiner1,c, Norbert Wehn1 and Matthias Jung2
1Microelectronic Systems Design Research Group Technische Universität Kaiserslautern Kaiserslautern, Germany
afeldmann@eit.uni-kl.de
bkraft@eit.uni-kl.de
cwehn@eit.uni-kl.de
2Embedded Systems Division Fraunhofer IESE Kaiserslautern, Germany
matthias.jung@iese.fraunhofer.de
ABSTRACT
The simulation of Dynamic Random Access Memories (DRAMs) in a system context requires highly accurate models due to the complex timing and power behavior of DRAMs. However, cycle accurate DRAM models often become the bottleneck regarding the overall simulation time. Therefore, fast but accurate DRAM simulation models are mandatory. This paper proposes two new performance optimized DRAM models that further accelerate the simulation speed with only a negligible degradation in accuracy. The first model is an enhanced Transaction Level Model (TLM), which uses a look-up table to accelerate parts of the simulation that feature a high memory access density for online scenarios. The second model is a neural network based simulator for offline trace analysis. We show a mathematical methodology to generate the inputs for the Look- Up Table (LUT) and an optimized artificial training set for the neural network. The enhanced TLM model is up to 5 times faster compared to a state-of-the-art TLM DRAM simulator. The neural network is able to speed up the simulation up to a factor of 10⨯, while inferring on a GPU. Both solutions provide only a slight decrease in accuracy of approximately 5%.
Keywords: DRAM, Simulation Acceleration, Neural Networks.
